2 menuconfig MTD_RAW_NAND
3 bool "Raw NAND Device Support"
6 config SYS_NAND_SELF_INIT
9 This option, if enabled, provides more flexible and linux-like
10 NAND initialization process.
12 config SPL_SYS_NAND_SELF_INIT
14 depends on !SPL_NAND_SIMPLE
16 This option, if enabled, provides more flexible and linux-like
17 NAND initialization process, in SPL.
19 config TPL_SYS_NAND_SELF_INIT
21 depends on TPL_NAND_SUPPORT
23 This option, if enabled, provides more flexible and linux-like
24 NAND initialization process, in SPL.
26 config SYS_NAND_DRIVER_ECC_LAYOUT
27 bool "Omit standard ECC layouts to save space"
29 Omit standard ECC layouts to save space. Select this if your driver
30 is known to provide its own ECC layout.
32 config SYS_NAND_USE_FLASH_BBT
33 bool "Enable BBT (Bad Block Table) support"
35 Enable the BBT (Bad Block Table) usage.
38 bool "Support Atmel NAND controller"
39 select SYS_NAND_SELF_INIT
40 imply SYS_NAND_USE_FLASH_BBT
42 Enable this driver for NAND flash platforms using an Atmel NAND
47 config ATMEL_NAND_HWECC
48 bool "Atmel Hardware ECC"
50 config ATMEL_NAND_HW_PMECC
51 bool "Atmel Programmable Multibit ECC (PMECC)"
52 select ATMEL_NAND_HWECC
54 The Programmable Multibit ECC (PMECC) controller is a programmable
55 binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder.
58 int "PMECC Correctable ECC Bits"
59 depends on ATMEL_NAND_HW_PMECC
62 Correctable ECC bits, can be 2, 4, 8, 12, and 24.
64 config PMECC_SECTOR_SIZE
65 int "PMECC Sector Size"
66 depends on ATMEL_NAND_HW_PMECC
69 Sector size, in bytes, can be 512 or 1024.
71 config SPL_GENERATE_ATMEL_PMECC_HEADER
72 bool "Atmel PMECC Header Generation"
73 select ATMEL_NAND_HWECC
74 select ATMEL_NAND_HW_PMECC
76 Generate Programmable Multibit ECC (PMECC) header for SPL image.
81 bool "Support Broadcom NAND controller"
82 depends on OF_CONTROL && DM && DM_MTD
83 select SYS_NAND_SELF_INIT
85 Enable the driver for NAND flash on platforms using a Broadcom NAND
88 config NAND_BRCMNAND_6368
89 bool "Support Broadcom NAND controller on bcm6368"
90 depends on NAND_BRCMNAND && ARCH_BMIPS
92 Enable support for broadcom nand driver on bcm6368.
94 config NAND_BRCMNAND_6753
95 bool "Support Broadcom NAND controller on bcm6753"
96 depends on NAND_BRCMNAND && ARCH_BCM6753
98 Enable support for broadcom nand driver on bcm6753.
100 config NAND_BRCMNAND_68360
101 bool "Support Broadcom NAND controller on bcm68360"
102 depends on NAND_BRCMNAND && ARCH_BCM68360
104 Enable support for broadcom nand driver on bcm68360.
106 config NAND_BRCMNAND_6838
107 bool "Support Broadcom NAND controller on bcm6838"
108 depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838
110 Enable support for broadcom nand driver on bcm6838.
112 config NAND_BRCMNAND_6858
113 bool "Support Broadcom NAND controller on bcm6858"
114 depends on NAND_BRCMNAND && ARCH_BCM6858
116 Enable support for broadcom nand driver on bcm6858.
118 config NAND_BRCMNAND_63158
119 bool "Support Broadcom NAND controller on bcm63158"
120 depends on NAND_BRCMNAND && ARCH_BCM63158
122 Enable support for broadcom nand driver on bcm63158.
125 bool "Support TI Davinci NAND controller"
126 select SYS_NAND_SELF_INIT if TARGET_DA850EVM
128 Enable this driver for NAND flash controllers available in TI Davinci
129 and Keystone2 platforms
131 config KEYSTONE_RBL_NAND
132 depends on ARCH_KEYSTONE
137 depends on NAND_DAVINCI && ARCH_DAVINCI && SPL_NAND_SUPPORT
141 select SYS_NAND_SELF_INIT
144 config NAND_DENALI_DT
145 bool "Support Denali NAND controller as a DT device"
147 depends on OF_CONTROL && DM_MTD
149 Enable the driver for NAND flash on platforms using a Denali NAND
150 controller as a DT device.
153 bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver"
154 select TPL_SYS_NAND_SELF_INIT if TPL_NAND_SUPPORT
155 select SPL_SYS_NAND_SELF_INIT
156 select SYS_NAND_SELF_INIT
159 Enable the Freescale Enhanced Local Bus Controller FCM NAND driver.
162 bool "Support Freescale Integrated Flash Controller NAND driver"
163 select TPL_SYS_NAND_SELF_INIT if TPL_NAND_SUPPORT
164 select SPL_SYS_NAND_SELF_INIT
165 select SYS_NAND_SELF_INIT
168 Enable the Freescale Integrated Flash Controller NAND driver.
170 config NAND_LPC32XX_MLC
171 bool "Support LPC32XX_MLC controller"
172 select SYS_NAND_SELF_INIT
174 Enable the LPC32XX MLC NAND controller.
176 config NAND_LPC32XX_SLC
177 bool "Support LPC32XX_SLC controller"
179 Enable the LPC32XX SLC NAND controller.
181 config NAND_OMAP_GPMC
182 bool "Support OMAP GPMC NAND controller"
183 depends on ARCH_OMAP2PLUS
185 Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
186 GPMC controller is used for parallel NAND flash devices, and can
187 do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
188 and BCH16 ECC algorithms.
192 config NAND_OMAP_GPMC_PREFETCH
193 bool "Enable GPMC Prefetch"
196 On OMAP platforms that use the GPMC controller
197 (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
198 uses the prefetch mode to speed up read operations.
201 bool "Enable ELM driver for OMAPxx and AMxx platforms."
204 ELM controller is used for ECC error detection (not ECC calculation)
205 of BCH4, BCH8 and BCH16 ECC algorithms.
206 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
207 thus such SoC platforms need to depend on software library for ECC error
208 detection. However ECC calculation on such plaforms would still be
209 done by GPMC controller.
213 default NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
215 On OMAP platforms, this CONFIG specifies NAND ECC scheme.
216 It can take following values:
217 OMAP_ECC_HAM1_CODE_SW
218 1-bit Hamming code using software lib.
219 (for legacy devices only)
220 OMAP_ECC_HAM1_CODE_HW
221 1-bit Hamming code using GPMC hardware.
222 (for legacy devices only)
223 OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
224 4-bit BCH code (unsupported)
225 OMAP_ECC_BCH4_CODE_HW
226 4-bit BCH code (unsupported)
227 OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
229 - ecc calculation using GPMC hardware engine,
230 - error detection using software library.
231 - requires CONFIG_BCH to enable software BCH library
232 (For legacy device which do not have ELM h/w engine)
233 OMAP_ECC_BCH8_CODE_HW
235 - ecc calculation using GPMC hardware engine,
236 - error detection using ELM hardware engine.
237 OMAP_ECC_BCH16_CODE_HW
239 - ecc calculation using GPMC hardware engine,
240 - error detection using ELM hardware engine.
242 How to select ECC scheme on OMAP and AMxx platforms ?
243 -----------------------------------------------------
244 Though higher ECC schemes have more capability to detect and correct
245 bit-flips, but still selection of ECC scheme is dependent on following
246 - hardware engines present in SoC.
247 Some legacy OMAP SoC do not have ELM h/w engine thus such
248 SoC cannot support BCHx_HW ECC schemes.
249 - size of OOB/Spare region
250 With higher ECC schemes, more OOB/Spare area is required to
251 store ECC. So choice of ECC scheme is limited by NAND oobsize.
253 In general following expression can help:
254 NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES
256 NAND_OOBSIZE = number of bytes available in
257 OOB/spare area per NAND page.
258 NAND_PAGESIZE = bytes in main-area of NAND page.
259 ECC_BYTES = number of ECC bytes generated to
260 protect 512 bytes of data, which is:
261 3 for HAM1_xx ecc schemes
262 7 for BCH4_xx ecc schemes
263 14 for BCH8_xx ecc schemes
264 26 for BCH16_xx ecc schemes
266 example to check for BCH16 on 2K page NAND
269 2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE
270 Thus BCH16 cannot be supported on 2K page NAND.
272 However, for 4K pagesize NAND
276 2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE
277 Thus BCH16 can be supported on 4K page NAND.
279 config NAND_OMAP_ECCSCHEME_HAM1_CODE_SW
280 bool "1-bit Hamming code using software lib"
282 config NAND_OMAP_ECCSCHEME_HAM1_CODE_HW
283 bool "1-bit Hamming code using GPMC hardware"
285 config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW
286 bool "8-bit BCH code with HW calculation SW error detection"
288 config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
289 bool "8-bit BCH code with HW calculation and error detection"
291 config NAND_OMAP_ECCSCHEME_BCH16_CODE_HW
292 bool "16-bit BCH code with HW calculation and error detection"
296 config NAND_OMAP_ECCSCHEME
298 default 1 if NAND_OMAP_ECCSCHEME_HAM1_CODE_SW
299 default 2 if NAND_OMAP_ECCSCHEME_HAM1_CODE_HW
300 default 5 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW
301 default 6 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
302 default 7 if NAND_OMAP_ECCSCHEME_BCH16_CODE_HW
304 This must be kept in sync with the enum in
305 include/linux/mtd/omap_gpmc.h
309 config NAND_VF610_NFC
310 bool "Support for Freescale NFC for VF610"
311 select SYS_NAND_SELF_INIT
312 select SYS_NAND_DRIVER_ECC_LAYOUT
315 Enables support for NAND Flash Controller on some Freescale
316 processors like the VF610, MCF54418 or Kinetis K70.
317 The driver supports a maximum 2k page size. The driver
318 currently does not support hardware ECC.
322 config NAND_VF610_NFC_DT
323 bool "Support Vybrid's vf610 NAND controller as a DT device"
324 depends on OF_CONTROL && DM_MTD
326 Enable the driver for Vybrid's vf610 NAND flash on platforms
330 prompt "Hardware ECC strength"
331 depends on NAND_VF610_NFC
332 default SYS_NAND_VF610_NFC_45_ECC_BYTES
334 Select the ECC strength used in the hardware BCH ECC block.
336 config SYS_NAND_VF610_NFC_45_ECC_BYTES
337 bool "24-error correction (45 ECC bytes)"
339 config SYS_NAND_VF610_NFC_60_ECC_BYTES
340 bool "32-error correction (60 ECC bytes)"
347 bool "Support for NAND on PXA3xx and Armada 370/XP/38x"
348 select SYS_NAND_SELF_INIT
354 This enables the driver for the NAND flash device found on
355 PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
358 bool "Support for NAND on Allwinner SoCs"
360 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I
361 select SYS_NAND_SELF_INIT
362 select SYS_NAND_U_BOOT_LOCATIONS
363 select SPL_NAND_SUPPORT
364 select SPL_SYS_NAND_SELF_INIT
367 Enable support for NAND. This option enables the standard and
369 The SPL driver only supports reading from the NAND using DMA
374 config NAND_SUNXI_SPL_ECC_STRENGTH
375 int "Allwinner NAND SPL ECC Strength"
378 config NAND_SUNXI_SPL_ECC_SIZE
379 int "Allwinner NAND SPL ECC Step Size"
382 config NAND_SUNXI_SPL_USABLE_PAGE_SIZE
383 int "Allwinner NAND SPL Usable Page Size"
389 bool "Configure Arasan Nand"
390 select SYS_NAND_SELF_INIT
394 This enables Nand driver support for Arasan nand flash
395 controller. This uses the hardware ECC for read and
399 bool "MXC NAND support"
400 depends on CPU_ARM926EJS || CPU_ARM1136 || MX5
403 This enables the NAND driver for the NAND flash controller on the
404 i.MX27 / i.MX31 / i.MX5 processors.
407 bool "MXS NAND support"
408 depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M
409 select SPL_SYS_NAND_SELF_INIT
410 select SYS_NAND_SELF_INIT
413 select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
414 select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
416 This enables NAND driver for the NAND flash controller on the
422 bool "Support MXS NAND controller as a DT device"
423 depends on OF_CONTROL && DM_MTD
425 Enable the driver for MXS NAND flash on platforms using
428 config NAND_MXS_USE_MINIMUM_ECC
429 bool "Use minimum ECC strength supported by the controller"
435 bool "Macronix raw NAND controller"
436 select SYS_NAND_SELF_INIT
438 This selects the Macronix raw NAND controller driver.
441 bool "Support for Zynq Nand controller"
442 select SPL_SYS_NAND_SELF_INIT
443 select SYS_NAND_SELF_INIT
447 This enables Nand driver support for Nand flash controller
450 config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
451 bool "Enable use of 1st stage bootloader timing for NAND"
454 This flag prevent U-boot reconfigure NAND flash controller and reuse
455 the NAND timing from 1st stage bootloader.
458 bool "Support for OcteonTX NAND controller"
459 select SYS_NAND_SELF_INIT
462 This enables Nand flash controller hardware found on the OcteonTX
465 config NAND_OCTEONTX_HW_ECC
466 bool "Support Hardware ECC for OcteonTX NAND controller"
467 depends on NAND_OCTEONTX
470 This enables Hardware BCH engine found on the OcteonTX processors to
471 support ECC for NAND flash controller.
473 config NAND_STM32_FMC2
474 bool "Support for NAND controller on STM32MP SoCs"
475 depends on ARCH_STM32MP
476 select SYS_NAND_SELF_INIT
479 Enables support for NAND Flash chips on SoCs containing the FMC2
480 NAND controller. This controller is found on STM32MP SoCs.
481 The controller supports a maximum 8k page size and supports
482 a maximum 8-bit correction error per sector of 512 bytes.
485 bool "Support for NAND controller on Cortina-Access SoCs"
486 depends on CORTINA_PLATFORM
487 select SYS_NAND_SELF_INIT
491 Enables support for NAND Flash chips on Coartina-Access SoCs platform
492 This controller is found on Presidio/Venus SoCs.
493 The controller supports a maximum 8k page size and supports
494 a maximum 40-bit error correction per sector of 1024 bytes.
497 bool "Support for NAND controller on Rockchip SoCs"
498 depends on ARCH_ROCKCHIP
499 select SYS_NAND_SELF_INIT
503 Enables support for NAND Flash chips on Rockchip SoCs platform.
504 This controller is found on Rockchip SoCs.
505 There are four different versions of NAND FLASH Controllers,
507 NFC v600: RK2928, RK3066, RK3188
508 NFC v622: RK3036, RK3128
509 NFC v800: RK3308, RV1108
510 NFC v900: PX30, RK3326
513 bool "Support for NAND controller on Tegra SoCs"
514 depends on ARCH_TEGRA
515 select SYS_NAND_SELF_INIT
518 Enables support for NAND Flash chips on Tegra SoCs platforms.
520 comment "Generic NAND options"
522 config SYS_NAND_BLOCK_SIZE
523 hex "NAND chip eraseblock size"
524 depends on ARCH_SUNXI || SPL_NAND_SUPPORT || TPL_NAND_SUPPORT
525 depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && !NAND_FSL_IFC
527 Number of data bytes in one eraseblock for the NAND chip on the
528 board. This is the multiple of NAND_PAGE_SIZE and the number of
531 config SYS_NAND_ONFI_DETECTION
532 bool "Enable detection of ONFI compliant devices during probe"
534 Enables detection of ONFI compliant devices during probe.
535 And fetching device parameters flashed on device, by parsing
538 config SYS_NAND_PAGE_COUNT
539 hex "NAND chip page count"
540 depends on SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC || \
541 SPL_NAND_AM33XX_BCH || SPL_NAND_LOAD || SPL_NAND_SIMPLE)
543 Number of pages in the NAND chip.
545 config SYS_NAND_PAGE_SIZE
546 hex "NAND chip page size"
547 depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
548 SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
549 (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
550 depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
552 Number of data bytes in one page for the NAND chip on the
553 board, not including the OOB area.
555 config SYS_NAND_OOBSIZE
556 hex "NAND chip OOB size"
557 depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
558 SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
559 (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
560 depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
562 Number of bytes in the Out-Of-Band area for the NAND chip on
565 # Enhance depends when converting drivers to Kconfig which use this config
566 # option (mxc_nand, ndfc, omap_gpmc).
567 config SYS_NAND_BUSWIDTH_16BIT
568 bool "Use 16-bit NAND interface"
569 depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI
571 Indicates that NAND device has 16-bit wide data-bus. In absence of this
572 config, bus-width of NAND device is assumed to be either 8-bit and later
573 determined by reading ONFI params.
574 Above config is useful when NAND device's bus-width information cannot
575 be determined from on-chip ONFI params, like in following scenarios:
576 - SPL boot does not support reading of ONFI parameters. This is done to
577 keep SPL code foot-print small.
578 - In current U-Boot flow using nand_init(), driver initialization
579 happens in board_nand_init() which is called before any device probe
580 (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are
581 not available while configuring controller. So a static CONFIG_NAND_xx
582 is needed to know the device's bus-width in advance.
586 config SYS_NAND_5_ADDR_CYCLE
587 bool "Wait 5 address cycles during NAND commands"
588 depends on SPL_NAND_AM33XX_BCH || SPL_NAND_SIMPLE || \
589 (SPL_NAND_SUPPORT && NAND_ATMEL)
592 Some controllers require waiting for 5 address cycles when issuing
593 some commands, on NAND chips larger than 128MiB.
596 prompt "NAND bad block marker/indicator position in the OOB"
597 depends on SPL_NAND_AM33XX_BCH || SPL_NAND_DENALI || SPL_NAND_SIMPLE || \
598 SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC)
599 default HAS_NAND_LARGE_BADBLOCK_POS
601 In the OOB, which position contains the badblock information.
603 config HAS_NAND_LARGE_BADBLOCK_POS
604 bool "Set the bad block marker/indicator to the 'large' position"
606 config HAS_NAND_SMALL_BADBLOCK_POS
607 bool "Set the bad block marker/indicator to the 'small' position"
611 config SYS_NAND_BAD_BLOCK_POS
613 default 0 if HAS_NAND_LARGE_BADBLOCK_POS
614 default 5 if HAS_NAND_SMALL_BADBLOCK_POS
616 config SYS_NAND_U_BOOT_LOCATIONS
617 bool "Define U-boot binaries locations in NAND"
619 Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig.
620 This option should not be enabled when compiling U-boot for boards
621 defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h
624 config SYS_NAND_U_BOOT_OFFS
625 hex "Location in NAND to read U-Boot from"
626 default 0x800000 if NAND_SUNXI
627 depends on SYS_NAND_U_BOOT_LOCATIONS
629 Set the offset from the start of the nand where u-boot should be
632 config SYS_NAND_U_BOOT_OFFS_REDUND
633 hex "Location in NAND to read U-Boot from"
634 default SYS_NAND_U_BOOT_OFFS
635 depends on SYS_NAND_U_BOOT_LOCATIONS
637 Set the offset from the start of the nand where the redundant u-boot
638 should be loaded from.
640 config SPL_NAND_AM33XX_BCH
641 bool "Enables SPL-NAND driver which supports ELM based"
642 depends on NAND_OMAP_GPMC && !OMAP34XX
645 Hardware ECC correction. This is useful for platforms which have ELM
646 hardware engine and use NAND boot mode.
647 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
648 so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
649 SPL-NAND driver with software ECC correction support.
651 config SPL_NAND_DENALI
652 bool "Support Denali NAND controller for SPL"
654 This is a small implementation of the Denali NAND controller
657 config NAND_DENALI_SPARE_AREA_SKIP_BYTES
658 int "Number of bytes skipped in OOB area"
659 depends on SPL_NAND_DENALI
662 This option specifies the number of bytes to skip from the beginning
663 of OOB area before last ECC sector data starts. This is potentially
664 used to preserve the bad block marker in the OOB area.
666 config SPL_NAND_SIMPLE
667 bool "Use simple SPL NAND driver"
668 depends on !SPL_NAND_AM33XX_BCH
670 Support for NAND boot using simple NAND drivers that
671 expose the cmd_ctrl() interface.