2 menuconfig MTD_RAW_NAND
3 bool "Raw NAND Device Support"
6 config SYS_NAND_SELF_INIT
9 This option, if enabled, provides more flexible and linux-like
10 NAND initialization process.
12 config SPL_SYS_NAND_SELF_INIT
14 depends on !SPL_NAND_SIMPLE
16 This option, if enabled, provides more flexible and linux-like
17 NAND initialization process, in SPL.
19 config TPL_SYS_NAND_SELF_INIT
21 depends on TPL_NAND_SUPPORT
23 This option, if enabled, provides more flexible and linux-like
24 NAND initialization process, in SPL.
29 config SYS_MAX_NAND_DEVICE
30 int "Maximum number of NAND devices to support"
33 config SYS_NAND_DRIVER_ECC_LAYOUT
34 bool "Omit standard ECC layouts to save space"
36 Omit standard ECC layouts to save space. Select this if your driver
37 is known to provide its own ECC layout.
39 config SYS_NAND_USE_FLASH_BBT
40 bool "Enable BBT (Bad Block Table) support"
42 Enable the BBT (Bad Block Table) usage.
44 config SYS_NAND_NO_SUBPAGE_WRITE
45 bool "Disable subpage write support"
46 depends on NAND_ARASAN || NAND_DAVINCI || NAND_KIRKWOOD
49 bool "Support Atmel NAND controller"
50 select SYS_NAND_SELF_INIT
51 imply SYS_NAND_USE_FLASH_BBT
53 Enable this driver for NAND flash platforms using an Atmel NAND
58 config ATMEL_NAND_HWECC
59 bool "Atmel Hardware ECC"
61 config ATMEL_NAND_HW_PMECC
62 bool "Atmel Programmable Multibit ECC (PMECC)"
63 select ATMEL_NAND_HWECC
65 The Programmable Multibit ECC (PMECC) controller is a programmable
66 binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder.
69 int "PMECC Correctable ECC Bits"
70 depends on ATMEL_NAND_HW_PMECC
73 Correctable ECC bits, can be 2, 4, 8, 12, and 24.
75 config PMECC_SECTOR_SIZE
76 int "PMECC Sector Size"
77 depends on ATMEL_NAND_HW_PMECC
80 Sector size, in bytes, can be 512 or 1024.
82 config SPL_GENERATE_ATMEL_PMECC_HEADER
83 bool "Atmel PMECC Header Generation"
85 select ATMEL_NAND_HWECC
86 select ATMEL_NAND_HW_PMECC
88 Generate Programmable Multibit ECC (PMECC) header for SPL image.
91 prompt "NAND bus width (bits)"
92 default SYS_NAND_DBW_8
95 bool "NAND bus width is 8 bits"
97 config SYS_NAND_DBW_16
98 bool "NAND bus width is 16 bits"
105 bool "Support Broadcom NAND controller"
106 depends on OF_CONTROL && DM && DM_MTD
107 select SYS_NAND_SELF_INIT
109 Enable the driver for NAND flash on platforms using a Broadcom NAND
112 config NAND_BRCMNAND_6368
113 bool "Support Broadcom NAND controller on bcm6368"
114 depends on NAND_BRCMNAND && ARCH_BMIPS
116 Enable support for broadcom nand driver on bcm6368.
118 config NAND_BRCMNAND_6753
119 bool "Support Broadcom NAND controller on bcm6753"
120 depends on NAND_BRCMNAND && BCM6855
122 Enable support for broadcom nand driver on bcm6753.
124 config NAND_BRCMNAND_68360
125 bool "Support Broadcom NAND controller on bcm68360"
126 depends on NAND_BRCMNAND && BCM6856
128 Enable support for broadcom nand driver on bcm68360.
130 config NAND_BRCMNAND_6838
131 bool "Support Broadcom NAND controller on bcm6838"
132 depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838
134 Enable support for broadcom nand driver on bcm6838.
136 config NAND_BRCMNAND_6858
137 bool "Support Broadcom NAND controller on bcm6858"
138 depends on NAND_BRCMNAND && BCM6858
140 Enable support for broadcom nand driver on bcm6858.
142 config NAND_BRCMNAND_63158
143 bool "Support Broadcom NAND controller on bcm63158"
144 depends on NAND_BRCMNAND && BCM63158
146 Enable support for broadcom nand driver on bcm63158.
149 bool "Support TI Davinci NAND controller"
150 select SYS_NAND_SELF_INIT if TARGET_DA850EVM
152 Enable this driver for NAND flash controllers available in TI Davinci
153 and Keystone2 platforms
156 prompt "Type of ECC used on NAND"
157 default SYS_NAND_4BIT_HW_ECC_OOBFIRST
158 depends on NAND_DAVINCI
160 config SYS_NAND_HW_ECC
161 bool "Use 1-bit HW ECC"
163 config SYS_NAND_4BIT_HW_ECC_OOBFIRST
164 bool "Use 4-bit HW ECC with OOB at the front"
166 config SYS_NAND_SOFT_ECC
167 bool "Use software ECC"
172 prompt "NAND page size"
173 depends on NAND_DAVINCI
174 default SYS_NAND_PAGE_2K
176 config SYS_NAND_PAGE_2K
177 bool "Page size is 2K"
179 config SYS_NAND_PAGE_4K
180 bool "Page size is 4K"
184 config KEYSTONE_RBL_NAND
185 depends on ARCH_KEYSTONE
190 depends on NAND_DAVINCI && ARCH_DAVINCI && SPL_NAND_SUPPORT
194 select SYS_NAND_SELF_INIT
197 config NAND_DENALI_DT
198 bool "Support Denali NAND controller as a DT device"
200 depends on OF_CONTROL && DM_MTD
202 Enable the driver for NAND flash on platforms using a Denali NAND
203 controller as a DT device.
206 bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver"
207 select TPL_SYS_NAND_SELF_INIT if TPL_NAND_SUPPORT
208 select SPL_SYS_NAND_SELF_INIT
209 select SYS_NAND_SELF_INIT
212 Enable the Freescale Enhanced Local Bus Controller FCM NAND driver.
214 config NAND_FSL_ELBC_DT
215 bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver (DT mode)"
216 depends on NAND_FSL_ELBC
219 bool "Support Freescale Integrated Flash Controller NAND driver"
220 select TPL_SYS_NAND_SELF_INIT if TPL_NAND_SUPPORT
221 select TPL_NAND_INIT if TPL && !TPL_FRAMEWORK
222 select SPL_SYS_NAND_SELF_INIT
223 select SYS_NAND_SELF_INIT
226 Enable the Freescale Integrated Flash Controller NAND driver.
228 config NAND_LPC32XX_MLC
229 bool "Support LPC32XX_MLC controller"
230 select SYS_NAND_SELF_INIT
232 Enable the LPC32XX MLC NAND controller.
234 config NAND_LPC32XX_SLC
235 bool "Support LPC32XX_SLC controller"
237 Enable the LPC32XX SLC NAND controller.
239 config NAND_OMAP_GPMC
240 bool "Support OMAP GPMC NAND controller"
241 depends on ARCH_OMAP2PLUS
243 Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
244 GPMC controller is used for parallel NAND flash devices, and can
245 do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
246 and BCH16 ECC algorithms.
250 config NAND_OMAP_GPMC_PREFETCH
251 bool "Enable GPMC Prefetch"
254 On OMAP platforms that use the GPMC controller
255 (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
256 uses the prefetch mode to speed up read operations.
259 bool "Enable ELM driver for OMAPxx and AMxx platforms."
262 ELM controller is used for ECC error detection (not ECC calculation)
263 of BCH4, BCH8 and BCH16 ECC algorithms.
264 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
265 thus such SoC platforms need to depend on software library for ECC error
266 detection. However ECC calculation on such plaforms would still be
267 done by GPMC controller.
271 default NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
273 On OMAP platforms, this CONFIG specifies NAND ECC scheme.
274 It can take following values:
275 OMAP_ECC_HAM1_CODE_SW
276 1-bit Hamming code using software lib.
277 (for legacy devices only)
278 OMAP_ECC_HAM1_CODE_HW
279 1-bit Hamming code using GPMC hardware.
280 (for legacy devices only)
281 OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
282 4-bit BCH code (unsupported)
283 OMAP_ECC_BCH4_CODE_HW
284 4-bit BCH code (unsupported)
285 OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
287 - ecc calculation using GPMC hardware engine,
288 - error detection using software library.
289 - requires CONFIG_BCH to enable software BCH library
290 (For legacy device which do not have ELM h/w engine)
291 OMAP_ECC_BCH8_CODE_HW
293 - ecc calculation using GPMC hardware engine,
294 - error detection using ELM hardware engine.
295 OMAP_ECC_BCH16_CODE_HW
297 - ecc calculation using GPMC hardware engine,
298 - error detection using ELM hardware engine.
300 How to select ECC scheme on OMAP and AMxx platforms ?
301 -----------------------------------------------------
302 Though higher ECC schemes have more capability to detect and correct
303 bit-flips, but still selection of ECC scheme is dependent on following
304 - hardware engines present in SoC.
305 Some legacy OMAP SoC do not have ELM h/w engine thus such
306 SoC cannot support BCHx_HW ECC schemes.
307 - size of OOB/Spare region
308 With higher ECC schemes, more OOB/Spare area is required to
309 store ECC. So choice of ECC scheme is limited by NAND oobsize.
311 In general following expression can help:
312 NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES
314 NAND_OOBSIZE = number of bytes available in
315 OOB/spare area per NAND page.
316 NAND_PAGESIZE = bytes in main-area of NAND page.
317 ECC_BYTES = number of ECC bytes generated to
318 protect 512 bytes of data, which is:
319 3 for HAM1_xx ecc schemes
320 7 for BCH4_xx ecc schemes
321 14 for BCH8_xx ecc schemes
322 26 for BCH16_xx ecc schemes
324 example to check for BCH16 on 2K page NAND
327 2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE
328 Thus BCH16 cannot be supported on 2K page NAND.
330 However, for 4K pagesize NAND
334 2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE
335 Thus BCH16 can be supported on 4K page NAND.
337 config NAND_OMAP_ECCSCHEME_HAM1_CODE_SW
338 bool "1-bit Hamming code using software lib"
340 config NAND_OMAP_ECCSCHEME_HAM1_CODE_HW
341 bool "1-bit Hamming code using GPMC hardware"
343 config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW
344 bool "8-bit BCH code with HW calculation SW error detection"
346 config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
347 bool "8-bit BCH code with HW calculation and error detection"
349 config NAND_OMAP_ECCSCHEME_BCH16_CODE_HW
350 bool "16-bit BCH code with HW calculation and error detection"
354 config NAND_OMAP_ECCSCHEME
356 default 1 if NAND_OMAP_ECCSCHEME_HAM1_CODE_SW
357 default 2 if NAND_OMAP_ECCSCHEME_HAM1_CODE_HW
358 default 5 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW
359 default 6 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
360 default 7 if NAND_OMAP_ECCSCHEME_BCH16_CODE_HW
362 This must be kept in sync with the enum in
363 include/linux/mtd/omap_gpmc.h
367 config NAND_VF610_NFC
368 bool "Support for Freescale NFC for VF610"
369 select SYS_NAND_SELF_INIT
370 select SYS_NAND_DRIVER_ECC_LAYOUT
373 Enables support for NAND Flash Controller on some Freescale
374 processors like the VF610, MCF54418 or Kinetis K70.
375 The driver supports a maximum 2k page size. The driver
376 currently does not support hardware ECC.
380 config NAND_VF610_NFC_DT
381 bool "Support Vybrid's vf610 NAND controller as a DT device"
382 depends on OF_CONTROL && DM_MTD
384 Enable the driver for Vybrid's vf610 NAND flash on platforms
388 prompt "Hardware ECC strength"
389 depends on NAND_VF610_NFC
390 default SYS_NAND_VF610_NFC_45_ECC_BYTES
392 Select the ECC strength used in the hardware BCH ECC block.
394 config SYS_NAND_VF610_NFC_45_ECC_BYTES
395 bool "24-error correction (45 ECC bytes)"
397 config SYS_NAND_VF610_NFC_60_ECC_BYTES
398 bool "32-error correction (60 ECC bytes)"
405 bool "Support for NAND on PXA3xx and Armada 370/XP/38x"
406 select SYS_NAND_SELF_INIT
412 This enables the driver for the NAND flash device found on
413 PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
416 bool "Support for NAND on Allwinner SoCs"
418 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I
419 select SYS_NAND_SELF_INIT
420 select SYS_NAND_U_BOOT_LOCATIONS
421 select SPL_NAND_SUPPORT
422 select SPL_SYS_NAND_SELF_INIT
425 Enable support for NAND. This option enables the standard and
427 The SPL driver only supports reading from the NAND using DMA
432 config NAND_SUNXI_SPL_ECC_STRENGTH
433 int "Allwinner NAND SPL ECC Strength"
436 config NAND_SUNXI_SPL_ECC_SIZE
437 int "Allwinner NAND SPL ECC Step Size"
440 config NAND_SUNXI_SPL_USABLE_PAGE_SIZE
441 int "Allwinner NAND SPL Usable Page Size"
447 bool "Configure Arasan Nand"
448 select SYS_NAND_SELF_INIT
452 This enables Nand driver support for Arasan nand flash
453 controller. This uses the hardware ECC for read and
457 bool "MXC NAND support"
458 depends on CPU_ARM926EJS || CPU_ARM1136 || MX5
461 This enables the NAND driver for the NAND flash controller on the
462 i.MX27 / i.MX31 / i.MX5 processors.
465 int "Size of NAND in kilobytes"
466 depends on NAND_MXC && SPL_NAND_SUPPORT
470 bool "MXS NAND support"
471 depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M
472 select SPL_SYS_NAND_SELF_INIT
473 select SYS_NAND_SELF_INIT
476 select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
477 select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
479 This enables NAND driver for the NAND flash controller on the
485 bool "Support MXS NAND controller as a DT device"
486 depends on OF_CONTROL && DM_MTD
488 Enable the driver for MXS NAND flash on platforms using
491 config NAND_MXS_USE_MINIMUM_ECC
492 bool "Use minimum ECC strength supported by the controller"
498 bool "Macronix raw NAND controller"
499 select SYS_NAND_SELF_INIT
501 This selects the Macronix raw NAND controller driver.
504 bool "Support for Zynq Nand controller"
505 select SPL_SYS_NAND_SELF_INIT
506 select SYS_NAND_SELF_INIT
510 This enables Nand driver support for Nand flash controller
513 config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
514 bool "Enable use of 1st stage bootloader timing for NAND"
517 This flag prevent U-boot reconfigure NAND flash controller and reuse
518 the NAND timing from 1st stage bootloader.
521 bool "Support for OcteonTX NAND controller"
522 select SYS_NAND_SELF_INIT
525 This enables Nand flash controller hardware found on the OcteonTX
528 config NAND_OCTEONTX_HW_ECC
529 bool "Support Hardware ECC for OcteonTX NAND controller"
530 depends on NAND_OCTEONTX
533 This enables Hardware BCH engine found on the OcteonTX processors to
534 support ECC for NAND flash controller.
536 config NAND_STM32_FMC2
537 bool "Support for NAND controller on STM32MP SoCs"
538 depends on ARCH_STM32MP
539 select SYS_NAND_SELF_INIT
542 Enables support for NAND Flash chips on SoCs containing the FMC2
543 NAND controller. This controller is found on STM32MP SoCs.
544 The controller supports a maximum 8k page size and supports
545 a maximum 8-bit correction error per sector of 512 bytes.
548 bool "Support for NAND controller on Cortina-Access SoCs"
549 depends on CORTINA_PLATFORM
550 select SYS_NAND_SELF_INIT
554 Enables support for NAND Flash chips on Coartina-Access SoCs platform
555 This controller is found on Presidio/Venus SoCs.
556 The controller supports a maximum 8k page size and supports
557 a maximum 40-bit error correction per sector of 1024 bytes.
560 bool "Support for NAND controller on Rockchip SoCs"
561 depends on ARCH_ROCKCHIP
562 select SYS_NAND_SELF_INIT
566 Enables support for NAND Flash chips on Rockchip SoCs platform.
567 This controller is found on Rockchip SoCs.
568 There are four different versions of NAND FLASH Controllers,
570 NFC v600: RK2928, RK3066, RK3188
571 NFC v622: RK3036, RK3128
572 NFC v800: RK3308, RV1108
573 NFC v900: PX30, RK3326
576 bool "Support for NAND controller on Tegra SoCs"
577 depends on ARCH_TEGRA
578 select SYS_NAND_SELF_INIT
581 Enables support for NAND Flash chips on Tegra SoCs platforms.
584 bool "Support for MediaTek MT7621 NAND flash controller"
585 depends on SOC_MT7621
586 select SYS_NAND_SELF_INIT
587 select SPL_SYS_NAND_SELF_INIT
590 This enables NAND driver for the NAND flash controller on MediaTek
592 The controller supports 4~12 bits correction per 512 bytes with a
593 maximum 4KB page size.
595 comment "Generic NAND options"
597 config SYS_NAND_BLOCK_SIZE
598 hex "NAND chip eraseblock size"
599 depends on ARCH_SUNXI || SPL_NAND_SUPPORT || TPL_NAND_SUPPORT
600 depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && \
601 !NAND_FSL_IFC && !NAND_MT7621
603 Number of data bytes in one eraseblock for the NAND chip on the
604 board. This is the multiple of NAND_PAGE_SIZE and the number of
607 config SYS_NAND_ONFI_DETECTION
608 bool "Enable detection of ONFI compliant devices during probe"
610 Enables detection of ONFI compliant devices during probe.
611 And fetching device parameters flashed on device, by parsing
614 config SYS_NAND_PAGE_COUNT
615 hex "NAND chip page count"
616 depends on SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC || \
617 SPL_NAND_AM33XX_BCH || SPL_NAND_LOAD || SPL_NAND_SIMPLE)
619 Number of pages in the NAND chip.
621 config SYS_NAND_PAGE_SIZE
622 hex "NAND chip page size"
623 depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
624 SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
625 (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
626 depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && !NAND_MT7621
628 Number of data bytes in one page for the NAND chip on the
629 board, not including the OOB area.
631 config SYS_NAND_OOBSIZE
632 hex "NAND chip OOB size"
633 depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
634 SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
635 (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
636 depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
638 Number of bytes in the Out-Of-Band area for the NAND chip on
641 # Enhance depends when converting drivers to Kconfig which use this config
642 # option (mxc_nand, ndfc, omap_gpmc).
643 config SYS_NAND_BUSWIDTH_16BIT
644 bool "Use 16-bit NAND interface"
645 depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI
647 Indicates that NAND device has 16-bit wide data-bus. In absence of this
648 config, bus-width of NAND device is assumed to be either 8-bit and later
649 determined by reading ONFI params.
650 Above config is useful when NAND device's bus-width information cannot
651 be determined from on-chip ONFI params, like in following scenarios:
652 - SPL boot does not support reading of ONFI parameters. This is done to
653 keep SPL code foot-print small.
654 - In current U-Boot flow using nand_init(), driver initialization
655 happens in board_nand_init() which is called before any device probe
656 (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are
657 not available while configuring controller. So a static CONFIG_NAND_xx
658 is needed to know the device's bus-width in advance.
662 config SYS_NAND_5_ADDR_CYCLE
663 bool "Wait 5 address cycles during NAND commands"
664 depends on SPL_NAND_AM33XX_BCH || SPL_NAND_SIMPLE || \
665 (SPL_NAND_SUPPORT && NAND_ATMEL)
668 Some controllers require waiting for 5 address cycles when issuing
669 some commands, on NAND chips larger than 128MiB.
672 prompt "NAND bad block marker/indicator position in the OOB"
673 depends on SPL_NAND_AM33XX_BCH || SPL_NAND_DENALI || SPL_NAND_SIMPLE || \
674 SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC)
675 default HAS_NAND_LARGE_BADBLOCK_POS
677 In the OOB, which position contains the badblock information.
679 config HAS_NAND_LARGE_BADBLOCK_POS
680 bool "Set the bad block marker/indicator to the 'large' position"
682 config HAS_NAND_SMALL_BADBLOCK_POS
683 bool "Set the bad block marker/indicator to the 'small' position"
687 config SYS_NAND_BAD_BLOCK_POS
689 default 0 if HAS_NAND_LARGE_BADBLOCK_POS
690 default 5 if HAS_NAND_SMALL_BADBLOCK_POS
692 config SYS_NAND_U_BOOT_LOCATIONS
693 bool "Define U-boot binaries locations in NAND"
695 Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig.
696 This option should not be enabled when compiling U-boot for boards
697 defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h
700 config SYS_NAND_U_BOOT_OFFS
701 hex "Location in NAND to read U-Boot from"
702 default 0x800000 if NAND_SUNXI
703 depends on SYS_NAND_U_BOOT_LOCATIONS
705 Set the offset from the start of the nand where u-boot should be
708 config SYS_NAND_U_BOOT_OFFS_REDUND
709 hex "Location in NAND to read U-Boot from"
710 default SYS_NAND_U_BOOT_OFFS
711 depends on SYS_NAND_U_BOOT_LOCATIONS
713 Set the offset from the start of the nand where the redundant u-boot
714 should be loaded from.
716 config SPL_NAND_AM33XX_BCH
717 bool "Enables SPL-NAND driver which supports ELM based"
718 depends on SPL_NAND_SUPPORT && NAND_OMAP_GPMC && !OMAP34XX
721 Hardware ECC correction. This is useful for platforms which have ELM
722 hardware engine and use NAND boot mode.
723 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
724 so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
725 SPL-NAND driver with software ECC correction support.
727 config SPL_NAND_DENALI
728 bool "Support Denali NAND controller for SPL"
729 depends on SPL_NAND_SUPPORT
731 This is a small implementation of the Denali NAND controller
734 config NAND_DENALI_SPARE_AREA_SKIP_BYTES
735 int "Number of bytes skipped in OOB area"
736 depends on SPL_NAND_DENALI
739 This option specifies the number of bytes to skip from the beginning
740 of OOB area before last ECC sector data starts. This is potentially
741 used to preserve the bad block marker in the OOB area.
743 config SPL_NAND_SIMPLE
744 bool "Use simple SPL NAND driver"
745 depends on !SPL_NAND_AM33XX_BCH && SPL_NAND_SUPPORT
747 Support for NAND boot using simple NAND drivers that
748 expose the cmd_ctrl() interface.
750 config SYS_NAND_HW_ECC_OOBFIRST
751 bool "In SPL, read the OOB first and then the data from NAND"
752 depends on SPL_NAND_SIMPLE