2 menuconfig MTD_RAW_NAND
3 bool "Raw NAND Device Support"
6 config SYS_NAND_SELF_INIT
9 This option, if enabled, provides more flexible and linux-like
10 NAND initialization process.
12 config SYS_NAND_DRIVER_ECC_LAYOUT
15 Omit standard ECC layouts to safe space. Select this if your driver
16 is known to provide its own ECC layout.
18 config SYS_NAND_USE_FLASH_BBT
19 bool "Enable BBT (Bad Block Table) support"
21 Enable the BBT (Bad Block Table) usage.
24 bool "Support Atmel NAND controller"
25 imply SYS_NAND_USE_FLASH_BBT
27 Enable this driver for NAND flash platforms using an Atmel NAND
32 config ATMEL_NAND_HWECC
33 bool "Atmel Hardware ECC"
35 config ATMEL_NAND_HW_PMECC
36 bool "Atmel Programmable Multibit ECC (PMECC)"
37 select ATMEL_NAND_HWECC
39 The Programmable Multibit ECC (PMECC) controller is a programmable
40 binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder.
43 int "PMECC Correctable ECC Bits"
44 depends on ATMEL_NAND_HW_PMECC
47 Correctable ECC bits, can be 2, 4, 8, 12, and 24.
49 config PMECC_SECTOR_SIZE
50 int "PMECC Sector Size"
51 depends on ATMEL_NAND_HW_PMECC
54 Sector size, in bytes, can be 512 or 1024.
56 config SPL_GENERATE_ATMEL_PMECC_HEADER
57 bool "Atmel PMECC Header Generation"
58 select ATMEL_NAND_HWECC
59 select ATMEL_NAND_HW_PMECC
61 Generate Programmable Multibit ECC (PMECC) header for SPL image.
66 bool "Support Broadcom NAND controller"
67 depends on OF_CONTROL && DM && DM_MTD
69 Enable the driver for NAND flash on platforms using a Broadcom NAND
72 config NAND_BRCMNAND_6368
73 bool "Support Broadcom NAND controller on bcm6368"
74 depends on NAND_BRCMNAND && ARCH_BMIPS
76 Enable support for broadcom nand driver on bcm6368.
78 config NAND_BRCMNAND_68360
79 bool "Support Broadcom NAND controller on bcm68360"
80 depends on NAND_BRCMNAND && ARCH_BCM68360
82 Enable support for broadcom nand driver on bcm68360.
84 config NAND_BRCMNAND_6838
85 bool "Support Broadcom NAND controller on bcm6838"
86 depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838
88 Enable support for broadcom nand driver on bcm6838.
90 config NAND_BRCMNAND_6858
91 bool "Support Broadcom NAND controller on bcm6858"
92 depends on NAND_BRCMNAND && ARCH_BCM6858
94 Enable support for broadcom nand driver on bcm6858.
96 config NAND_BRCMNAND_63158
97 bool "Support Broadcom NAND controller on bcm63158"
98 depends on NAND_BRCMNAND && ARCH_BCM63158
100 Enable support for broadcom nand driver on bcm63158.
103 bool "Support TI Davinci NAND controller"
105 Enable this driver for NAND flash controllers available in TI Davinci
106 and Keystone2 platforms
108 config KEYSTONE_RBL_NAND
109 depends on ARCH_KEYSTONE
114 depends on NAND_DAVINCI && ARCH_DAVINCI && SPL_NAND_SUPPORT
118 select SYS_NAND_SELF_INIT
121 config NAND_DENALI_DT
122 bool "Support Denali NAND controller as a DT device"
124 depends on OF_CONTROL && DM_MTD
126 Enable the driver for NAND flash on platforms using a Denali NAND
127 controller as a DT device.
130 bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver"
133 Enable the Freescale Enhanced Local Bus Controller FCM NAND driver.
136 bool "Support Freescale Integrated Flash Controller NAND driver"
138 Enable the Freescale Integrated Flash Controller NAND driver.
140 config NAND_LPC32XX_MLC
141 bool "Support LPC32XX_MLC controller"
143 Enable the LPC32XX MLC NAND controller.
145 config NAND_LPC32XX_SLC
146 bool "Support LPC32XX_SLC controller"
148 Enable the LPC32XX SLC NAND controller.
150 config NAND_OMAP_GPMC
151 bool "Support OMAP GPMC NAND controller"
152 depends on ARCH_OMAP2PLUS
154 Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
155 GPMC controller is used for parallel NAND flash devices, and can
156 do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
157 and BCH16 ECC algorithms.
161 config NAND_OMAP_GPMC_PREFETCH
162 bool "Enable GPMC Prefetch"
165 On OMAP platforms that use the GPMC controller
166 (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
167 uses the prefetch mode to speed up read operations.
170 bool "Enable ELM driver for OMAPxx and AMxx platforms."
173 ELM controller is used for ECC error detection (not ECC calculation)
174 of BCH4, BCH8 and BCH16 ECC algorithms.
175 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
176 thus such SoC platforms need to depend on software library for ECC error
177 detection. However ECC calculation on such plaforms would still be
178 done by GPMC controller.
182 default NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
184 On OMAP platforms, this CONFIG specifies NAND ECC scheme.
185 It can take following values:
186 OMAP_ECC_HAM1_CODE_SW
187 1-bit Hamming code using software lib.
188 (for legacy devices only)
189 OMAP_ECC_HAM1_CODE_HW
190 1-bit Hamming code using GPMC hardware.
191 (for legacy devices only)
192 OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
193 4-bit BCH code (unsupported)
194 OMAP_ECC_BCH4_CODE_HW
195 4-bit BCH code (unsupported)
196 OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
198 - ecc calculation using GPMC hardware engine,
199 - error detection using software library.
200 - requires CONFIG_BCH to enable software BCH library
201 (For legacy device which do not have ELM h/w engine)
202 OMAP_ECC_BCH8_CODE_HW
204 - ecc calculation using GPMC hardware engine,
205 - error detection using ELM hardware engine.
206 OMAP_ECC_BCH16_CODE_HW
208 - ecc calculation using GPMC hardware engine,
209 - error detection using ELM hardware engine.
211 How to select ECC scheme on OMAP and AMxx platforms ?
212 -----------------------------------------------------
213 Though higher ECC schemes have more capability to detect and correct
214 bit-flips, but still selection of ECC scheme is dependent on following
215 - hardware engines present in SoC.
216 Some legacy OMAP SoC do not have ELM h/w engine thus such
217 SoC cannot support BCHx_HW ECC schemes.
218 - size of OOB/Spare region
219 With higher ECC schemes, more OOB/Spare area is required to
220 store ECC. So choice of ECC scheme is limited by NAND oobsize.
222 In general following expression can help:
223 NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES
225 NAND_OOBSIZE = number of bytes available in
226 OOB/spare area per NAND page.
227 NAND_PAGESIZE = bytes in main-area of NAND page.
228 ECC_BYTES = number of ECC bytes generated to
229 protect 512 bytes of data, which is:
230 3 for HAM1_xx ecc schemes
231 7 for BCH4_xx ecc schemes
232 14 for BCH8_xx ecc schemes
233 26 for BCH16_xx ecc schemes
235 example to check for BCH16 on 2K page NAND
238 2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE
239 Thus BCH16 cannot be supported on 2K page NAND.
241 However, for 4K pagesize NAND
245 2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE
246 Thus BCH16 can be supported on 4K page NAND.
248 config NAND_OMAP_ECCSCHEME_HAM1_CODE_SW
249 bool "1-bit Hamming code using software lib"
251 config NAND_OMAP_ECCSCHEME_HAM1_CODE_HW
252 bool "1-bit Hamming code using GPMC hardware"
254 config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW
255 bool "8-bit BCH code with HW calculation SW error detection"
257 config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
258 bool "8-bit BCH code with HW calculation and error detection"
260 config NAND_OMAP_ECCSCHEME_BCH16_CODE_HW
261 bool "16-bit BCH code with HW calculation and error detection"
265 config NAND_OMAP_ECCSCHEME
267 default 1 if NAND_OMAP_ECCSCHEME_HAM1_CODE_SW
268 default 2 if NAND_OMAP_ECCSCHEME_HAM1_CODE_HW
269 default 5 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW
270 default 6 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
271 default 7 if NAND_OMAP_ECCSCHEME_BCH16_CODE_HW
273 This must be kept in sync with the enum in
274 include/linux/mtd/omap_gpmc.h
278 config NAND_VF610_NFC
279 bool "Support for Freescale NFC for VF610"
280 select SYS_NAND_SELF_INIT
281 select SYS_NAND_DRIVER_ECC_LAYOUT
284 Enables support for NAND Flash Controller on some Freescale
285 processors like the VF610, MCF54418 or Kinetis K70.
286 The driver supports a maximum 2k page size. The driver
287 currently does not support hardware ECC.
291 config NAND_VF610_NFC_DT
292 bool "Support Vybrid's vf610 NAND controller as a DT device"
293 depends on OF_CONTROL && DM_MTD
295 Enable the driver for Vybrid's vf610 NAND flash on platforms
299 prompt "Hardware ECC strength"
300 depends on NAND_VF610_NFC
301 default SYS_NAND_VF610_NFC_45_ECC_BYTES
303 Select the ECC strength used in the hardware BCH ECC block.
305 config SYS_NAND_VF610_NFC_45_ECC_BYTES
306 bool "24-error correction (45 ECC bytes)"
308 config SYS_NAND_VF610_NFC_60_ECC_BYTES
309 bool "32-error correction (60 ECC bytes)"
316 bool "Support for NAND on PXA3xx and Armada 370/XP/38x"
317 select SYS_NAND_SELF_INIT
323 This enables the driver for the NAND flash device found on
324 PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
327 bool "Support for NAND on Allwinner SoCs"
329 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I
330 select SYS_NAND_SELF_INIT
331 select SYS_NAND_U_BOOT_LOCATIONS
332 select SPL_NAND_SUPPORT
335 Enable support for NAND. This option enables the standard and
337 The SPL driver only supports reading from the NAND using DMA
342 config NAND_SUNXI_SPL_ECC_STRENGTH
343 int "Allwinner NAND SPL ECC Strength"
346 config NAND_SUNXI_SPL_ECC_SIZE
347 int "Allwinner NAND SPL ECC Step Size"
350 config NAND_SUNXI_SPL_USABLE_PAGE_SIZE
351 int "Allwinner NAND SPL Usable Page Size"
357 bool "Configure Arasan Nand"
358 select SYS_NAND_SELF_INIT
362 This enables Nand driver support for Arasan nand flash
363 controller. This uses the hardware ECC for read and
367 bool "MXC NAND support"
368 depends on CPU_ARM926EJS || CPU_ARM1136 || MX5
371 This enables the NAND driver for the NAND flash controller on the
372 i.MX27 / i.MX31 / i.MX5 rocessors.
375 bool "MXS NAND support"
376 depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M
377 select SYS_NAND_SELF_INIT
380 select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
381 select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
383 This enables NAND driver for the NAND flash controller on the
389 bool "Support MXS NAND controller as a DT device"
390 depends on OF_CONTROL && DM_MTD
392 Enable the driver for MXS NAND flash on platforms using
395 config NAND_MXS_USE_MINIMUM_ECC
396 bool "Use minimum ECC strength supported by the controller"
402 bool "Macronix raw NAND controller"
403 select SYS_NAND_SELF_INIT
405 This selects the Macronix raw NAND controller driver.
408 bool "Support for Zynq Nand controller"
409 select SYS_NAND_SELF_INIT
413 This enables Nand driver support for Nand flash controller
416 config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
417 bool "Enable use of 1st stage bootloader timing for NAND"
420 This flag prevent U-boot reconfigure NAND flash controller and reuse
421 the NAND timing from 1st stage bootloader.
424 bool "Support for OcteonTX NAND controller"
425 select SYS_NAND_SELF_INIT
428 This enables Nand flash controller hardware found on the OcteonTX
431 config NAND_OCTEONTX_HW_ECC
432 bool "Support Hardware ECC for OcteonTX NAND controller"
433 depends on NAND_OCTEONTX
436 This enables Hardware BCH engine found on the OcteonTX processors to
437 support ECC for NAND flash controller.
439 config NAND_STM32_FMC2
440 bool "Support for NAND controller on STM32MP SoCs"
441 depends on ARCH_STM32MP
442 select SYS_NAND_SELF_INIT
445 Enables support for NAND Flash chips on SoCs containing the FMC2
446 NAND controller. This controller is found on STM32MP SoCs.
447 The controller supports a maximum 8k page size and supports
448 a maximum 8-bit correction error per sector of 512 bytes.
451 bool "Support for NAND controller on Cortina-Access SoCs"
452 depends on CORTINA_PLATFORM
453 select SYS_NAND_SELF_INIT
457 Enables support for NAND Flash chips on Coartina-Access SoCs platform
458 This controller is found on Presidio/Venus SoCs.
459 The controller supports a maximum 8k page size and supports
460 a maximum 40-bit error correction per sector of 1024 bytes.
463 bool "Support for NAND controller on Rockchip SoCs"
464 depends on ARCH_ROCKCHIP
465 select SYS_NAND_SELF_INIT
469 Enables support for NAND Flash chips on Rockchip SoCs platform.
470 This controller is found on Rockchip SoCs.
471 There are four different versions of NAND FLASH Controllers,
473 NFC v600: RK2928, RK3066, RK3188
474 NFC v622: RK3036, RK3128
475 NFC v800: RK3308, RV1108
476 NFC v900: PX30, RK3326
478 comment "Generic NAND options"
480 config SYS_NAND_BLOCK_SIZE
481 hex "NAND chip eraseblock size"
482 depends on ARCH_SUNXI || SPL_NAND_SUPPORT || TPL_NAND_SUPPORT
483 depends on !NAND_MXS_DT && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
485 Number of data bytes in one eraseblock for the NAND chip on the
486 board. This is the multiple of NAND_PAGE_SIZE and the number of
489 config SYS_NAND_ONFI_DETECTION
490 bool "Enable detection of ONFI compliant devices during probe"
492 Enables detection of ONFI compliant devices during probe.
493 And fetching device parameters flashed on device, by parsing
496 config SYS_NAND_PAGE_COUNT
497 hex "NAND chip page count"
498 depends on SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC || \
499 SPL_NAND_AM33XX_BCH || SPL_NAND_LOAD || SPL_NAND_SIMPLE)
501 Number of pages in the NAND chip.
503 config SYS_NAND_PAGE_SIZE
504 hex "NAND chip page size"
505 depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
506 SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
507 (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
508 depends on !NAND_MXS_DT && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
510 Number of data bytes in one page for the NAND chip on the
511 board, not including the OOB area.
513 config SYS_NAND_OOBSIZE
514 hex "NAND chip OOB size"
515 depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
516 SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
517 (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
518 depends on !NAND_MXS_DT && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
520 Number of bytes in the Out-Of-Band area for the NAND chip on
523 # Enhance depends when converting drivers to Kconfig which use this config
524 # option (mxc_nand, ndfc, omap_gpmc).
525 config SYS_NAND_BUSWIDTH_16BIT
526 bool "Use 16-bit NAND interface"
527 depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI
529 Indicates that NAND device has 16-bit wide data-bus. In absence of this
530 config, bus-width of NAND device is assumed to be either 8-bit and later
531 determined by reading ONFI params.
532 Above config is useful when NAND device's bus-width information cannot
533 be determined from on-chip ONFI params, like in following scenarios:
534 - SPL boot does not support reading of ONFI parameters. This is done to
535 keep SPL code foot-print small.
536 - In current U-Boot flow using nand_init(), driver initialization
537 happens in board_nand_init() which is called before any device probe
538 (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are
539 not available while configuring controller. So a static CONFIG_NAND_xx
540 is needed to know the device's bus-width in advance.
544 config SYS_NAND_5_ADDR_CYCLE
545 bool "Wait 5 address cycles during NAND commands"
546 depends on SPL_NAND_AM33XX_BCH || SPL_NAND_SIMPLE || \
547 (SPL_NAND_SUPPORT && NAND_ATMEL)
550 Some controllers require waiting for 5 address cycles when issuing
551 some commands, on NAND chips larger than 128MiB.
554 prompt "NAND bad block marker/indicator position in the OOB"
555 depends on SPL_NAND_AM33XX_BCH || SPL_NAND_DENALI || SPL_NAND_SIMPLE || \
556 SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC)
557 default HAS_NAND_LARGE_BADBLOCK_POS
559 In the OOB, which position contains the badblock information.
561 config HAS_NAND_LARGE_BADBLOCK_POS
562 bool "Set the bad block marker/indicator to the 'large' position"
564 config HAS_NAND_SMALL_BADBLOCK_POS
565 bool "Set the bad block marker/indicator to the 'small' position"
569 config SYS_NAND_BAD_BLOCK_POS
571 default 0 if HAS_NAND_LARGE_BADBLOCK_POS
572 default 5 if HAS_NAND_SMALL_BADBLOCK_POS
574 config SYS_NAND_U_BOOT_LOCATIONS
575 bool "Define U-boot binaries locations in NAND"
577 Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig.
578 This option should not be enabled when compiling U-boot for boards
579 defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h
582 config SYS_NAND_U_BOOT_OFFS
583 hex "Location in NAND to read U-Boot from"
584 default 0x800000 if NAND_SUNXI
585 depends on SYS_NAND_U_BOOT_LOCATIONS
587 Set the offset from the start of the nand where u-boot should be
590 config SYS_NAND_U_BOOT_OFFS_REDUND
591 hex "Location in NAND to read U-Boot from"
592 default SYS_NAND_U_BOOT_OFFS
593 depends on SYS_NAND_U_BOOT_LOCATIONS
595 Set the offset from the start of the nand where the redundant u-boot
596 should be loaded from.
598 config SPL_NAND_AM33XX_BCH
599 bool "Enables SPL-NAND driver which supports ELM based"
600 depends on NAND_OMAP_GPMC && !OMAP34XX
603 Hardware ECC correction. This is useful for platforms which have ELM
604 hardware engine and use NAND boot mode.
605 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
606 so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
607 SPL-NAND driver with software ECC correction support.
609 config SPL_NAND_DENALI
610 bool "Support Denali NAND controller for SPL"
612 This is a small implementation of the Denali NAND controller
615 config NAND_DENALI_SPARE_AREA_SKIP_BYTES
616 int "Number of bytes skipped in OOB area"
617 depends on SPL_NAND_DENALI
620 This option specifies the number of bytes to skip from the beginning
621 of OOB area before last ECC sector data starts. This is potentially
622 used to preserve the bad block marker in the OOB area.
624 config SPL_NAND_SIMPLE
625 bool "Use simple SPL NAND driver"
626 depends on !SPL_NAND_AM33XX_BCH
628 Support for NAND boot using simple NAND drivers that
629 expose the cmd_ctrl() interface.