2 * drivers/mtd/nand/pxa3xx_nand.c
4 * Copyright © 2005 Intel Corporation
5 * Copyright © 2006 Marvell International Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/interrupt.h>
15 #include <linux/platform_device.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/delay.h>
18 #include <linux/clk.h>
19 #include <linux/mtd/mtd.h>
20 #include <linux/mtd/nand.h>
21 #include <linux/mtd/partitions.h>
23 #include <linux/irq.h>
24 #include <linux/slab.h>
26 #include <linux/of_device.h>
29 #include <linux/platform_data/mtd-nand-pxa3xx.h>
31 #define CHIP_DELAY_TIMEOUT (2 * HZ/10)
32 #define NAND_STOP_DELAY (2 * HZ/50)
33 #define PAGE_CHUNK_SIZE (2048)
35 /* registers and bit definitions */
36 #define NDCR (0x00) /* Control register */
37 #define NDTR0CS0 (0x04) /* Timing Parameter 0 for CS0 */
38 #define NDTR1CS0 (0x0C) /* Timing Parameter 1 for CS0 */
39 #define NDSR (0x14) /* Status Register */
40 #define NDPCR (0x18) /* Page Count Register */
41 #define NDBDR0 (0x1C) /* Bad Block Register 0 */
42 #define NDBDR1 (0x20) /* Bad Block Register 1 */
43 #define NDDB (0x40) /* Data Buffer */
44 #define NDCB0 (0x48) /* Command Buffer0 */
45 #define NDCB1 (0x4C) /* Command Buffer1 */
46 #define NDCB2 (0x50) /* Command Buffer2 */
48 #define NDCR_SPARE_EN (0x1 << 31)
49 #define NDCR_ECC_EN (0x1 << 30)
50 #define NDCR_DMA_EN (0x1 << 29)
51 #define NDCR_ND_RUN (0x1 << 28)
52 #define NDCR_DWIDTH_C (0x1 << 27)
53 #define NDCR_DWIDTH_M (0x1 << 26)
54 #define NDCR_PAGE_SZ (0x1 << 24)
55 #define NDCR_NCSX (0x1 << 23)
56 #define NDCR_ND_MODE (0x3 << 21)
57 #define NDCR_NAND_MODE (0x0)
58 #define NDCR_CLR_PG_CNT (0x1 << 20)
59 #define NDCR_STOP_ON_UNCOR (0x1 << 19)
60 #define NDCR_RD_ID_CNT_MASK (0x7 << 16)
61 #define NDCR_RD_ID_CNT(x) (((x) << 16) & NDCR_RD_ID_CNT_MASK)
63 #define NDCR_RA_START (0x1 << 15)
64 #define NDCR_PG_PER_BLK (0x1 << 14)
65 #define NDCR_ND_ARB_EN (0x1 << 12)
66 #define NDCR_INT_MASK (0xFFF)
68 #define NDSR_MASK (0xfff)
69 #define NDSR_RDY (0x1 << 12)
70 #define NDSR_FLASH_RDY (0x1 << 11)
71 #define NDSR_CS0_PAGED (0x1 << 10)
72 #define NDSR_CS1_PAGED (0x1 << 9)
73 #define NDSR_CS0_CMDD (0x1 << 8)
74 #define NDSR_CS1_CMDD (0x1 << 7)
75 #define NDSR_CS0_BBD (0x1 << 6)
76 #define NDSR_CS1_BBD (0x1 << 5)
77 #define NDSR_DBERR (0x1 << 4)
78 #define NDSR_SBERR (0x1 << 3)
79 #define NDSR_WRDREQ (0x1 << 2)
80 #define NDSR_RDDREQ (0x1 << 1)
81 #define NDSR_WRCMDREQ (0x1)
83 #define NDCB0_ST_ROW_EN (0x1 << 26)
84 #define NDCB0_AUTO_RS (0x1 << 25)
85 #define NDCB0_CSEL (0x1 << 24)
86 #define NDCB0_CMD_TYPE_MASK (0x7 << 21)
87 #define NDCB0_CMD_TYPE(x) (((x) << 21) & NDCB0_CMD_TYPE_MASK)
88 #define NDCB0_NC (0x1 << 20)
89 #define NDCB0_DBC (0x1 << 19)
90 #define NDCB0_ADDR_CYC_MASK (0x7 << 16)
91 #define NDCB0_ADDR_CYC(x) (((x) << 16) & NDCB0_ADDR_CYC_MASK)
92 #define NDCB0_CMD2_MASK (0xff << 8)
93 #define NDCB0_CMD1_MASK (0xff)
94 #define NDCB0_ADDR_CYC_SHIFT (16)
96 /* macros for registers read/write */
97 #define nand_writel(info, off, val) \
98 __raw_writel((val), (info)->mmio_base + (off))
100 #define nand_readl(info, off) \
101 __raw_readl((info)->mmio_base + (off))
103 /* error code and state */
126 struct pxa3xx_nand_host {
127 struct nand_chip chip;
128 struct pxa3xx_nand_cmdset *cmdset;
129 struct mtd_info *mtd;
132 /* page size of attached chip */
133 unsigned int page_size;
137 /* calculated from pxa3xx_nand_flash data */
138 unsigned int col_addr_cycles;
139 unsigned int row_addr_cycles;
140 size_t read_id_bytes;
142 /* cached register value */
148 struct pxa3xx_nand_info {
149 struct nand_hw_control controller;
150 struct platform_device *pdev;
153 void __iomem *mmio_base;
154 unsigned long mmio_phys;
155 struct completion cmd_complete;
157 unsigned int buf_start;
158 unsigned int buf_count;
160 /* DMA information */
164 unsigned char *data_buff;
165 unsigned char *oob_buff;
166 dma_addr_t data_buff_phys;
168 struct pxa_dma_desc *data_desc;
169 dma_addr_t data_desc_addr;
171 struct pxa3xx_nand_host *host[NUM_CHIP_SELECT];
175 int use_ecc; /* use HW ECC ? */
176 int use_dma; /* use DMA ? */
179 unsigned int page_size; /* page size of attached chip */
180 unsigned int data_size; /* data size in FIFO */
181 unsigned int oob_size;
184 /* generated NDCBx register values */
190 static bool use_dma = 1;
191 module_param(use_dma, bool, 0444);
192 MODULE_PARM_DESC(use_dma, "enable DMA for data transferring to/from NAND HW");
195 * Default NAND flash controller configuration setup by the
196 * bootloader. This configuration is used only when pdata->keep_config is set
198 static struct pxa3xx_nand_cmdset default_cmdset = {
202 .read_status = 0x0070,
208 .lock_status = 0x007A,
211 static struct pxa3xx_nand_timing timing[] = {
212 { 40, 80, 60, 100, 80, 100, 90000, 400, 40, },
213 { 10, 0, 20, 40, 30, 40, 11123, 110, 10, },
214 { 10, 25, 15, 25, 15, 30, 25000, 60, 10, },
215 { 10, 35, 15, 25, 15, 25, 25000, 60, 10, },
218 static struct pxa3xx_nand_flash builtin_flash_types[] = {
219 { "DEFAULT FLASH", 0, 0, 2048, 8, 8, 0, &timing[0] },
220 { "64MiB 16-bit", 0x46ec, 32, 512, 16, 16, 4096, &timing[1] },
221 { "256MiB 8-bit", 0xdaec, 64, 2048, 8, 8, 2048, &timing[1] },
222 { "4GiB 8-bit", 0xd7ec, 128, 4096, 8, 8, 8192, &timing[1] },
223 { "128MiB 8-bit", 0xa12c, 64, 2048, 8, 8, 1024, &timing[2] },
224 { "128MiB 16-bit", 0xb12c, 64, 2048, 16, 16, 1024, &timing[2] },
225 { "512MiB 8-bit", 0xdc2c, 64, 2048, 8, 8, 4096, &timing[2] },
226 { "512MiB 16-bit", 0xcc2c, 64, 2048, 16, 16, 4096, &timing[2] },
227 { "256MiB 16-bit", 0xba20, 64, 2048, 16, 16, 2048, &timing[3] },
230 /* Define a default flash type setting serve as flash detecting only */
231 #define DEFAULT_FLASH_TYPE (&builtin_flash_types[0])
233 const char *mtd_names[] = {"pxa3xx_nand-0", "pxa3xx_nand-1", NULL};
235 #define NDTR0_tCH(c) (min((c), 7) << 19)
236 #define NDTR0_tCS(c) (min((c), 7) << 16)
237 #define NDTR0_tWH(c) (min((c), 7) << 11)
238 #define NDTR0_tWP(c) (min((c), 7) << 8)
239 #define NDTR0_tRH(c) (min((c), 7) << 3)
240 #define NDTR0_tRP(c) (min((c), 7) << 0)
242 #define NDTR1_tR(c) (min((c), 65535) << 16)
243 #define NDTR1_tWHR(c) (min((c), 15) << 4)
244 #define NDTR1_tAR(c) (min((c), 15) << 0)
246 /* convert nano-seconds to nand flash controller clock cycles */
247 #define ns2cycle(ns, clk) (int)((ns) * (clk / 1000000) / 1000)
249 static void pxa3xx_nand_set_timing(struct pxa3xx_nand_host *host,
250 const struct pxa3xx_nand_timing *t)
252 struct pxa3xx_nand_info *info = host->info_data;
253 unsigned long nand_clk = clk_get_rate(info->clk);
254 uint32_t ndtr0, ndtr1;
256 ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) |
257 NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) |
258 NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) |
259 NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) |
260 NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) |
261 NDTR0_tRP(ns2cycle(t->tRP, nand_clk));
263 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) |
264 NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
265 NDTR1_tAR(ns2cycle(t->tAR, nand_clk));
267 host->ndtr0cs0 = ndtr0;
268 host->ndtr1cs0 = ndtr1;
269 nand_writel(info, NDTR0CS0, ndtr0);
270 nand_writel(info, NDTR1CS0, ndtr1);
273 static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info)
275 struct pxa3xx_nand_host *host = info->host[info->cs];
276 int oob_enable = host->reg_ndcr & NDCR_SPARE_EN;
278 info->data_size = host->page_size;
284 switch (host->page_size) {
286 info->oob_size = (info->use_ecc) ? 40 : 64;
289 info->oob_size = (info->use_ecc) ? 8 : 16;
295 * NOTE: it is a must to set ND_RUN firstly, then write
296 * command buffer, otherwise, it does not work.
297 * We enable all the interrupt at the same time, and
298 * let pxa3xx_nand_irq to handle all logic.
300 static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
302 struct pxa3xx_nand_host *host = info->host[info->cs];
305 ndcr = host->reg_ndcr;
306 ndcr |= info->use_ecc ? NDCR_ECC_EN : 0;
307 ndcr |= info->use_dma ? NDCR_DMA_EN : 0;
310 /* clear status bits and run */
311 nand_writel(info, NDCR, 0);
312 nand_writel(info, NDSR, NDSR_MASK);
313 nand_writel(info, NDCR, ndcr);
316 static void pxa3xx_nand_stop(struct pxa3xx_nand_info *info)
319 int timeout = NAND_STOP_DELAY;
321 /* wait RUN bit in NDCR become 0 */
322 ndcr = nand_readl(info, NDCR);
323 while ((ndcr & NDCR_ND_RUN) && (timeout-- > 0)) {
324 ndcr = nand_readl(info, NDCR);
329 ndcr &= ~NDCR_ND_RUN;
330 nand_writel(info, NDCR, ndcr);
332 /* clear status bits */
333 nand_writel(info, NDSR, NDSR_MASK);
336 static void enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
340 ndcr = nand_readl(info, NDCR);
341 nand_writel(info, NDCR, ndcr & ~int_mask);
344 static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
348 ndcr = nand_readl(info, NDCR);
349 nand_writel(info, NDCR, ndcr | int_mask);
352 static void handle_data_pio(struct pxa3xx_nand_info *info)
354 switch (info->state) {
355 case STATE_PIO_WRITING:
356 __raw_writesl(info->mmio_base + NDDB, info->data_buff,
357 DIV_ROUND_UP(info->data_size, 4));
358 if (info->oob_size > 0)
359 __raw_writesl(info->mmio_base + NDDB, info->oob_buff,
360 DIV_ROUND_UP(info->oob_size, 4));
362 case STATE_PIO_READING:
363 __raw_readsl(info->mmio_base + NDDB, info->data_buff,
364 DIV_ROUND_UP(info->data_size, 4));
365 if (info->oob_size > 0)
366 __raw_readsl(info->mmio_base + NDDB, info->oob_buff,
367 DIV_ROUND_UP(info->oob_size, 4));
370 dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
376 static void start_data_dma(struct pxa3xx_nand_info *info)
378 struct pxa_dma_desc *desc = info->data_desc;
379 int dma_len = ALIGN(info->data_size + info->oob_size, 32);
381 desc->ddadr = DDADR_STOP;
382 desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len;
384 switch (info->state) {
385 case STATE_DMA_WRITING:
386 desc->dsadr = info->data_buff_phys;
387 desc->dtadr = info->mmio_phys + NDDB;
388 desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG;
390 case STATE_DMA_READING:
391 desc->dtadr = info->data_buff_phys;
392 desc->dsadr = info->mmio_phys + NDDB;
393 desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC;
396 dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
401 DRCMR(info->drcmr_dat) = DRCMR_MAPVLD | info->data_dma_ch;
402 DDADR(info->data_dma_ch) = info->data_desc_addr;
403 DCSR(info->data_dma_ch) |= DCSR_RUN;
406 static void pxa3xx_nand_data_dma_irq(int channel, void *data)
408 struct pxa3xx_nand_info *info = data;
411 dcsr = DCSR(channel);
412 DCSR(channel) = dcsr;
414 if (dcsr & DCSR_BUSERR) {
415 info->retcode = ERR_DMABUSERR;
418 info->state = STATE_DMA_DONE;
419 enable_int(info, NDCR_INT_MASK);
420 nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);
423 static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
425 struct pxa3xx_nand_info *info = devid;
426 unsigned int status, is_completed = 0;
427 unsigned int ready, cmd_done;
430 ready = NDSR_FLASH_RDY;
431 cmd_done = NDSR_CS0_CMDD;
434 cmd_done = NDSR_CS1_CMDD;
437 status = nand_readl(info, NDSR);
439 if (status & NDSR_DBERR)
440 info->retcode = ERR_DBERR;
441 if (status & NDSR_SBERR)
442 info->retcode = ERR_SBERR;
443 if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) {
444 /* whether use dma to transfer data */
446 disable_int(info, NDCR_INT_MASK);
447 info->state = (status & NDSR_RDDREQ) ?
448 STATE_DMA_READING : STATE_DMA_WRITING;
449 start_data_dma(info);
450 goto NORMAL_IRQ_EXIT;
452 info->state = (status & NDSR_RDDREQ) ?
453 STATE_PIO_READING : STATE_PIO_WRITING;
454 handle_data_pio(info);
457 if (status & cmd_done) {
458 info->state = STATE_CMD_DONE;
461 if (status & ready) {
463 info->state = STATE_READY;
466 if (status & NDSR_WRCMDREQ) {
467 nand_writel(info, NDSR, NDSR_WRCMDREQ);
468 status &= ~NDSR_WRCMDREQ;
469 info->state = STATE_CMD_HANDLE;
470 nand_writel(info, NDCB0, info->ndcb0);
471 nand_writel(info, NDCB0, info->ndcb1);
472 nand_writel(info, NDCB0, info->ndcb2);
475 /* clear NDSR to let the controller exit the IRQ */
476 nand_writel(info, NDSR, status);
478 complete(&info->cmd_complete);
483 static inline int is_buf_blank(uint8_t *buf, size_t len)
485 for (; len > 0; len--)
491 static int prepare_command_pool(struct pxa3xx_nand_info *info, int command,
492 uint16_t column, int page_addr)
495 int addr_cycle, exec_cmd;
496 struct pxa3xx_nand_host *host;
497 struct mtd_info *mtd;
499 host = info->host[info->cs];
504 /* reset data and oob column point to handle data */
510 info->retcode = ERR_NONE;
512 info->ndcb0 = NDCB0_CSEL;
518 case NAND_CMD_PAGEPROG:
520 case NAND_CMD_READOOB:
521 pxa3xx_set_datasize(info);
532 addr_cycle = NDCB0_ADDR_CYC(host->row_addr_cycles
533 + host->col_addr_cycles);
536 case NAND_CMD_READOOB:
538 cmd = host->cmdset->read1;
539 if (command == NAND_CMD_READOOB)
540 info->buf_start = mtd->writesize + column;
542 info->buf_start = column;
544 if (unlikely(host->page_size < PAGE_CHUNK_SIZE))
545 info->ndcb0 |= NDCB0_CMD_TYPE(0)
547 | (cmd & NDCB0_CMD1_MASK);
549 info->ndcb0 |= NDCB0_CMD_TYPE(0)
555 /* small page addr setting */
556 if (unlikely(host->page_size < PAGE_CHUNK_SIZE)) {
557 info->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
562 info->ndcb1 = ((page_addr & 0xFFFF) << 16)
565 if (page_addr & 0xFF0000)
566 info->ndcb2 = (page_addr & 0xFF0000) >> 16;
571 info->buf_count = mtd->writesize + mtd->oobsize;
572 memset(info->data_buff, 0xFF, info->buf_count);
576 case NAND_CMD_PAGEPROG:
577 if (is_buf_blank(info->data_buff,
578 (mtd->writesize + mtd->oobsize))) {
583 cmd = host->cmdset->program;
584 info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
592 case NAND_CMD_READID:
593 cmd = host->cmdset->read_id;
594 info->buf_count = host->read_id_bytes;
595 info->ndcb0 |= NDCB0_CMD_TYPE(3)
601 case NAND_CMD_STATUS:
602 cmd = host->cmdset->read_status;
604 info->ndcb0 |= NDCB0_CMD_TYPE(4)
611 case NAND_CMD_ERASE1:
612 cmd = host->cmdset->erase;
613 info->ndcb0 |= NDCB0_CMD_TYPE(2)
618 info->ndcb1 = page_addr;
623 cmd = host->cmdset->reset;
624 info->ndcb0 |= NDCB0_CMD_TYPE(5)
629 case NAND_CMD_ERASE2:
635 dev_err(&info->pdev->dev, "non-supported command %x\n",
643 static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
644 int column, int page_addr)
646 struct pxa3xx_nand_host *host = mtd->priv;
647 struct pxa3xx_nand_info *info = host->info_data;
651 * if this is a x16 device ,then convert the input
652 * "byte" address into a "word" address appropriate
653 * for indexing a word-oriented device
655 if (host->reg_ndcr & NDCR_DWIDTH_M)
659 * There may be different NAND chip hooked to
660 * different chip select, so check whether
661 * chip select has been changed, if yes, reset the timing
663 if (info->cs != host->cs) {
665 nand_writel(info, NDTR0CS0, host->ndtr0cs0);
666 nand_writel(info, NDTR1CS0, host->ndtr1cs0);
669 info->state = STATE_PREPARED;
670 exec_cmd = prepare_command_pool(info, command, column, page_addr);
672 init_completion(&info->cmd_complete);
673 pxa3xx_nand_start(info);
675 ret = wait_for_completion_timeout(&info->cmd_complete,
678 dev_err(&info->pdev->dev, "Wait time out!!!\n");
679 /* Stop State Machine for next command cycle */
680 pxa3xx_nand_stop(info);
683 info->state = STATE_IDLE;
686 static void pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd,
687 struct nand_chip *chip, const uint8_t *buf, int oob_required)
689 chip->write_buf(mtd, buf, mtd->writesize);
690 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
693 static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd,
694 struct nand_chip *chip, uint8_t *buf, int oob_required,
697 struct pxa3xx_nand_host *host = mtd->priv;
698 struct pxa3xx_nand_info *info = host->info_data;
700 chip->read_buf(mtd, buf, mtd->writesize);
701 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
703 if (info->retcode == ERR_SBERR) {
704 switch (info->use_ecc) {
706 mtd->ecc_stats.corrected++;
712 } else if (info->retcode == ERR_DBERR) {
714 * for blank page (all 0xff), HW will calculate its ECC as
715 * 0, which is different from the ECC information within
716 * OOB, ignore such double bit errors
718 if (is_buf_blank(buf, mtd->writesize))
719 info->retcode = ERR_NONE;
721 mtd->ecc_stats.failed++;
727 static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
729 struct pxa3xx_nand_host *host = mtd->priv;
730 struct pxa3xx_nand_info *info = host->info_data;
733 if (info->buf_start < info->buf_count)
734 /* Has just send a new command? */
735 retval = info->data_buff[info->buf_start++];
740 static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
742 struct pxa3xx_nand_host *host = mtd->priv;
743 struct pxa3xx_nand_info *info = host->info_data;
746 if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) {
747 retval = *((u16 *)(info->data_buff+info->buf_start));
748 info->buf_start += 2;
753 static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
755 struct pxa3xx_nand_host *host = mtd->priv;
756 struct pxa3xx_nand_info *info = host->info_data;
757 int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
759 memcpy(buf, info->data_buff + info->buf_start, real_len);
760 info->buf_start += real_len;
763 static void pxa3xx_nand_write_buf(struct mtd_info *mtd,
764 const uint8_t *buf, int len)
766 struct pxa3xx_nand_host *host = mtd->priv;
767 struct pxa3xx_nand_info *info = host->info_data;
768 int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
770 memcpy(info->data_buff + info->buf_start, buf, real_len);
771 info->buf_start += real_len;
774 static int pxa3xx_nand_verify_buf(struct mtd_info *mtd,
775 const uint8_t *buf, int len)
780 static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip)
785 static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
787 struct pxa3xx_nand_host *host = mtd->priv;
788 struct pxa3xx_nand_info *info = host->info_data;
790 /* pxa3xx_nand_send_command has waited for command complete */
791 if (this->state == FL_WRITING || this->state == FL_ERASING) {
792 if (info->retcode == ERR_NONE)
796 * any error make it return 0x01 which will tell
797 * the caller the erase and write fail
806 static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
807 const struct pxa3xx_nand_flash *f)
809 struct platform_device *pdev = info->pdev;
810 struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
811 struct pxa3xx_nand_host *host = info->host[info->cs];
812 uint32_t ndcr = 0x0; /* enable all interrupts */
814 if (f->page_size != 2048 && f->page_size != 512) {
815 dev_err(&pdev->dev, "Current only support 2048 and 512 size\n");
819 if (f->flash_width != 16 && f->flash_width != 8) {
820 dev_err(&pdev->dev, "Only support 8bit and 16 bit!\n");
824 /* calculate flash information */
825 host->cmdset = &default_cmdset;
826 host->page_size = f->page_size;
827 host->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
829 /* calculate addressing information */
830 host->col_addr_cycles = (f->page_size == 2048) ? 2 : 1;
832 if (f->num_blocks * f->page_per_block > 65536)
833 host->row_addr_cycles = 3;
835 host->row_addr_cycles = 2;
837 ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
838 ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0;
839 ndcr |= (f->page_per_block == 64) ? NDCR_PG_PER_BLK : 0;
840 ndcr |= (f->page_size == 2048) ? NDCR_PAGE_SZ : 0;
841 ndcr |= (f->flash_width == 16) ? NDCR_DWIDTH_M : 0;
842 ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0;
844 ndcr |= NDCR_RD_ID_CNT(host->read_id_bytes);
845 ndcr |= NDCR_SPARE_EN; /* enable spare by default */
847 host->reg_ndcr = ndcr;
849 pxa3xx_nand_set_timing(host, f->timing);
853 static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
856 * We set 0 by hard coding here, for we don't support keep_config
857 * when there is more than one chip attached to the controller
859 struct pxa3xx_nand_host *host = info->host[0];
860 uint32_t ndcr = nand_readl(info, NDCR);
862 if (ndcr & NDCR_PAGE_SZ) {
863 host->page_size = 2048;
864 host->read_id_bytes = 4;
866 host->page_size = 512;
867 host->read_id_bytes = 2;
870 host->reg_ndcr = ndcr & ~NDCR_INT_MASK;
871 host->cmdset = &default_cmdset;
873 host->ndtr0cs0 = nand_readl(info, NDTR0CS0);
874 host->ndtr1cs0 = nand_readl(info, NDTR1CS0);
879 /* the maximum possible buffer size for large page with OOB data
880 * is: 2048 + 64 = 2112 bytes, allocate a page here for both the
881 * data buffer and the DMA descriptor
883 #define MAX_BUFF_SIZE PAGE_SIZE
885 static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
887 struct platform_device *pdev = info->pdev;
888 int data_desc_offset = MAX_BUFF_SIZE - sizeof(struct pxa_dma_desc);
891 info->data_buff = kmalloc(MAX_BUFF_SIZE, GFP_KERNEL);
892 if (info->data_buff == NULL)
897 info->data_buff = dma_alloc_coherent(&pdev->dev, MAX_BUFF_SIZE,
898 &info->data_buff_phys, GFP_KERNEL);
899 if (info->data_buff == NULL) {
900 dev_err(&pdev->dev, "failed to allocate dma buffer\n");
904 info->data_desc = (void *)info->data_buff + data_desc_offset;
905 info->data_desc_addr = info->data_buff_phys + data_desc_offset;
907 info->data_dma_ch = pxa_request_dma("nand-data", DMA_PRIO_LOW,
908 pxa3xx_nand_data_dma_irq, info);
909 if (info->data_dma_ch < 0) {
910 dev_err(&pdev->dev, "failed to request data dma\n");
911 dma_free_coherent(&pdev->dev, MAX_BUFF_SIZE,
912 info->data_buff, info->data_buff_phys);
913 return info->data_dma_ch;
919 static int pxa3xx_nand_sensing(struct pxa3xx_nand_info *info)
921 struct mtd_info *mtd;
923 mtd = info->host[info->cs]->mtd;
924 /* use the common timing to make a try */
925 ret = pxa3xx_nand_config_flash(info, &builtin_flash_types[0]);
929 pxa3xx_nand_cmdfunc(mtd, NAND_CMD_RESET, 0, 0);
936 static int pxa3xx_nand_scan(struct mtd_info *mtd)
938 struct pxa3xx_nand_host *host = mtd->priv;
939 struct pxa3xx_nand_info *info = host->info_data;
940 struct platform_device *pdev = info->pdev;
941 struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
942 struct nand_flash_dev pxa3xx_flash_ids[2], *def = NULL;
943 const struct pxa3xx_nand_flash *f = NULL;
944 struct nand_chip *chip = mtd->priv;
949 if (pdata->keep_config && !pxa3xx_nand_detect_config(info))
952 ret = pxa3xx_nand_sensing(info);
954 dev_info(&info->pdev->dev, "There is no chip on cs %d!\n",
960 chip->cmdfunc(mtd, NAND_CMD_READID, 0, 0);
961 id = *((uint16_t *)(info->data_buff));
963 dev_info(&info->pdev->dev, "Detect a flash id %x\n", id);
965 dev_warn(&info->pdev->dev,
966 "Read out ID 0, potential timing set wrong!!\n");
971 num = ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1;
972 for (i = 0; i < num; i++) {
973 if (i < pdata->num_flash)
974 f = pdata->flash + i;
976 f = &builtin_flash_types[i - pdata->num_flash + 1];
978 /* find the chip in default list */
979 if (f->chip_id == id)
983 if (i >= (ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1)) {
984 dev_err(&info->pdev->dev, "ERROR!! flash not defined!!!\n");
989 ret = pxa3xx_nand_config_flash(info, f);
991 dev_err(&info->pdev->dev, "ERROR! Configure failed\n");
995 pxa3xx_flash_ids[0].name = f->name;
996 pxa3xx_flash_ids[0].id = (f->chip_id >> 8) & 0xffff;
997 pxa3xx_flash_ids[0].pagesize = f->page_size;
998 chipsize = (uint64_t)f->num_blocks * f->page_per_block * f->page_size;
999 pxa3xx_flash_ids[0].chipsize = chipsize >> 20;
1000 pxa3xx_flash_ids[0].erasesize = f->page_size * f->page_per_block;
1001 if (f->flash_width == 16)
1002 pxa3xx_flash_ids[0].options = NAND_BUSWIDTH_16;
1003 pxa3xx_flash_ids[1].name = NULL;
1004 def = pxa3xx_flash_ids;
1006 chip->ecc.mode = NAND_ECC_HW;
1007 chip->ecc.size = host->page_size;
1008 chip->ecc.strength = 1;
1010 chip->options |= NAND_NO_READRDY;
1011 if (host->reg_ndcr & NDCR_DWIDTH_M)
1012 chip->options |= NAND_BUSWIDTH_16;
1014 if (nand_scan_ident(mtd, 1, def))
1016 /* calculate addressing information */
1017 if (mtd->writesize >= 2048)
1018 host->col_addr_cycles = 2;
1020 host->col_addr_cycles = 1;
1022 info->oob_buff = info->data_buff + mtd->writesize;
1023 if ((mtd->size >> chip->page_shift) > 65536)
1024 host->row_addr_cycles = 3;
1026 host->row_addr_cycles = 2;
1028 mtd->name = mtd_names[0];
1029 return nand_scan_tail(mtd);
1032 static int alloc_nand_resource(struct platform_device *pdev)
1034 struct pxa3xx_nand_platform_data *pdata;
1035 struct pxa3xx_nand_info *info;
1036 struct pxa3xx_nand_host *host;
1037 struct nand_chip *chip = NULL;
1038 struct mtd_info *mtd;
1042 pdata = pdev->dev.platform_data;
1043 info = kzalloc(sizeof(*info) + (sizeof(*mtd) +
1044 sizeof(*host)) * pdata->num_cs, GFP_KERNEL);
1046 dev_err(&pdev->dev, "failed to allocate memory\n");
1051 for (cs = 0; cs < pdata->num_cs; cs++) {
1052 mtd = (struct mtd_info *)((unsigned int)&info[1] +
1053 (sizeof(*mtd) + sizeof(*host)) * cs);
1054 chip = (struct nand_chip *)(&mtd[1]);
1055 host = (struct pxa3xx_nand_host *)chip;
1056 info->host[cs] = host;
1059 host->info_data = info;
1061 mtd->owner = THIS_MODULE;
1063 chip->ecc.read_page = pxa3xx_nand_read_page_hwecc;
1064 chip->ecc.write_page = pxa3xx_nand_write_page_hwecc;
1065 chip->controller = &info->controller;
1066 chip->waitfunc = pxa3xx_nand_waitfunc;
1067 chip->select_chip = pxa3xx_nand_select_chip;
1068 chip->cmdfunc = pxa3xx_nand_cmdfunc;
1069 chip->read_word = pxa3xx_nand_read_word;
1070 chip->read_byte = pxa3xx_nand_read_byte;
1071 chip->read_buf = pxa3xx_nand_read_buf;
1072 chip->write_buf = pxa3xx_nand_write_buf;
1073 chip->verify_buf = pxa3xx_nand_verify_buf;
1076 spin_lock_init(&chip->controller->lock);
1077 init_waitqueue_head(&chip->controller->wq);
1078 info->clk = clk_get(&pdev->dev, NULL);
1079 if (IS_ERR(info->clk)) {
1080 dev_err(&pdev->dev, "failed to get nand clock\n");
1081 ret = PTR_ERR(info->clk);
1084 clk_enable(info->clk);
1087 * This is a dirty hack to make this driver work from devicetree
1088 * bindings. It can be removed once we have a prober DMA controller
1091 if (pdev->dev.of_node && cpu_is_pxa3xx()) {
1092 info->drcmr_dat = 97;
1093 info->drcmr_cmd = 99;
1095 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1097 dev_err(&pdev->dev, "no resource defined for data DMA\n");
1101 info->drcmr_dat = r->start;
1103 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1105 dev_err(&pdev->dev, "no resource defined for command DMA\n");
1109 info->drcmr_cmd = r->start;
1112 irq = platform_get_irq(pdev, 0);
1114 dev_err(&pdev->dev, "no IRQ resource defined\n");
1119 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1121 dev_err(&pdev->dev, "no IO memory resource defined\n");
1126 r = request_mem_region(r->start, resource_size(r), pdev->name);
1128 dev_err(&pdev->dev, "failed to request memory resource\n");
1133 info->mmio_base = ioremap(r->start, resource_size(r));
1134 if (info->mmio_base == NULL) {
1135 dev_err(&pdev->dev, "ioremap() failed\n");
1139 info->mmio_phys = r->start;
1141 ret = pxa3xx_nand_init_buff(info);
1145 /* initialize all interrupts to be disabled */
1146 disable_int(info, NDSR_MASK);
1148 ret = request_irq(irq, pxa3xx_nand_irq, IRQF_DISABLED,
1151 dev_err(&pdev->dev, "failed to request IRQ\n");
1155 platform_set_drvdata(pdev, info);
1160 free_irq(irq, info);
1162 pxa_free_dma(info->data_dma_ch);
1163 dma_free_coherent(&pdev->dev, MAX_BUFF_SIZE,
1164 info->data_buff, info->data_buff_phys);
1166 kfree(info->data_buff);
1168 iounmap(info->mmio_base);
1170 release_mem_region(r->start, resource_size(r));
1172 clk_disable(info->clk);
1179 static int pxa3xx_nand_remove(struct platform_device *pdev)
1181 struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
1182 struct pxa3xx_nand_platform_data *pdata;
1189 pdata = pdev->dev.platform_data;
1190 platform_set_drvdata(pdev, NULL);
1192 irq = platform_get_irq(pdev, 0);
1194 free_irq(irq, info);
1196 pxa_free_dma(info->data_dma_ch);
1197 dma_free_writecombine(&pdev->dev, MAX_BUFF_SIZE,
1198 info->data_buff, info->data_buff_phys);
1200 kfree(info->data_buff);
1202 iounmap(info->mmio_base);
1203 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1204 release_mem_region(r->start, resource_size(r));
1206 clk_disable(info->clk);
1209 for (cs = 0; cs < pdata->num_cs; cs++)
1210 nand_release(info->host[cs]->mtd);
1216 static struct of_device_id pxa3xx_nand_dt_ids[] = {
1217 { .compatible = "marvell,pxa3xx-nand" },
1220 MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids);
1222 static int pxa3xx_nand_probe_dt(struct platform_device *pdev)
1224 struct pxa3xx_nand_platform_data *pdata;
1225 struct device_node *np = pdev->dev.of_node;
1226 const struct of_device_id *of_id =
1227 of_match_device(pxa3xx_nand_dt_ids, &pdev->dev);
1232 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1236 if (of_get_property(np, "marvell,nand-enable-arbiter", NULL))
1237 pdata->enable_arbiter = 1;
1238 if (of_get_property(np, "marvell,nand-keep-config", NULL))
1239 pdata->keep_config = 1;
1240 of_property_read_u32(np, "num-cs", &pdata->num_cs);
1242 pdev->dev.platform_data = pdata;
1247 static inline int pxa3xx_nand_probe_dt(struct platform_device *pdev)
1253 static int pxa3xx_nand_probe(struct platform_device *pdev)
1255 struct pxa3xx_nand_platform_data *pdata;
1256 struct mtd_part_parser_data ppdata = {};
1257 struct pxa3xx_nand_info *info;
1258 int ret, cs, probe_success;
1260 ret = pxa3xx_nand_probe_dt(pdev);
1264 pdata = pdev->dev.platform_data;
1266 dev_err(&pdev->dev, "no platform data defined\n");
1270 ret = alloc_nand_resource(pdev);
1272 dev_err(&pdev->dev, "alloc nand resource failed\n");
1276 info = platform_get_drvdata(pdev);
1278 for (cs = 0; cs < pdata->num_cs; cs++) {
1280 ret = pxa3xx_nand_scan(info->host[cs]->mtd);
1282 dev_warn(&pdev->dev, "failed to scan nand at cs %d\n",
1287 ppdata.of_node = pdev->dev.of_node;
1288 ret = mtd_device_parse_register(info->host[cs]->mtd, NULL,
1289 &ppdata, pdata->parts[cs],
1290 pdata->nr_parts[cs]);
1295 if (!probe_success) {
1296 pxa3xx_nand_remove(pdev);
1304 static int pxa3xx_nand_suspend(struct platform_device *pdev, pm_message_t state)
1306 struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
1307 struct pxa3xx_nand_platform_data *pdata;
1308 struct mtd_info *mtd;
1311 pdata = pdev->dev.platform_data;
1313 dev_err(&pdev->dev, "driver busy, state = %d\n", info->state);
1317 for (cs = 0; cs < pdata->num_cs; cs++) {
1318 mtd = info->host[cs]->mtd;
1325 static int pxa3xx_nand_resume(struct platform_device *pdev)
1327 struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
1328 struct pxa3xx_nand_platform_data *pdata;
1329 struct mtd_info *mtd;
1332 pdata = pdev->dev.platform_data;
1333 /* We don't want to handle interrupt without calling mtd routine */
1334 disable_int(info, NDCR_INT_MASK);
1337 * Directly set the chip select to a invalid value,
1338 * then the driver would reset the timing according
1339 * to current chip select at the beginning of cmdfunc
1344 * As the spec says, the NDSR would be updated to 0x1800 when
1345 * doing the nand_clk disable/enable.
1346 * To prevent it damaging state machine of the driver, clear
1347 * all status before resume
1349 nand_writel(info, NDSR, NDSR_MASK);
1350 for (cs = 0; cs < pdata->num_cs; cs++) {
1351 mtd = info->host[cs]->mtd;
1358 #define pxa3xx_nand_suspend NULL
1359 #define pxa3xx_nand_resume NULL
1362 static struct platform_driver pxa3xx_nand_driver = {
1364 .name = "pxa3xx-nand",
1365 .of_match_table = of_match_ptr(pxa3xx_nand_dt_ids),
1367 .probe = pxa3xx_nand_probe,
1368 .remove = pxa3xx_nand_remove,
1369 .suspend = pxa3xx_nand_suspend,
1370 .resume = pxa3xx_nand_resume,
1373 module_platform_driver(pxa3xx_nand_driver);
1375 MODULE_LICENSE("GPL");
1376 MODULE_DESCRIPTION("PXA3xx NAND controller driver");