drivers/mtd/nand/pxa3xx_nand.c

   1 /*
   2  * drivers/mtd/nand/pxa3xx_nand.c
   3  *
   4  * Copyright © 2005 Intel Corporation
   5  * Copyright © 2006 Marvell International Ltd.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/delay.h>
  18 #include <linux/clk.h>
  19 #include <linux/mtd/mtd.h>
  20 #include <linux/mtd/nand.h>
  21 #include <linux/mtd/partitions.h>
  22 #include <linux/io.h>
  23 #include <linux/irq.h>
  24 #include <linux/slab.h>
  25 #include <linux/of.h>
  26 #include <linux/of_device.h>
  27
  28 #include <mach/dma.h>
  29 #include <linux/platform_data/mtd-nand-pxa3xx.h>
  30
  31 #define CHIP_DELAY_TIMEOUT      (2 * HZ/10)
  32 #define NAND_STOP_DELAY         (2 * HZ/50)
  33 #define PAGE_CHUNK_SIZE         (2048)
  34
  35 /* registers and bit definitions */
  36 #define NDCR            (0x00) /* Control register */
  37 #define NDTR0CS0        (0x04) /* Timing Parameter 0 for CS0 */
  38 #define NDTR1CS0        (0x0C) /* Timing Parameter 1 for CS0 */
  39 #define NDSR            (0x14) /* Status Register */
  40 #define NDPCR           (0x18) /* Page Count Register */
  41 #define NDBDR0          (0x1C) /* Bad Block Register 0 */
  42 #define NDBDR1          (0x20) /* Bad Block Register 1 */
  43 #define NDDB            (0x40) /* Data Buffer */
  44 #define NDCB0           (0x48) /* Command Buffer0 */
  45 #define NDCB1           (0x4C) /* Command Buffer1 */
  46 #define NDCB2           (0x50) /* Command Buffer2 */
  47
  48 #define NDCR_SPARE_EN           (0x1 << 31)
  49 #define NDCR_ECC_EN             (0x1 << 30)
  50 #define NDCR_DMA_EN             (0x1 << 29)
  51 #define NDCR_ND_RUN             (0x1 << 28)
  52 #define NDCR_DWIDTH_C           (0x1 << 27)
  53 #define NDCR_DWIDTH_M           (0x1 << 26)
  54 #define NDCR_PAGE_SZ            (0x1 << 24)
  55 #define NDCR_NCSX               (0x1 << 23)
  56 #define NDCR_ND_MODE            (0x3 << 21)
  57 #define NDCR_NAND_MODE          (0x0)
  58 #define NDCR_CLR_PG_CNT         (0x1 << 20)
  59 #define NDCR_STOP_ON_UNCOR      (0x1 << 19)
  60 #define NDCR_RD_ID_CNT_MASK     (0x7 << 16)
  61 #define NDCR_RD_ID_CNT(x)       (((x) << 16) & NDCR_RD_ID_CNT_MASK)
  62
  63 #define NDCR_RA_START           (0x1 << 15)
  64 #define NDCR_PG_PER_BLK         (0x1 << 14)
  65 #define NDCR_ND_ARB_EN          (0x1 << 12)
  66 #define NDCR_INT_MASK           (0xFFF)
  67
  68 #define NDSR_MASK               (0xfff)
  69 #define NDSR_RDY                (0x1 << 12)
  70 #define NDSR_FLASH_RDY          (0x1 << 11)
  71 #define NDSR_CS0_PAGED          (0x1 << 10)
  72 #define NDSR_CS1_PAGED          (0x1 << 9)
  73 #define NDSR_CS0_CMDD           (0x1 << 8)
  74 #define NDSR_CS1_CMDD           (0x1 << 7)
  75 #define NDSR_CS0_BBD            (0x1 << 6)
  76 #define NDSR_CS1_BBD            (0x1 << 5)
  77 #define NDSR_DBERR              (0x1 << 4)
  78 #define NDSR_SBERR              (0x1 << 3)
  79 #define NDSR_WRDREQ             (0x1 << 2)
  80 #define NDSR_RDDREQ             (0x1 << 1)
  81 #define NDSR_WRCMDREQ           (0x1)
  82
  83 #define NDCB0_ST_ROW_EN         (0x1 << 26)
  84 #define NDCB0_AUTO_RS           (0x1 << 25)
  85 #define NDCB0_CSEL              (0x1 << 24)
  86 #define NDCB0_CMD_TYPE_MASK     (0x7 << 21)
  87 #define NDCB0_CMD_TYPE(x)       (((x) << 21) & NDCB0_CMD_TYPE_MASK)
  88 #define NDCB0_NC                (0x1 << 20)
  89 #define NDCB0_DBC               (0x1 << 19)
  90 #define NDCB0_ADDR_CYC_MASK     (0x7 << 16)
  91 #define NDCB0_ADDR_CYC(x)       (((x) << 16) & NDCB0_ADDR_CYC_MASK)
  92 #define NDCB0_CMD2_MASK         (0xff << 8)
  93 #define NDCB0_CMD1_MASK         (0xff)
  94 #define NDCB0_ADDR_CYC_SHIFT    (16)
  95
  96 /* macros for registers read/write */
  97 #define nand_writel(info, off, val)     \
  98         __raw_writel((val), (info)->mmio_base + (off))
  99
 100 #define nand_readl(info, off)           \
 101         __raw_readl((info)->mmio_base + (off))
 102
 103 /* error code and state */
 104 enum {
 105         ERR_NONE        = 0,
 106         ERR_DMABUSERR   = -1,
 107         ERR_SENDCMD     = -2,
 108         ERR_DBERR       = -3,
 109         ERR_BBERR       = -4,
 110         ERR_SBERR       = -5,
 111 };
 112
 113 enum {
 114         STATE_IDLE = 0,
 115         STATE_PREPARED,
 116         STATE_CMD_HANDLE,
 117         STATE_DMA_READING,
 118         STATE_DMA_WRITING,
 119         STATE_DMA_DONE,
 120         STATE_PIO_READING,
 121         STATE_PIO_WRITING,
 122         STATE_CMD_DONE,
 123         STATE_READY,
 124 };
 125
 126 enum pxa3xx_nand_variant {
 127         PXA3XX_NAND_VARIANT_PXA,
 128         PXA3XX_NAND_VARIANT_ARMADA370,
 129 };
 130
 131 struct pxa3xx_nand_host {
 132         struct nand_chip        chip;
 133         struct pxa3xx_nand_cmdset *cmdset;
 134         struct mtd_info         *mtd;
 135         void                    *info_data;
 136
 137         /* page size of attached chip */
 138         unsigned int            page_size;
 139         int                     use_ecc;
 140         int                     cs;
 141
 142         /* calculated from pxa3xx_nand_flash data */
 143         unsigned int            col_addr_cycles;
 144         unsigned int            row_addr_cycles;
 145         size_t                  read_id_bytes;
 146
 147         /* cached register value */
 148         uint32_t                reg_ndcr;
 149         uint32_t                ndtr0cs0;
 150         uint32_t                ndtr1cs0;
 151 };
 152
 153 struct pxa3xx_nand_info {
 154         struct nand_hw_control  controller;
 155         struct platform_device   *pdev;
 156
 157         struct clk              *clk;
 158         void __iomem            *mmio_base;
 159         unsigned long           mmio_phys;
 160         struct completion       cmd_complete;
 161
 162         unsigned int            buf_start;
 163         unsigned int            buf_count;
 164
 165         /* DMA information */
 166         int                     drcmr_dat;
 167         int                     drcmr_cmd;
 168
 169         unsigned char           *data_buff;
 170         unsigned char           *oob_buff;
 171         dma_addr_t              data_buff_phys;
 172         int                     data_dma_ch;
 173         struct pxa_dma_desc     *data_desc;
 174         dma_addr_t              data_desc_addr;
 175
 176         struct pxa3xx_nand_host *host[NUM_CHIP_SELECT];
 177         unsigned int            state;
 178
 179         /*
 180          * This driver supports NFCv1 (as found in PXA SoC)
 181          * and NFCv2 (as found in Armada 370/XP SoC).
 182          */
 183         enum pxa3xx_nand_variant variant;
 184
 185         int                     cs;
 186         int                     use_ecc;        /* use HW ECC ? */
 187         int                     use_dma;        /* use DMA ? */
 188         int                     use_spare;      /* use spare ? */
 189         int                     is_ready;
 190
 191         unsigned int            page_size;      /* page size of attached chip */
 192         unsigned int            data_size;      /* data size in FIFO */
 193         unsigned int            oob_size;
 194         int                     retcode;
 195
 196         /* generated NDCBx register values */
 197         uint32_t                ndcb0;
 198         uint32_t                ndcb1;
 199         uint32_t                ndcb2;
 200         uint32_t                ndcb3;
 201 };
 202
 203 static bool use_dma = 1;
 204 module_param(use_dma, bool, 0444);
 205 MODULE_PARM_DESC(use_dma, "enable DMA for data transferring to/from NAND HW");
 206
 207 /*
 208  * Default NAND flash controller configuration setup by the
 209  * bootloader. This configuration is used only when pdata->keep_config is set
 210  */
 211 static struct pxa3xx_nand_cmdset default_cmdset = {
 212         .read1          = 0x3000,
 213         .read2          = 0x0050,
 214         .program        = 0x1080,
 215         .read_status    = 0x0070,
 216         .read_id        = 0x0090,
 217         .erase          = 0xD060,
 218         .reset          = 0x00FF,
 219         .lock           = 0x002A,
 220         .unlock         = 0x2423,
 221         .lock_status    = 0x007A,
 222 };
 223
 224 static struct pxa3xx_nand_timing timing[] = {
 225         { 40, 80, 60, 100, 80, 100, 90000, 400, 40, },
 226         { 10,  0, 20,  40, 30,  40, 11123, 110, 10, },
 227         { 10, 25, 15,  25, 15,  30, 25000,  60, 10, },
 228         { 10, 35, 15,  25, 15,  25, 25000,  60, 10, },
 229 };
 230
 231 static struct pxa3xx_nand_flash builtin_flash_types[] = {
 232 { "DEFAULT FLASH",      0,   0, 2048,  8,  8,    0, &timing[0] },
 233 { "64MiB 16-bit",  0x46ec,  32,  512, 16, 16, 4096, &timing[1] },
 234 { "256MiB 8-bit",  0xdaec,  64, 2048,  8,  8, 2048, &timing[1] },
 235 { "4GiB 8-bit",    0xd7ec, 128, 4096,  8,  8, 8192, &timing[1] },
 236 { "128MiB 8-bit",  0xa12c,  64, 2048,  8,  8, 1024, &timing[2] },
 237 { "128MiB 16-bit", 0xb12c,  64, 2048, 16, 16, 1024, &timing[2] },
 238 { "512MiB 8-bit",  0xdc2c,  64, 2048,  8,  8, 4096, &timing[2] },
 239 { "512MiB 16-bit", 0xcc2c,  64, 2048, 16, 16, 4096, &timing[2] },
 240 { "256MiB 16-bit", 0xba20,  64, 2048, 16, 16, 2048, &timing[3] },
 241 };
 242
 243 /* Define a default flash type setting serve as flash detecting only */
 244 #define DEFAULT_FLASH_TYPE (&builtin_flash_types[0])
 245
 246 const char *mtd_names[] = {"pxa3xx_nand-0", "pxa3xx_nand-1", NULL};
 247
 248 #define NDTR0_tCH(c)    (min((c), 7) << 19)
 249 #define NDTR0_tCS(c)    (min((c), 7) << 16)
 250 #define NDTR0_tWH(c)    (min((c), 7) << 11)
 251 #define NDTR0_tWP(c)    (min((c), 7) << 8)
 252 #define NDTR0_tRH(c)    (min((c), 7) << 3)
 253 #define NDTR0_tRP(c)    (min((c), 7) << 0)
 254
 255 #define NDTR1_tR(c)     (min((c), 65535) << 16)
 256 #define NDTR1_tWHR(c)   (min((c), 15) << 4)
 257 #define NDTR1_tAR(c)    (min((c), 15) << 0)
 258
 259 /* convert nano-seconds to nand flash controller clock cycles */
 260 #define ns2cycle(ns, clk)       (int)((ns) * (clk / 1000000) / 1000)
 261
 262 static void pxa3xx_nand_set_timing(struct pxa3xx_nand_host *host,
 263                                    const struct pxa3xx_nand_timing *t)
 264 {
 265         struct pxa3xx_nand_info *info = host->info_data;
 266         unsigned long nand_clk = clk_get_rate(info->clk);
 267         uint32_t ndtr0, ndtr1;
 268
 269         ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) |
 270                 NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) |
 271                 NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) |
 272                 NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) |
 273                 NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) |
 274                 NDTR0_tRP(ns2cycle(t->tRP, nand_clk));
 275
 276         ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) |
 277                 NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
 278                 NDTR1_tAR(ns2cycle(t->tAR, nand_clk));
 279
 280         host->ndtr0cs0 = ndtr0;
 281         host->ndtr1cs0 = ndtr1;
 282         nand_writel(info, NDTR0CS0, ndtr0);
 283         nand_writel(info, NDTR1CS0, ndtr1);
 284 }
 285
 286 static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info)
 287 {
 288         struct pxa3xx_nand_host *host = info->host[info->cs];
 289         int oob_enable = host->reg_ndcr & NDCR_SPARE_EN;
 290
 291         info->data_size = host->page_size;
 292         if (!oob_enable) {
 293                 info->oob_size = 0;
 294                 return;
 295         }
 296
 297         switch (host->page_size) {
 298         case 2048:
 299                 info->oob_size = (info->use_ecc) ? 40 : 64;
 300                 break;
 301         case 512:
 302                 info->oob_size = (info->use_ecc) ? 8 : 16;
 303                 break;
 304         }
 305 }
 306
 307 /**
 308  * NOTE: it is a must to set ND_RUN firstly, then write
 309  * command buffer, otherwise, it does not work.
 310  * We enable all the interrupt at the same time, and
 311  * let pxa3xx_nand_irq to handle all logic.
 312  */
 313 static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
 314 {
 315         struct pxa3xx_nand_host *host = info->host[info->cs];
 316         uint32_t ndcr;
 317
 318         ndcr = host->reg_ndcr;
 319
 320         if (info->use_ecc)
 321                 ndcr |= NDCR_ECC_EN;
 322         else
 323                 ndcr &= ~NDCR_ECC_EN;
 324
 325         if (info->use_dma)
 326                 ndcr |= NDCR_DMA_EN;
 327         else
 328                 ndcr &= ~NDCR_DMA_EN;
 329
 330         if (info->use_spare)
 331                 ndcr |= NDCR_SPARE_EN;
 332         else
 333                 ndcr &= ~NDCR_SPARE_EN;
 334
 335         ndcr |= NDCR_ND_RUN;
 336
 337         /* clear status bits and run */
 338         nand_writel(info, NDCR, 0);
 339         nand_writel(info, NDSR, NDSR_MASK);
 340         nand_writel(info, NDCR, ndcr);
 341 }
 342
 343 static void pxa3xx_nand_stop(struct pxa3xx_nand_info *info)
 344 {
 345         uint32_t ndcr;
 346         int timeout = NAND_STOP_DELAY;
 347
 348         /* wait RUN bit in NDCR become 0 */
 349         ndcr = nand_readl(info, NDCR);
 350         while ((ndcr & NDCR_ND_RUN) && (timeout-- > 0)) {
 351                 ndcr = nand_readl(info, NDCR);
 352                 udelay(1);
 353         }
 354
 355         if (timeout <= 0) {
 356                 ndcr &= ~NDCR_ND_RUN;
 357                 nand_writel(info, NDCR, ndcr);
 358         }
 359         /* clear status bits */
 360         nand_writel(info, NDSR, NDSR_MASK);
 361 }
 362
 363 static void enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
 364 {
 365         uint32_t ndcr;
 366
 367         ndcr = nand_readl(info, NDCR);
 368         nand_writel(info, NDCR, ndcr & ~int_mask);
 369 }
 370
 371 static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
 372 {
 373         uint32_t ndcr;
 374
 375         ndcr = nand_readl(info, NDCR);
 376         nand_writel(info, NDCR, ndcr | int_mask);
 377 }
 378
 379 static void handle_data_pio(struct pxa3xx_nand_info *info)
 380 {
 381         switch (info->state) {
 382         case STATE_PIO_WRITING:
 383                 __raw_writesl(info->mmio_base + NDDB, info->data_buff,
 384                                 DIV_ROUND_UP(info->data_size, 4));
 385                 if (info->oob_size > 0)
 386                         __raw_writesl(info->mmio_base + NDDB, info->oob_buff,
 387                                         DIV_ROUND_UP(info->oob_size, 4));
 388                 break;
 389         case STATE_PIO_READING:
 390                 __raw_readsl(info->mmio_base + NDDB, info->data_buff,
 391                                 DIV_ROUND_UP(info->data_size, 4));
 392                 if (info->oob_size > 0)
 393                         __raw_readsl(info->mmio_base + NDDB, info->oob_buff,
 394                                         DIV_ROUND_UP(info->oob_size, 4));
 395                 break;
 396         default:
 397                 dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
 398                                 info->state);
 399                 BUG();
 400         }
 401 }
 402
 403 static void start_data_dma(struct pxa3xx_nand_info *info)
 404 {
 405         struct pxa_dma_desc *desc = info->data_desc;
 406         int dma_len = ALIGN(info->data_size + info->oob_size, 32);
 407
 408         desc->ddadr = DDADR_STOP;
 409         desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len;
 410
 411         switch (info->state) {
 412         case STATE_DMA_WRITING:
 413                 desc->dsadr = info->data_buff_phys;
 414                 desc->dtadr = info->mmio_phys + NDDB;
 415                 desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG;
 416                 break;
 417         case STATE_DMA_READING:
 418                 desc->dtadr = info->data_buff_phys;
 419                 desc->dsadr = info->mmio_phys + NDDB;
 420                 desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC;
 421                 break;
 422         default:
 423                 dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
 424                                 info->state);
 425                 BUG();
 426         }
 427
 428         DRCMR(info->drcmr_dat) = DRCMR_MAPVLD | info->data_dma_ch;
 429         DDADR(info->data_dma_ch) = info->data_desc_addr;
 430         DCSR(info->data_dma_ch) |= DCSR_RUN;
 431 }
 432
 433 static void pxa3xx_nand_data_dma_irq(int channel, void *data)
 434 {
 435         struct pxa3xx_nand_info *info = data;
 436         uint32_t dcsr;
 437
 438         dcsr = DCSR(channel);
 439         DCSR(channel) = dcsr;
 440
 441         if (dcsr & DCSR_BUSERR) {
 442                 info->retcode = ERR_DMABUSERR;
 443         }
 444
 445         info->state = STATE_DMA_DONE;
 446         enable_int(info, NDCR_INT_MASK);
 447         nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);
 448 }
 449
 450 static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
 451 {
 452         struct pxa3xx_nand_info *info = devid;
 453         unsigned int status, is_completed = 0;
 454         unsigned int ready, cmd_done;
 455
 456         if (info->cs == 0) {
 457                 ready           = NDSR_FLASH_RDY;
 458                 cmd_done        = NDSR_CS0_CMDD;
 459         } else {
 460                 ready           = NDSR_RDY;
 461                 cmd_done        = NDSR_CS1_CMDD;
 462         }
 463
 464         status = nand_readl(info, NDSR);
 465
 466         if (status & NDSR_DBERR)
 467                 info->retcode = ERR_DBERR;
 468         if (status & NDSR_SBERR)
 469                 info->retcode = ERR_SBERR;
 470         if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) {
 471                 /* whether use dma to transfer data */
 472                 if (info->use_dma) {
 473                         disable_int(info, NDCR_INT_MASK);
 474                         info->state = (status & NDSR_RDDREQ) ?
 475                                       STATE_DMA_READING : STATE_DMA_WRITING;
 476                         start_data_dma(info);
 477                         goto NORMAL_IRQ_EXIT;
 478                 } else {
 479                         info->state = (status & NDSR_RDDREQ) ?
 480                                       STATE_PIO_READING : STATE_PIO_WRITING;
 481                         handle_data_pio(info);
 482                 }
 483         }
 484         if (status & cmd_done) {
 485                 info->state = STATE_CMD_DONE;
 486                 is_completed = 1;
 487         }
 488         if (status & ready) {
 489                 info->is_ready = 1;
 490                 info->state = STATE_READY;
 491         }
 492
 493         if (status & NDSR_WRCMDREQ) {
 494                 nand_writel(info, NDSR, NDSR_WRCMDREQ);
 495                 status &= ~NDSR_WRCMDREQ;
 496                 info->state = STATE_CMD_HANDLE;
 497
 498                 /*
 499                  * Command buffer registers NDCB{0-2} (and optionally NDCB3)
 500                  * must be loaded by writing directly either 12 or 16
 501                  * bytes directly to NDCB0, four bytes at a time.
 502                  *
 503                  * Direct write access to NDCB1, NDCB2 and NDCB3 is ignored
 504                  * but each NDCBx register can be read.
 505                  */
 506                 nand_writel(info, NDCB0, info->ndcb0);
 507                 nand_writel(info, NDCB0, info->ndcb1);
 508                 nand_writel(info, NDCB0, info->ndcb2);
 509
 510                 /* NDCB3 register is available in NFCv2 (Armada 370/XP SoC) */
 511                 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
 512                         nand_writel(info, NDCB0, info->ndcb3);
 513         }
 514
 515         /* clear NDSR to let the controller exit the IRQ */
 516         nand_writel(info, NDSR, status);
 517         if (is_completed)
 518                 complete(&info->cmd_complete);
 519 NORMAL_IRQ_EXIT:
 520         return IRQ_HANDLED;
 521 }
 522
 523 static inline int is_buf_blank(uint8_t *buf, size_t len)
 524 {
 525         for (; len > 0; len--)
 526                 if (*buf++ != 0xff)
 527                         return 0;
 528         return 1;
 529 }
 530
 531 static int prepare_command_pool(struct pxa3xx_nand_info *info, int command,
 532                 uint16_t column, int page_addr)
 533 {
 534         uint16_t cmd;
 535         int addr_cycle, exec_cmd;
 536         struct pxa3xx_nand_host *host;
 537         struct mtd_info *mtd;
 538
 539         host = info->host[info->cs];
 540         mtd = host->mtd;
 541         addr_cycle = 0;
 542         exec_cmd = 1;
 543
 544         /* reset data and oob column point to handle data */
 545         info->buf_start         = 0;
 546         info->buf_count         = 0;
 547         info->oob_size          = 0;
 548         info->use_ecc           = 0;
 549         info->use_spare         = 1;
 550         info->use_dma           = (use_dma) ? 1 : 0;
 551         info->is_ready          = 0;
 552         info->retcode           = ERR_NONE;
 553         if (info->cs != 0)
 554                 info->ndcb0 = NDCB0_CSEL;
 555         else
 556                 info->ndcb0 = 0;
 557
 558         switch (command) {
 559         case NAND_CMD_READ0:
 560         case NAND_CMD_PAGEPROG:
 561                 info->use_ecc = 1;
 562         case NAND_CMD_READOOB:
 563                 pxa3xx_set_datasize(info);
 564                 break;
 565         case NAND_CMD_SEQIN:
 566                 exec_cmd = 0;
 567                 break;
 568         default:
 569                 info->ndcb1 = 0;
 570                 info->ndcb2 = 0;
 571                 info->ndcb3 = 0;
 572                 break;
 573         }
 574
 575         addr_cycle = NDCB0_ADDR_CYC(host->row_addr_cycles
 576                                     + host->col_addr_cycles);
 577
 578         switch (command) {
 579         case NAND_CMD_READOOB:
 580         case NAND_CMD_READ0:
 581                 cmd = host->cmdset->read1;
 582                 if (command == NAND_CMD_READOOB)
 583                         info->buf_start = mtd->writesize + column;
 584                 else
 585                         info->buf_start = column;
 586
 587                 if (unlikely(host->page_size < PAGE_CHUNK_SIZE))
 588                         info->ndcb0 |= NDCB0_CMD_TYPE(0)
 589                                         | addr_cycle
 590                                         | (cmd & NDCB0_CMD1_MASK);
 591                 else
 592                         info->ndcb0 |= NDCB0_CMD_TYPE(0)
 593                                         | NDCB0_DBC
 594                                         | addr_cycle
 595                                         | cmd;
 596
 597         case NAND_CMD_SEQIN:
 598                 /* small page addr setting */
 599                 if (unlikely(host->page_size < PAGE_CHUNK_SIZE)) {
 600                         info->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
 601                                         | (column & 0xFF);
 602
 603                         info->ndcb2 = 0;
 604                 } else {
 605                         info->ndcb1 = ((page_addr & 0xFFFF) << 16)
 606                                         | (column & 0xFFFF);
 607
 608                         if (page_addr & 0xFF0000)
 609                                 info->ndcb2 = (page_addr & 0xFF0000) >> 16;
 610                         else
 611                                 info->ndcb2 = 0;
 612                 }
 613
 614                 info->buf_count = mtd->writesize + mtd->oobsize;
 615                 memset(info->data_buff, 0xFF, info->buf_count);
 616
 617                 break;
 618
 619         case NAND_CMD_PAGEPROG:
 620                 if (is_buf_blank(info->data_buff,
 621                                         (mtd->writesize + mtd->oobsize))) {
 622                         exec_cmd = 0;
 623                         break;
 624                 }
 625
 626                 cmd = host->cmdset->program;
 627                 info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
 628                                 | NDCB0_AUTO_RS
 629                                 | NDCB0_ST_ROW_EN
 630                                 | NDCB0_DBC
 631                                 | cmd
 632                                 | addr_cycle;
 633                 break;
 634
 635         case NAND_CMD_PARAM:
 636                 cmd = NAND_CMD_PARAM;
 637                 info->buf_count = 256;
 638                 info->ndcb0 |= NDCB0_CMD_TYPE(0)
 639                                 | NDCB0_ADDR_CYC(1)
 640                                 | cmd;
 641                 info->ndcb1 = (column & 0xFF);
 642                 info->data_size = 256;
 643                 break;
 644
 645         case NAND_CMD_READID:
 646                 cmd = host->cmdset->read_id;
 647                 info->buf_count = host->read_id_bytes;
 648                 info->ndcb0 |= NDCB0_CMD_TYPE(3)
 649                                 | NDCB0_ADDR_CYC(1)
 650                                 | cmd;
 651                 info->ndcb1 = (column & 0xFF);
 652
 653                 info->data_size = 8;
 654                 break;
 655         case NAND_CMD_STATUS:
 656                 cmd = host->cmdset->read_status;
 657                 info->buf_count = 1;
 658                 info->ndcb0 |= NDCB0_CMD_TYPE(4)
 659                                 | NDCB0_ADDR_CYC(1)
 660                                 | cmd;
 661
 662                 info->data_size = 8;
 663                 break;
 664
 665         case NAND_CMD_ERASE1:
 666                 cmd = host->cmdset->erase;
 667                 info->ndcb0 |= NDCB0_CMD_TYPE(2)
 668                                 | NDCB0_AUTO_RS
 669                                 | NDCB0_ADDR_CYC(3)
 670                                 | NDCB0_DBC
 671                                 | cmd;
 672                 info->ndcb1 = page_addr;
 673                 info->ndcb2 = 0;
 674
 675                 break;
 676         case NAND_CMD_RESET:
 677                 cmd = host->cmdset->reset;
 678                 info->ndcb0 |= NDCB0_CMD_TYPE(5)
 679                                 | cmd;
 680
 681                 break;
 682
 683         case NAND_CMD_ERASE2:
 684                 exec_cmd = 0;
 685                 break;
 686
 687         default:
 688                 exec_cmd = 0;
 689                 dev_err(&info->pdev->dev, "non-supported command %x\n",
 690                                 command);
 691                 break;
 692         }
 693
 694         return exec_cmd;
 695 }
 696
 697 static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
 698                                 int column, int page_addr)
 699 {
 700         struct pxa3xx_nand_host *host = mtd->priv;
 701         struct pxa3xx_nand_info *info = host->info_data;
 702         int ret, exec_cmd;
 703
 704         /*
 705          * if this is a x16 device ,then convert the input
 706          * "byte" address into a "word" address appropriate
 707          * for indexing a word-oriented device
 708          */
 709         if (host->reg_ndcr & NDCR_DWIDTH_M)
 710                 column /= 2;
 711
 712         /*
 713          * There may be different NAND chip hooked to
 714          * different chip select, so check whether
 715          * chip select has been changed, if yes, reset the timing
 716          */
 717         if (info->cs != host->cs) {
 718                 info->cs = host->cs;
 719                 nand_writel(info, NDTR0CS0, host->ndtr0cs0);
 720                 nand_writel(info, NDTR1CS0, host->ndtr1cs0);
 721         }
 722
 723         info->state = STATE_PREPARED;
 724         exec_cmd = prepare_command_pool(info, command, column, page_addr);
 725         if (exec_cmd) {
 726                 init_completion(&info->cmd_complete);
 727                 pxa3xx_nand_start(info);
 728
 729                 ret = wait_for_completion_timeout(&info->cmd_complete,
 730                                 CHIP_DELAY_TIMEOUT);
 731                 if (!ret) {
 732                         dev_err(&info->pdev->dev, "Wait time out!!!\n");
 733                         /* Stop State Machine for next command cycle */
 734                         pxa3xx_nand_stop(info);
 735                 }
 736         }
 737         info->state = STATE_IDLE;
 738 }
 739
 740 static int pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd,
 741                 struct nand_chip *chip, const uint8_t *buf, int oob_required)
 742 {
 743         chip->write_buf(mtd, buf, mtd->writesize);
 744         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 745
 746         return 0;
 747 }
 748
 749 static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd,
 750                 struct nand_chip *chip, uint8_t *buf, int oob_required,
 751                 int page)
 752 {
 753         struct pxa3xx_nand_host *host = mtd->priv;
 754         struct pxa3xx_nand_info *info = host->info_data;
 755
 756         chip->read_buf(mtd, buf, mtd->writesize);
 757         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 758
 759         if (info->retcode == ERR_SBERR) {
 760                 switch (info->use_ecc) {
 761                 case 1:
 762                         mtd->ecc_stats.corrected++;
 763                         break;
 764                 case 0:
 765                 default:
 766                         break;
 767                 }
 768         } else if (info->retcode == ERR_DBERR) {
 769                 /*
 770                  * for blank page (all 0xff), HW will calculate its ECC as
 771                  * 0, which is different from the ECC information within
 772                  * OOB, ignore such double bit errors
 773                  */
 774                 if (is_buf_blank(buf, mtd->writesize))
 775                         info->retcode = ERR_NONE;
 776                 else
 777                         mtd->ecc_stats.failed++;
 778         }
 779
 780         return 0;
 781 }
 782
 783 static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
 784 {
 785         struct pxa3xx_nand_host *host = mtd->priv;
 786         struct pxa3xx_nand_info *info = host->info_data;
 787         char retval = 0xFF;
 788
 789         if (info->buf_start < info->buf_count)
 790                 /* Has just send a new command? */
 791                 retval = info->data_buff[info->buf_start++];
 792
 793         return retval;
 794 }
 795
 796 static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
 797 {
 798         struct pxa3xx_nand_host *host = mtd->priv;
 799         struct pxa3xx_nand_info *info = host->info_data;
 800         u16 retval = 0xFFFF;
 801
 802         if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) {
 803                 retval = *((u16 *)(info->data_buff+info->buf_start));
 804                 info->buf_start += 2;
 805         }
 806         return retval;
 807 }
 808
 809 static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 810 {
 811         struct pxa3xx_nand_host *host = mtd->priv;
 812         struct pxa3xx_nand_info *info = host->info_data;
 813         int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
 814
 815         memcpy(buf, info->data_buff + info->buf_start, real_len);
 816         info->buf_start += real_len;
 817 }
 818
 819 static void pxa3xx_nand_write_buf(struct mtd_info *mtd,
 820                 const uint8_t *buf, int len)
 821 {
 822         struct pxa3xx_nand_host *host = mtd->priv;
 823         struct pxa3xx_nand_info *info = host->info_data;
 824         int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
 825
 826         memcpy(info->data_buff + info->buf_start, buf, real_len);
 827         info->buf_start += real_len;
 828 }
 829
 830 static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip)
 831 {
 832         return;
 833 }
 834
 835 static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
 836 {
 837         struct pxa3xx_nand_host *host = mtd->priv;
 838         struct pxa3xx_nand_info *info = host->info_data;
 839
 840         /* pxa3xx_nand_send_command has waited for command complete */
 841         if (this->state == FL_WRITING || this->state == FL_ERASING) {
 842                 if (info->retcode == ERR_NONE)
 843                         return 0;
 844                 else {
 845                         /*
 846                          * any error make it return 0x01 which will tell
 847                          * the caller the erase and write fail
 848                          */
 849                         return 0x01;
 850                 }
 851         }
 852
 853         return 0;
 854 }
 855
 856 static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
 857                                     const struct pxa3xx_nand_flash *f)
 858 {
 859         struct platform_device *pdev = info->pdev;
 860         struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
 861         struct pxa3xx_nand_host *host = info->host[info->cs];
 862         uint32_t ndcr = 0x0; /* enable all interrupts */
 863
 864         if (f->page_size != 2048 && f->page_size != 512) {
 865                 dev_err(&pdev->dev, "Current only support 2048 and 512 size\n");
 866                 return -EINVAL;
 867         }
 868
 869         if (f->flash_width != 16 && f->flash_width != 8) {
 870                 dev_err(&pdev->dev, "Only support 8bit and 16 bit!\n");
 871                 return -EINVAL;
 872         }
 873
 874         /* calculate flash information */
 875         host->cmdset = &default_cmdset;
 876         host->page_size = f->page_size;
 877         host->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
 878
 879         /* calculate addressing information */
 880         host->col_addr_cycles = (f->page_size == 2048) ? 2 : 1;
 881
 882         if (f->num_blocks * f->page_per_block > 65536)
 883                 host->row_addr_cycles = 3;
 884         else
 885                 host->row_addr_cycles = 2;
 886
 887         ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
 888         ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0;
 889         ndcr |= (f->page_per_block == 64) ? NDCR_PG_PER_BLK : 0;
 890         ndcr |= (f->page_size == 2048) ? NDCR_PAGE_SZ : 0;
 891         ndcr |= (f->flash_width == 16) ? NDCR_DWIDTH_M : 0;
 892         ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0;
 893
 894         ndcr |= NDCR_RD_ID_CNT(host->read_id_bytes);
 895         ndcr |= NDCR_SPARE_EN; /* enable spare by default */
 896
 897         host->reg_ndcr = ndcr;
 898
 899         pxa3xx_nand_set_timing(host, f->timing);
 900         return 0;
 901 }
 902
 903 static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
 904 {
 905         /*
 906          * We set 0 by hard coding here, for we don't support keep_config
 907          * when there is more than one chip attached to the controller
 908          */
 909         struct pxa3xx_nand_host *host = info->host[0];
 910         uint32_t ndcr = nand_readl(info, NDCR);
 911
 912         if (ndcr & NDCR_PAGE_SZ) {
 913                 host->page_size = 2048;
 914                 host->read_id_bytes = 4;
 915         } else {
 916                 host->page_size = 512;
 917                 host->read_id_bytes = 2;
 918         }
 919
 920         host->reg_ndcr = ndcr & ~NDCR_INT_MASK;
 921         host->cmdset = &default_cmdset;
 922
 923         host->ndtr0cs0 = nand_readl(info, NDTR0CS0);
 924         host->ndtr1cs0 = nand_readl(info, NDTR1CS0);
 925
 926         return 0;
 927 }
 928
 929 /* the maximum possible buffer size for large page with OOB data
 930  * is: 2048 + 64 = 2112 bytes, allocate a page here for both the
 931  * data buffer and the DMA descriptor
 932  */
 933 #define MAX_BUFF_SIZE   PAGE_SIZE
 934
 935 static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
 936 {
 937         struct platform_device *pdev = info->pdev;
 938         int data_desc_offset = MAX_BUFF_SIZE - sizeof(struct pxa_dma_desc);
 939
 940         if (use_dma == 0) {
 941                 info->data_buff = kmalloc(MAX_BUFF_SIZE, GFP_KERNEL);
 942                 if (info->data_buff == NULL)
 943                         return -ENOMEM;
 944                 return 0;
 945         }
 946
 947         info->data_buff = dma_alloc_coherent(&pdev->dev, MAX_BUFF_SIZE,
 948                                 &info->data_buff_phys, GFP_KERNEL);
 949         if (info->data_buff == NULL) {
 950                 dev_err(&pdev->dev, "failed to allocate dma buffer\n");
 951                 return -ENOMEM;
 952         }
 953
 954         info->data_desc = (void *)info->data_buff + data_desc_offset;
 955         info->data_desc_addr = info->data_buff_phys + data_desc_offset;
 956
 957         info->data_dma_ch = pxa_request_dma("nand-data", DMA_PRIO_LOW,
 958                                 pxa3xx_nand_data_dma_irq, info);
 959         if (info->data_dma_ch < 0) {
 960                 dev_err(&pdev->dev, "failed to request data dma\n");
 961                 dma_free_coherent(&pdev->dev, MAX_BUFF_SIZE,
 962                                 info->data_buff, info->data_buff_phys);
 963                 return info->data_dma_ch;
 964         }
 965
 966         return 0;
 967 }
 968
 969 static void pxa3xx_nand_free_buff(struct pxa3xx_nand_info *info)
 970 {
 971         struct platform_device *pdev = info->pdev;
 972         if (use_dma) {
 973                 pxa_free_dma(info->data_dma_ch);
 974                 dma_free_coherent(&pdev->dev, MAX_BUFF_SIZE,
 975                                   info->data_buff, info->data_buff_phys);
 976         } else {
 977                 kfree(info->data_buff);
 978         }
 979 }
 980
 981 static int pxa3xx_nand_sensing(struct pxa3xx_nand_info *info)
 982 {
 983         struct mtd_info *mtd;
 984         int ret;
 985         mtd = info->host[info->cs]->mtd;
 986         /* use the common timing to make a try */
 987         ret = pxa3xx_nand_config_flash(info, &builtin_flash_types[0]);
 988         if (ret)
 989                 return ret;
 990
 991         pxa3xx_nand_cmdfunc(mtd, NAND_CMD_RESET, 0, 0);
 992         if (info->is_ready)
 993                 return 0;
 994
 995         return -ENODEV;
 996 }
 997
 998 static int pxa3xx_nand_scan(struct mtd_info *mtd)
 999 {
1000         struct pxa3xx_nand_host *host = mtd->priv;
1001         struct pxa3xx_nand_info *info = host->info_data;
1002         struct platform_device *pdev = info->pdev;
1003         struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
1004         struct nand_flash_dev pxa3xx_flash_ids[2], *def = NULL;
1005         const struct pxa3xx_nand_flash *f = NULL;
1006         struct nand_chip *chip = mtd->priv;
1007         uint32_t id = -1;
1008         uint64_t chipsize;
1009         int i, ret, num;
1010
1011         if (pdata->keep_config && !pxa3xx_nand_detect_config(info))
1012                 goto KEEP_CONFIG;
1013
1014         ret = pxa3xx_nand_sensing(info);
1015         if (ret) {
1016                 dev_info(&info->pdev->dev, "There is no chip on cs %d!\n",
1017                          info->cs);
1018
1019                 return ret;
1020         }
1021
1022         chip->cmdfunc(mtd, NAND_CMD_READID, 0, 0);
1023         id = *((uint16_t *)(info->data_buff));
1024         if (id != 0)
1025                 dev_info(&info->pdev->dev, "Detect a flash id %x\n", id);
1026         else {
1027                 dev_warn(&info->pdev->dev,
1028                          "Read out ID 0, potential timing set wrong!!\n");
1029
1030                 return -EINVAL;
1031         }
1032
1033         num = ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1;
1034         for (i = 0; i < num; i++) {
1035                 if (i < pdata->num_flash)
1036                         f = pdata->flash + i;
1037                 else
1038                         f = &builtin_flash_types[i - pdata->num_flash + 1];
1039
1040                 /* find the chip in default list */
1041                 if (f->chip_id == id)
1042                         break;
1043         }
1044
1045         if (i >= (ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1)) {
1046                 dev_err(&info->pdev->dev, "ERROR!! flash not defined!!!\n");
1047
1048                 return -EINVAL;
1049         }
1050
1051         ret = pxa3xx_nand_config_flash(info, f);
1052         if (ret) {
1053                 dev_err(&info->pdev->dev, "ERROR! Configure failed\n");
1054                 return ret;
1055         }
1056
1057         pxa3xx_flash_ids[0].name = f->name;
1058         pxa3xx_flash_ids[0].dev_id = (f->chip_id >> 8) & 0xffff;
1059         pxa3xx_flash_ids[0].pagesize = f->page_size;
1060         chipsize = (uint64_t)f->num_blocks * f->page_per_block * f->page_size;
1061         pxa3xx_flash_ids[0].chipsize = chipsize >> 20;
1062         pxa3xx_flash_ids[0].erasesize = f->page_size * f->page_per_block;
1063         if (f->flash_width == 16)
1064                 pxa3xx_flash_ids[0].options = NAND_BUSWIDTH_16;
1065         pxa3xx_flash_ids[1].name = NULL;
1066         def = pxa3xx_flash_ids;
1067 KEEP_CONFIG:
1068         chip->ecc.mode = NAND_ECC_HW;
1069         chip->ecc.size = host->page_size;
1070         chip->ecc.strength = 1;
1071
1072         if (host->reg_ndcr & NDCR_DWIDTH_M)
1073                 chip->options |= NAND_BUSWIDTH_16;
1074
1075         if (nand_scan_ident(mtd, 1, def))
1076                 return -ENODEV;
1077         /* calculate addressing information */
1078         if (mtd->writesize >= 2048)
1079                 host->col_addr_cycles = 2;
1080         else
1081                 host->col_addr_cycles = 1;
1082
1083         info->oob_buff = info->data_buff + mtd->writesize;
1084         if ((mtd->size >> chip->page_shift) > 65536)
1085                 host->row_addr_cycles = 3;
1086         else
1087                 host->row_addr_cycles = 2;
1088
1089         mtd->name = mtd_names[0];
1090         return nand_scan_tail(mtd);
1091 }
1092
1093 static int alloc_nand_resource(struct platform_device *pdev)
1094 {
1095         struct pxa3xx_nand_platform_data *pdata;
1096         struct pxa3xx_nand_info *info;
1097         struct pxa3xx_nand_host *host;
1098         struct nand_chip *chip = NULL;
1099         struct mtd_info *mtd;
1100         struct resource *r;
1101         int ret, irq, cs;
1102
1103         pdata = dev_get_platdata(&pdev->dev);
1104         info = devm_kzalloc(&pdev->dev, sizeof(*info) + (sizeof(*mtd) +
1105                             sizeof(*host)) * pdata->num_cs, GFP_KERNEL);
1106         if (!info)
1107                 return -ENOMEM;
1108
1109         info->pdev = pdev;
1110         for (cs = 0; cs < pdata->num_cs; cs++) {
1111                 mtd = (struct mtd_info *)((unsigned int)&info[1] +
1112                       (sizeof(*mtd) + sizeof(*host)) * cs);
1113                 chip = (struct nand_chip *)(&mtd[1]);
1114                 host = (struct pxa3xx_nand_host *)chip;
1115                 info->host[cs] = host;
1116                 host->mtd = mtd;
1117                 host->cs = cs;
1118                 host->info_data = info;
1119                 mtd->priv = host;
1120                 mtd->owner = THIS_MODULE;
1121
1122                 chip->ecc.read_page     = pxa3xx_nand_read_page_hwecc;
1123                 chip->ecc.write_page    = pxa3xx_nand_write_page_hwecc;
1124                 chip->controller        = &info->controller;
1125                 chip->waitfunc          = pxa3xx_nand_waitfunc;
1126                 chip->select_chip       = pxa3xx_nand_select_chip;
1127                 chip->cmdfunc           = pxa3xx_nand_cmdfunc;
1128                 chip->read_word         = pxa3xx_nand_read_word;
1129                 chip->read_byte         = pxa3xx_nand_read_byte;
1130                 chip->read_buf          = pxa3xx_nand_read_buf;
1131                 chip->write_buf         = pxa3xx_nand_write_buf;
1132         }
1133
1134         spin_lock_init(&chip->controller->lock);
1135         init_waitqueue_head(&chip->controller->wq);
1136         info->clk = devm_clk_get(&pdev->dev, NULL);
1137         if (IS_ERR(info->clk)) {
1138                 dev_err(&pdev->dev, "failed to get nand clock\n");
1139                 return PTR_ERR(info->clk);
1140         }
1141         ret = clk_prepare_enable(info->clk);
1142         if (ret < 0)
1143                 return ret;
1144
1145         /*
1146          * This is a dirty hack to make this driver work from devicetree
1147          * bindings. It can be removed once we have a prober DMA controller
1148          * framework for DT.
1149          */
1150         if (pdev->dev.of_node && of_machine_is_compatible("marvell,pxa3xx")) {
1151                 info->drcmr_dat = 97;
1152                 info->drcmr_cmd = 99;
1153         } else {
1154                 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1155                 if (r == NULL) {
1156                         dev_err(&pdev->dev, "no resource defined for data DMA\n");
1157                         ret = -ENXIO;
1158                         goto fail_disable_clk;
1159                 }
1160                 info->drcmr_dat = r->start;
1161
1162                 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1163                 if (r == NULL) {
1164                         dev_err(&pdev->dev, "no resource defined for command DMA\n");
1165                         ret = -ENXIO;
1166                         goto fail_disable_clk;
1167                 }
1168                 info->drcmr_cmd = r->start;
1169         }
1170
1171         irq = platform_get_irq(pdev, 0);
1172         if (irq < 0) {
1173                 dev_err(&pdev->dev, "no IRQ resource defined\n");
1174                 ret = -ENXIO;
1175                 goto fail_disable_clk;
1176         }
1177
1178         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1179         info->mmio_base = devm_ioremap_resource(&pdev->dev, r);
1180         if (IS_ERR(info->mmio_base)) {
1181                 ret = PTR_ERR(info->mmio_base);
1182                 goto fail_disable_clk;
1183         }
1184         info->mmio_phys = r->start;
1185
1186         ret = pxa3xx_nand_init_buff(info);
1187         if (ret)
1188                 goto fail_disable_clk;
1189
1190         /* initialize all interrupts to be disabled */
1191         disable_int(info, NDSR_MASK);
1192
1193         ret = request_irq(irq, pxa3xx_nand_irq, IRQF_DISABLED,
1194                           pdev->name, info);
1195         if (ret < 0) {
1196                 dev_err(&pdev->dev, "failed to request IRQ\n");
1197                 goto fail_free_buf;
1198         }
1199
1200         platform_set_drvdata(pdev, info);
1201
1202         return 0;
1203
1204 fail_free_buf:
1205         free_irq(irq, info);
1206         pxa3xx_nand_free_buff(info);
1207 fail_disable_clk:
1208         clk_disable_unprepare(info->clk);
1209         return ret;
1210 }
1211
1212 static int pxa3xx_nand_remove(struct platform_device *pdev)
1213 {
1214         struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
1215         struct pxa3xx_nand_platform_data *pdata;
1216         int irq, cs;
1217
1218         if (!info)
1219                 return 0;
1220
1221         pdata = dev_get_platdata(&pdev->dev);
1222
1223         irq = platform_get_irq(pdev, 0);
1224         if (irq >= 0)
1225                 free_irq(irq, info);
1226         pxa3xx_nand_free_buff(info);
1227
1228         clk_disable_unprepare(info->clk);
1229
1230         for (cs = 0; cs < pdata->num_cs; cs++)
1231                 nand_release(info->host[cs]->mtd);
1232         return 0;
1233 }
1234
1235 #ifdef CONFIG_OF
1236 static struct of_device_id pxa3xx_nand_dt_ids[] = {
1237         {
1238                 .compatible = "marvell,pxa3xx-nand",
1239                 .data       = (void *)PXA3XX_NAND_VARIANT_PXA,
1240         },
1241         {
1242                 .compatible = "marvell,armada370-nand",
1243                 .data       = (void *)PXA3XX_NAND_VARIANT_ARMADA370,
1244         },
1245         {}
1246 };
1247 MODULE_DEVICE_TABLE(of, pxa3xx_nand_dt_ids);
1248
1249 static enum pxa3xx_nand_variant
1250 pxa3xx_nand_get_variant(struct platform_device *pdev)
1251 {
1252         const struct of_device_id *of_id =
1253                         of_match_device(pxa3xx_nand_dt_ids, &pdev->dev);
1254         if (!of_id)
1255                 return PXA3XX_NAND_VARIANT_PXA;
1256         return (enum pxa3xx_nand_variant)of_id->data;
1257 }
1258
1259 static int pxa3xx_nand_probe_dt(struct platform_device *pdev)
1260 {
1261         struct pxa3xx_nand_platform_data *pdata;
1262         struct device_node *np = pdev->dev.of_node;
1263         const struct of_device_id *of_id =
1264                         of_match_device(pxa3xx_nand_dt_ids, &pdev->dev);
1265
1266         if (!of_id)
1267                 return 0;
1268
1269         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1270         if (!pdata)
1271                 return -ENOMEM;
1272
1273         if (of_get_property(np, "marvell,nand-enable-arbiter", NULL))
1274                 pdata->enable_arbiter = 1;
1275         if (of_get_property(np, "marvell,nand-keep-config", NULL))
1276                 pdata->keep_config = 1;
1277         of_property_read_u32(np, "num-cs", &pdata->num_cs);
1278
1279         pdev->dev.platform_data = pdata;
1280
1281         return 0;
1282 }
1283 #else
1284 static inline int pxa3xx_nand_probe_dt(struct platform_device *pdev)
1285 {
1286         return 0;
1287 }
1288 #endif
1289
1290 static int pxa3xx_nand_probe(struct platform_device *pdev)
1291 {
1292         struct pxa3xx_nand_platform_data *pdata;
1293         struct mtd_part_parser_data ppdata = {};
1294         struct pxa3xx_nand_info *info;
1295         int ret, cs, probe_success;
1296
1297         ret = pxa3xx_nand_probe_dt(pdev);
1298         if (ret)
1299                 return ret;
1300
1301         pdata = dev_get_platdata(&pdev->dev);
1302         if (!pdata) {
1303                 dev_err(&pdev->dev, "no platform data defined\n");
1304                 return -ENODEV;
1305         }
1306
1307         ret = alloc_nand_resource(pdev);
1308         if (ret) {
1309                 dev_err(&pdev->dev, "alloc nand resource failed\n");
1310                 return ret;
1311         }
1312
1313         info = platform_get_drvdata(pdev);
1314         info->variant = pxa3xx_nand_get_variant(pdev);
1315         probe_success = 0;
1316         for (cs = 0; cs < pdata->num_cs; cs++) {
1317                 info->cs = cs;
1318                 ret = pxa3xx_nand_scan(info->host[cs]->mtd);
1319                 if (ret) {
1320                         dev_warn(&pdev->dev, "failed to scan nand at cs %d\n",
1321                                 cs);
1322                         continue;
1323                 }
1324
1325                 ppdata.of_node = pdev->dev.of_node;
1326                 ret = mtd_device_parse_register(info->host[cs]->mtd, NULL,
1327                                                 &ppdata, pdata->parts[cs],
1328                                                 pdata->nr_parts[cs]);
1329                 if (!ret)
1330                         probe_success = 1;
1331         }
1332
1333         if (!probe_success) {
1334                 pxa3xx_nand_remove(pdev);
1335                 return -ENODEV;
1336         }
1337
1338         return 0;
1339 }
1340
1341 #ifdef CONFIG_PM
1342 static int pxa3xx_nand_suspend(struct platform_device *pdev, pm_message_t state)
1343 {
1344         struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
1345         struct pxa3xx_nand_platform_data *pdata;
1346         struct mtd_info *mtd;
1347         int cs;
1348
1349         pdata = dev_get_platdata(&pdev->dev);
1350         if (info->state) {
1351                 dev_err(&pdev->dev, "driver busy, state = %d\n", info->state);
1352                 return -EAGAIN;
1353         }
1354
1355         for (cs = 0; cs < pdata->num_cs; cs++) {
1356                 mtd = info->host[cs]->mtd;
1357                 mtd_suspend(mtd);
1358         }
1359
1360         return 0;
1361 }
1362
1363 static int pxa3xx_nand_resume(struct platform_device *pdev)
1364 {
1365         struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
1366         struct pxa3xx_nand_platform_data *pdata;
1367         struct mtd_info *mtd;
1368         int cs;
1369
1370         pdata = dev_get_platdata(&pdev->dev);
1371         /* We don't want to handle interrupt without calling mtd routine */
1372         disable_int(info, NDCR_INT_MASK);
1373
1374         /*
1375          * Directly set the chip select to a invalid value,
1376          * then the driver would reset the timing according
1377          * to current chip select at the beginning of cmdfunc
1378          */
1379         info->cs = 0xff;
1380
1381         /*
1382          * As the spec says, the NDSR would be updated to 0x1800 when
1383          * doing the nand_clk disable/enable.
1384          * To prevent it damaging state machine of the driver, clear
1385          * all status before resume
1386          */
1387         nand_writel(info, NDSR, NDSR_MASK);
1388         for (cs = 0; cs < pdata->num_cs; cs++) {
1389                 mtd = info->host[cs]->mtd;
1390                 mtd_resume(mtd);
1391         }
1392
1393         return 0;
1394 }
1395 #else
1396 #define pxa3xx_nand_suspend     NULL
1397 #define pxa3xx_nand_resume      NULL
1398 #endif
1399
1400 static struct platform_driver pxa3xx_nand_driver = {
1401         .driver = {
1402                 .name   = "pxa3xx-nand",
1403                 .of_match_table = of_match_ptr(pxa3xx_nand_dt_ids),
1404         },
1405         .probe          = pxa3xx_nand_probe,
1406         .remove         = pxa3xx_nand_remove,
1407         .suspend        = pxa3xx_nand_suspend,
1408         .resume         = pxa3xx_nand_resume,
1409 };
1410
1411 module_platform_driver(pxa3xx_nand_driver);
1412
1413 MODULE_LICENSE("GPL");
1414 MODULE_DESCRIPTION("PXA3xx NAND controller driver");