drivers/mtd/nand/pxa3xx_nand.c

   1 /*
   2  * drivers/mtd/nand/pxa3xx_nand.c
   3  *
   4  * Copyright © 2005 Intel Corporation
   5  * Copyright © 2006 Marvell International Ltd.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/delay.h>
  18 #include <linux/clk.h>
  19 #include <linux/mtd/mtd.h>
  20 #include <linux/mtd/nand.h>
  21 #include <linux/mtd/partitions.h>
  22 #include <linux/io.h>
  23 #include <linux/irq.h>
  24 #include <linux/slab.h>
  25 #include <linux/of.h>
  26 #include <linux/of_device.h>
  27
  28 #include <mach/dma.h>
  29 #include <linux/platform_data/mtd-nand-pxa3xx.h>
  30
  31 #define CHIP_DELAY_TIMEOUT      (2 * HZ/10)
  32 #define NAND_STOP_DELAY         (2 * HZ/50)
  33 #define PAGE_CHUNK_SIZE         (2048)
  34
  35 /* registers and bit definitions */
  36 #define NDCR            (0x00) /* Control register */
  37 #define NDTR0CS0        (0x04) /* Timing Parameter 0 for CS0 */
  38 #define NDTR1CS0        (0x0C) /* Timing Parameter 1 for CS0 */
  39 #define NDSR            (0x14) /* Status Register */
  40 #define NDPCR           (0x18) /* Page Count Register */
  41 #define NDBDR0          (0x1C) /* Bad Block Register 0 */
  42 #define NDBDR1          (0x20) /* Bad Block Register 1 */
  43 #define NDDB            (0x40) /* Data Buffer */
  44 #define NDCB0           (0x48) /* Command Buffer0 */
  45 #define NDCB1           (0x4C) /* Command Buffer1 */
  46 #define NDCB2           (0x50) /* Command Buffer2 */
  47
  48 #define NDCR_SPARE_EN           (0x1 << 31)
  49 #define NDCR_ECC_EN             (0x1 << 30)
  50 #define NDCR_DMA_EN             (0x1 << 29)
  51 #define NDCR_ND_RUN             (0x1 << 28)
  52 #define NDCR_DWIDTH_C           (0x1 << 27)
  53 #define NDCR_DWIDTH_M           (0x1 << 26)
  54 #define NDCR_PAGE_SZ            (0x1 << 24)
  55 #define NDCR_NCSX               (0x1 << 23)
  56 #define NDCR_ND_MODE            (0x3 << 21)
  57 #define NDCR_NAND_MODE          (0x0)
  58 #define NDCR_CLR_PG_CNT         (0x1 << 20)
  59 #define NDCR_STOP_ON_UNCOR      (0x1 << 19)
  60 #define NDCR_RD_ID_CNT_MASK     (0x7 << 16)
  61 #define NDCR_RD_ID_CNT(x)       (((x) << 16) & NDCR_RD_ID_CNT_MASK)
  62
  63 #define NDCR_RA_START           (0x1 << 15)
  64 #define NDCR_PG_PER_BLK         (0x1 << 14)
  65 #define NDCR_ND_ARB_EN          (0x1 << 12)
  66 #define NDCR_INT_MASK           (0xFFF)
  67
  68 #define NDSR_MASK               (0xfff)
  69 #define NDSR_RDY                (0x1 << 12)
  70 #define NDSR_FLASH_RDY          (0x1 << 11)
  71 #define NDSR_CS0_PAGED          (0x1 << 10)
  72 #define NDSR_CS1_PAGED          (0x1 << 9)
  73 #define NDSR_CS0_CMDD           (0x1 << 8)
  74 #define NDSR_CS1_CMDD           (0x1 << 7)
  75 #define NDSR_CS0_BBD            (0x1 << 6)
  76 #define NDSR_CS1_BBD            (0x1 << 5)
  77 #define NDSR_DBERR              (0x1 << 4)
  78 #define NDSR_SBERR              (0x1 << 3)
  79 #define NDSR_WRDREQ             (0x1 << 2)
  80 #define NDSR_RDDREQ             (0x1 << 1)
  81 #define NDSR_WRCMDREQ           (0x1)
  82
  83 #define NDCB0_LEN_OVRD          (0x1 << 28)
  84 #define NDCB0_ST_ROW_EN         (0x1 << 26)
  85 #define NDCB0_AUTO_RS           (0x1 << 25)
  86 #define NDCB0_CSEL              (0x1 << 24)
  87 #define NDCB0_CMD_TYPE_MASK     (0x7 << 21)
  88 #define NDCB0_CMD_TYPE(x)       (((x) << 21) & NDCB0_CMD_TYPE_MASK)
  89 #define NDCB0_NC                (0x1 << 20)
  90 #define NDCB0_DBC               (0x1 << 19)
  91 #define NDCB0_ADDR_CYC_MASK     (0x7 << 16)
  92 #define NDCB0_ADDR_CYC(x)       (((x) << 16) & NDCB0_ADDR_CYC_MASK)
  93 #define NDCB0_CMD2_MASK         (0xff << 8)
  94 #define NDCB0_CMD1_MASK         (0xff)
  95 #define NDCB0_ADDR_CYC_SHIFT    (16)
  96
  97 /* macros for registers read/write */
  98 #define nand_writel(info, off, val)     \
  99         __raw_writel((val), (info)->mmio_base + (off))
 100
 101 #define nand_readl(info, off)           \
 102         __raw_readl((info)->mmio_base + (off))
 103
 104 /* error code and state */
 105 enum {
 106         ERR_NONE        = 0,
 107         ERR_DMABUSERR   = -1,
 108         ERR_SENDCMD     = -2,
 109         ERR_DBERR       = -3,
 110         ERR_BBERR       = -4,
 111         ERR_SBERR       = -5,
 112 };
 113
 114 enum {
 115         STATE_IDLE = 0,
 116         STATE_PREPARED,
 117         STATE_CMD_HANDLE,
 118         STATE_DMA_READING,
 119         STATE_DMA_WRITING,
 120         STATE_DMA_DONE,
 121         STATE_PIO_READING,
 122         STATE_PIO_WRITING,
 123         STATE_CMD_DONE,
 124         STATE_READY,
 125 };
 126
 127 enum pxa3xx_nand_variant {
 128         PXA3XX_NAND_VARIANT_PXA,
 129         PXA3XX_NAND_VARIANT_ARMADA370,
 130 };
 131
 132 struct pxa3xx_nand_host {
 133         struct nand_chip        chip;
 134         struct mtd_info         *mtd;
 135         void                    *info_data;
 136
 137         /* page size of attached chip */
 138         unsigned int            page_size;
 139         int                     use_ecc;
 140         int                     cs;
 141
 142         /* calculated from pxa3xx_nand_flash data */
 143         unsigned int            col_addr_cycles;
 144         unsigned int            row_addr_cycles;
 145         size_t                  read_id_bytes;
 146
 147 };
 148
 149 struct pxa3xx_nand_info {
 150         struct nand_hw_control  controller;
 151         struct platform_device   *pdev;
 152
 153         struct clk              *clk;
 154         void __iomem            *mmio_base;
 155         unsigned long           mmio_phys;
 156         struct completion       cmd_complete;
 157
 158         unsigned int            buf_start;
 159         unsigned int            buf_count;
 160
 161         /* DMA information */
 162         int                     drcmr_dat;
 163         int                     drcmr_cmd;
 164
 165         unsigned char           *data_buff;
 166         unsigned char           *oob_buff;
 167         dma_addr_t              data_buff_phys;
 168         int                     data_dma_ch;
 169         struct pxa_dma_desc     *data_desc;
 170         dma_addr_t              data_desc_addr;
 171
 172         struct pxa3xx_nand_host *host[NUM_CHIP_SELECT];
 173         unsigned int            state;
 174
 175         /*
 176          * This driver supports NFCv1 (as found in PXA SoC)
 177          * and NFCv2 (as found in Armada 370/XP SoC).
 178          */
 179         enum pxa3xx_nand_variant variant;
 180
 181         int                     cs;
 182         int                     use_ecc;        /* use HW ECC ? */
 183         int                     use_dma;        /* use DMA ? */
 184         int                     use_spare;      /* use spare ? */
 185         int                     is_ready;
 186
 187         unsigned int            page_size;      /* page size of attached chip */
 188         unsigned int            data_size;      /* data size in FIFO */
 189         unsigned int            oob_size;
 190         int                     retcode;
 191
 192         /* cached register value */
 193         uint32_t                reg_ndcr;
 194         uint32_t                ndtr0cs0;
 195         uint32_t                ndtr1cs0;
 196
 197         /* generated NDCBx register values */
 198         uint32_t                ndcb0;
 199         uint32_t                ndcb1;
 200         uint32_t                ndcb2;
 201         uint32_t                ndcb3;
 202 };
 203
 204 static bool use_dma = 1;
 205 module_param(use_dma, bool, 0444);
 206 MODULE_PARM_DESC(use_dma, "enable DMA for data transferring to/from NAND HW");
 207
 208 static struct pxa3xx_nand_timing timing[] = {
 209         { 40, 80, 60, 100, 80, 100, 90000, 400, 40, },
 210         { 10,  0, 20,  40, 30,  40, 11123, 110, 10, },
 211         { 10, 25, 15,  25, 15,  30, 25000,  60, 10, },
 212         { 10, 35, 15,  25, 15,  25, 25000,  60, 10, },
 213 };
 214
 215 static struct pxa3xx_nand_flash builtin_flash_types[] = {
 216 { "DEFAULT FLASH",      0,   0, 2048,  8,  8,    0, &timing[0] },
 217 { "64MiB 16-bit",  0x46ec,  32,  512, 16, 16, 4096, &timing[1] },
 218 { "256MiB 8-bit",  0xdaec,  64, 2048,  8,  8, 2048, &timing[1] },
 219 { "4GiB 8-bit",    0xd7ec, 128, 4096,  8,  8, 8192, &timing[1] },
 220 { "128MiB 8-bit",  0xa12c,  64, 2048,  8,  8, 1024, &timing[2] },
 221 { "128MiB 16-bit", 0xb12c,  64, 2048, 16, 16, 1024, &timing[2] },
 222 { "512MiB 8-bit",  0xdc2c,  64, 2048,  8,  8, 4096, &timing[2] },
 223 { "512MiB 16-bit", 0xcc2c,  64, 2048, 16, 16, 4096, &timing[2] },
 224 { "256MiB 16-bit", 0xba20,  64, 2048, 16, 16, 2048, &timing[3] },
 225 };
 226
 227 /* Define a default flash type setting serve as flash detecting only */
 228 #define DEFAULT_FLASH_TYPE (&builtin_flash_types[0])
 229
 230 #define NDTR0_tCH(c)    (min((c), 7) << 19)
 231 #define NDTR0_tCS(c)    (min((c), 7) << 16)
 232 #define NDTR0_tWH(c)    (min((c), 7) << 11)
 233 #define NDTR0_tWP(c)    (min((c), 7) << 8)
 234 #define NDTR0_tRH(c)    (min((c), 7) << 3)
 235 #define NDTR0_tRP(c)    (min((c), 7) << 0)
 236
 237 #define NDTR1_tR(c)     (min((c), 65535) << 16)
 238 #define NDTR1_tWHR(c)   (min((c), 15) << 4)
 239 #define NDTR1_tAR(c)    (min((c), 15) << 0)
 240
 241 /* convert nano-seconds to nand flash controller clock cycles */
 242 #define ns2cycle(ns, clk)       (int)((ns) * (clk / 1000000) / 1000)
 243
 244 static void pxa3xx_nand_set_timing(struct pxa3xx_nand_host *host,
 245                                    const struct pxa3xx_nand_timing *t)
 246 {
 247         struct pxa3xx_nand_info *info = host->info_data;
 248         unsigned long nand_clk = clk_get_rate(info->clk);
 249         uint32_t ndtr0, ndtr1;
 250
 251         ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) |
 252                 NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) |
 253                 NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) |
 254                 NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) |
 255                 NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) |
 256                 NDTR0_tRP(ns2cycle(t->tRP, nand_clk));
 257
 258         ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) |
 259                 NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
 260                 NDTR1_tAR(ns2cycle(t->tAR, nand_clk));
 261
 262         info->ndtr0cs0 = ndtr0;
 263         info->ndtr1cs0 = ndtr1;
 264         nand_writel(info, NDTR0CS0, ndtr0);
 265         nand_writel(info, NDTR1CS0, ndtr1);
 266 }
 267
 268 static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info)
 269 {
 270         struct pxa3xx_nand_host *host = info->host[info->cs];
 271         int oob_enable = info->reg_ndcr & NDCR_SPARE_EN;
 272
 273         info->data_size = host->page_size;
 274         if (!oob_enable) {
 275                 info->oob_size = 0;
 276                 return;
 277         }
 278
 279         switch (host->page_size) {
 280         case 2048:
 281                 info->oob_size = (info->use_ecc) ? 40 : 64;
 282                 break;
 283         case 512:
 284                 info->oob_size = (info->use_ecc) ? 8 : 16;
 285                 break;
 286         }
 287 }
 288
 289 /**
 290  * NOTE: it is a must to set ND_RUN firstly, then write
 291  * command buffer, otherwise, it does not work.
 292  * We enable all the interrupt at the same time, and
 293  * let pxa3xx_nand_irq to handle all logic.
 294  */
 295 static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
 296 {
 297         uint32_t ndcr;
 298
 299         ndcr = info->reg_ndcr;
 300
 301         if (info->use_ecc)
 302                 ndcr |= NDCR_ECC_EN;
 303         else
 304                 ndcr &= ~NDCR_ECC_EN;
 305
 306         if (info->use_dma)
 307                 ndcr |= NDCR_DMA_EN;
 308         else
 309                 ndcr &= ~NDCR_DMA_EN;
 310
 311         if (info->use_spare)
 312                 ndcr |= NDCR_SPARE_EN;
 313         else
 314                 ndcr &= ~NDCR_SPARE_EN;
 315
 316         ndcr |= NDCR_ND_RUN;
 317
 318         /* clear status bits and run */
 319         nand_writel(info, NDCR, 0);
 320         nand_writel(info, NDSR, NDSR_MASK);
 321         nand_writel(info, NDCR, ndcr);
 322 }
 323
 324 static void pxa3xx_nand_stop(struct pxa3xx_nand_info *info)
 325 {
 326         uint32_t ndcr;
 327         int timeout = NAND_STOP_DELAY;
 328
 329         /* wait RUN bit in NDCR become 0 */
 330         ndcr = nand_readl(info, NDCR);
 331         while ((ndcr & NDCR_ND_RUN) && (timeout-- > 0)) {
 332                 ndcr = nand_readl(info, NDCR);
 333                 udelay(1);
 334         }
 335
 336         if (timeout <= 0) {
 337                 ndcr &= ~NDCR_ND_RUN;
 338                 nand_writel(info, NDCR, ndcr);
 339         }
 340         /* clear status bits */
 341         nand_writel(info, NDSR, NDSR_MASK);
 342 }
 343
 344 static void enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
 345 {
 346         uint32_t ndcr;
 347
 348         ndcr = nand_readl(info, NDCR);
 349         nand_writel(info, NDCR, ndcr & ~int_mask);
 350 }
 351
 352 static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
 353 {
 354         uint32_t ndcr;
 355
 356         ndcr = nand_readl(info, NDCR);
 357         nand_writel(info, NDCR, ndcr | int_mask);
 358 }
 359
 360 static void handle_data_pio(struct pxa3xx_nand_info *info)
 361 {
 362         switch (info->state) {
 363         case STATE_PIO_WRITING:
 364                 __raw_writesl(info->mmio_base + NDDB, info->data_buff,
 365                                 DIV_ROUND_UP(info->data_size, 4));
 366                 if (info->oob_size > 0)
 367                         __raw_writesl(info->mmio_base + NDDB, info->oob_buff,
 368                                         DIV_ROUND_UP(info->oob_size, 4));
 369                 break;
 370         case STATE_PIO_READING:
 371                 __raw_readsl(info->mmio_base + NDDB, info->data_buff,
 372                                 DIV_ROUND_UP(info->data_size, 4));
 373                 if (info->oob_size > 0)
 374                         __raw_readsl(info->mmio_base + NDDB, info->oob_buff,
 375                                         DIV_ROUND_UP(info->oob_size, 4));
 376                 break;
 377         default:
 378                 dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
 379                                 info->state);
 380                 BUG();
 381         }
 382 }
 383
 384 static void start_data_dma(struct pxa3xx_nand_info *info)
 385 {
 386         struct pxa_dma_desc *desc = info->data_desc;
 387         int dma_len = ALIGN(info->data_size + info->oob_size, 32);
 388
 389         desc->ddadr = DDADR_STOP;
 390         desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len;
 391
 392         switch (info->state) {
 393         case STATE_DMA_WRITING:
 394                 desc->dsadr = info->data_buff_phys;
 395                 desc->dtadr = info->mmio_phys + NDDB;
 396                 desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG;
 397                 break;
 398         case STATE_DMA_READING:
 399                 desc->dtadr = info->data_buff_phys;
 400                 desc->dsadr = info->mmio_phys + NDDB;
 401                 desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC;
 402                 break;
 403         default:
 404                 dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
 405                                 info->state);
 406                 BUG();
 407         }
 408
 409         DRCMR(info->drcmr_dat) = DRCMR_MAPVLD | info->data_dma_ch;
 410         DDADR(info->data_dma_ch) = info->data_desc_addr;
 411         DCSR(info->data_dma_ch) |= DCSR_RUN;
 412 }
 413
 414 static void pxa3xx_nand_data_dma_irq(int channel, void *data)
 415 {
 416         struct pxa3xx_nand_info *info = data;
 417         uint32_t dcsr;
 418
 419         dcsr = DCSR(channel);
 420         DCSR(channel) = dcsr;
 421
 422         if (dcsr & DCSR_BUSERR) {
 423                 info->retcode = ERR_DMABUSERR;
 424         }
 425
 426         info->state = STATE_DMA_DONE;
 427         enable_int(info, NDCR_INT_MASK);
 428         nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);
 429 }
 430
 431 static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
 432 {
 433         struct pxa3xx_nand_info *info = devid;
 434         unsigned int status, is_completed = 0;
 435         unsigned int ready, cmd_done;
 436
 437         if (info->cs == 0) {
 438                 ready           = NDSR_FLASH_RDY;
 439                 cmd_done        = NDSR_CS0_CMDD;
 440         } else {
 441                 ready           = NDSR_RDY;
 442                 cmd_done        = NDSR_CS1_CMDD;
 443         }
 444
 445         status = nand_readl(info, NDSR);
 446
 447         if (status & NDSR_DBERR)
 448                 info->retcode = ERR_DBERR;
 449         if (status & NDSR_SBERR)
 450                 info->retcode = ERR_SBERR;
 451         if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) {
 452                 /* whether use dma to transfer data */
 453                 if (info->use_dma) {
 454                         disable_int(info, NDCR_INT_MASK);
 455                         info->state = (status & NDSR_RDDREQ) ?
 456                                       STATE_DMA_READING : STATE_DMA_WRITING;
 457                         start_data_dma(info);
 458                         goto NORMAL_IRQ_EXIT;
 459                 } else {
 460                         info->state = (status & NDSR_RDDREQ) ?
 461                                       STATE_PIO_READING : STATE_PIO_WRITING;
 462                         handle_data_pio(info);
 463                 }
 464         }
 465         if (status & cmd_done) {
 466                 info->state = STATE_CMD_DONE;
 467                 is_completed = 1;
 468         }
 469         if (status & ready) {
 470                 info->is_ready = 1;
 471                 info->state = STATE_READY;
 472         }
 473
 474         if (status & NDSR_WRCMDREQ) {
 475                 nand_writel(info, NDSR, NDSR_WRCMDREQ);
 476                 status &= ~NDSR_WRCMDREQ;
 477                 info->state = STATE_CMD_HANDLE;
 478
 479                 /*
 480                  * Command buffer registers NDCB{0-2} (and optionally NDCB3)
 481                  * must be loaded by writing directly either 12 or 16
 482                  * bytes directly to NDCB0, four bytes at a time.
 483                  *
 484                  * Direct write access to NDCB1, NDCB2 and NDCB3 is ignored
 485                  * but each NDCBx register can be read.
 486                  */
 487                 nand_writel(info, NDCB0, info->ndcb0);
 488                 nand_writel(info, NDCB0, info->ndcb1);
 489                 nand_writel(info, NDCB0, info->ndcb2);
 490
 491                 /* NDCB3 register is available in NFCv2 (Armada 370/XP SoC) */
 492                 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
 493                         nand_writel(info, NDCB0, info->ndcb3);
 494         }
 495
 496         /* clear NDSR to let the controller exit the IRQ */
 497         nand_writel(info, NDSR, status);
 498         if (is_completed)
 499                 complete(&info->cmd_complete);
 500 NORMAL_IRQ_EXIT:
 501         return IRQ_HANDLED;
 502 }
 503
 504 static inline int is_buf_blank(uint8_t *buf, size_t len)
 505 {
 506         for (; len > 0; len--)
 507                 if (*buf++ != 0xff)
 508                         return 0;
 509         return 1;
 510 }
 511
 512 static int prepare_command_pool(struct pxa3xx_nand_info *info, int command,
 513                 uint16_t column, int page_addr)
 514 {
 515         int addr_cycle, exec_cmd;
 516         struct pxa3xx_nand_host *host;
 517         struct mtd_info *mtd;
 518
 519         host = info->host[info->cs];
 520         mtd = host->mtd;
 521         addr_cycle = 0;
 522         exec_cmd = 1;
 523
 524         /* reset data and oob column point to handle data */
 525         info->buf_start         = 0;
 526         info->buf_count         = 0;
 527         info->oob_size          = 0;
 528         info->use_ecc           = 0;
 529         info->use_spare         = 1;
 530         info->use_dma           = (use_dma) ? 1 : 0;
 531         info->is_ready          = 0;
 532         info->retcode           = ERR_NONE;
 533         if (info->cs != 0)
 534                 info->ndcb0 = NDCB0_CSEL;
 535         else
 536                 info->ndcb0 = 0;
 537
 538         switch (command) {
 539         case NAND_CMD_READ0:
 540         case NAND_CMD_PAGEPROG:
 541                 info->use_ecc = 1;
 542         case NAND_CMD_READOOB:
 543                 pxa3xx_set_datasize(info);
 544                 break;
 545         case NAND_CMD_PARAM:
 546                 info->use_spare = 0;
 547                 break;
 548         case NAND_CMD_SEQIN:
 549                 exec_cmd = 0;
 550                 break;
 551         default:
 552                 info->ndcb1 = 0;
 553                 info->ndcb2 = 0;
 554                 info->ndcb3 = 0;
 555                 break;
 556         }
 557
 558         addr_cycle = NDCB0_ADDR_CYC(host->row_addr_cycles
 559                                     + host->col_addr_cycles);
 560
 561         switch (command) {
 562         case NAND_CMD_READOOB:
 563         case NAND_CMD_READ0:
 564                 info->buf_start = column;
 565                 info->ndcb0 |= NDCB0_CMD_TYPE(0)
 566                                 | addr_cycle
 567                                 | NAND_CMD_READ0;
 568
 569                 if (command == NAND_CMD_READOOB)
 570                         info->buf_start += mtd->writesize;
 571
 572                 /* Second command setting for large pages */
 573                 if (host->page_size >= PAGE_CHUNK_SIZE)
 574                         info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8);
 575
 576         case NAND_CMD_SEQIN:
 577                 /* small page addr setting */
 578                 if (unlikely(host->page_size < PAGE_CHUNK_SIZE)) {
 579                         info->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
 580                                         | (column & 0xFF);
 581
 582                         info->ndcb2 = 0;
 583                 } else {
 584                         info->ndcb1 = ((page_addr & 0xFFFF) << 16)
 585                                         | (column & 0xFFFF);
 586
 587                         if (page_addr & 0xFF0000)
 588                                 info->ndcb2 = (page_addr & 0xFF0000) >> 16;
 589                         else
 590                                 info->ndcb2 = 0;
 591                 }
 592
 593                 info->buf_count = mtd->writesize + mtd->oobsize;
 594                 memset(info->data_buff, 0xFF, info->buf_count);
 595
 596                 break;
 597
 598         case NAND_CMD_PAGEPROG:
 599                 if (is_buf_blank(info->data_buff,
 600                                         (mtd->writesize + mtd->oobsize))) {
 601                         exec_cmd = 0;
 602                         break;
 603                 }
 604
 605                 info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
 606                                 | NDCB0_AUTO_RS
 607                                 | NDCB0_ST_ROW_EN
 608                                 | NDCB0_DBC
 609                                 | (NAND_CMD_PAGEPROG << 8)
 610                                 | NAND_CMD_SEQIN
 611                                 | addr_cycle;
 612                 break;
 613
 614         case NAND_CMD_PARAM:
 615                 info->buf_count = 256;
 616                 info->ndcb0 |= NDCB0_CMD_TYPE(0)
 617                                 | NDCB0_ADDR_CYC(1)
 618                                 | NDCB0_LEN_OVRD
 619                                 | command;
 620                 info->ndcb1 = (column & 0xFF);
 621                 info->ndcb3 = 256;
 622                 info->data_size = 256;
 623                 break;
 624
 625         case NAND_CMD_READID:
 626                 info->buf_count = host->read_id_bytes;
 627                 info->ndcb0 |= NDCB0_CMD_TYPE(3)
 628                                 | NDCB0_ADDR_CYC(1)
 629                                 | command;
 630                 info->ndcb1 = (column & 0xFF);
 631
 632                 info->data_size = 8;
 633                 break;
 634         case NAND_CMD_STATUS:
 635                 info->buf_count = 1;
 636                 info->ndcb0 |= NDCB0_CMD_TYPE(4)
 637                                 | NDCB0_ADDR_CYC(1)
 638                                 | command;
 639
 640                 info->data_size = 8;
 641                 break;
 642
 643         case NAND_CMD_ERASE1:
 644                 info->ndcb0 |= NDCB0_CMD_TYPE(2)
 645                                 | NDCB0_AUTO_RS
 646                                 | NDCB0_ADDR_CYC(3)
 647                                 | NDCB0_DBC
 648                                 | (NAND_CMD_ERASE2 << 8)
 649                                 | NAND_CMD_ERASE1;
 650                 info->ndcb1 = page_addr;
 651                 info->ndcb2 = 0;
 652
 653                 break;
 654         case NAND_CMD_RESET:
 655                 info->ndcb0 |= NDCB0_CMD_TYPE(5)
 656                                 | command;
 657
 658                 break;
 659
 660         case NAND_CMD_ERASE2:
 661                 exec_cmd = 0;
 662                 break;
 663
 664         default:
 665                 exec_cmd = 0;
 666                 dev_err(&info->pdev->dev, "non-supported command %x\n",
 667                                 command);
 668                 break;
 669         }
 670
 671         return exec_cmd;
 672 }
 673
 674 static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
 675                                 int column, int page_addr)
 676 {
 677         struct pxa3xx_nand_host *host = mtd->priv;
 678         struct pxa3xx_nand_info *info = host->info_data;
 679         int ret, exec_cmd;
 680
 681         /*
 682          * if this is a x16 device ,then convert the input
 683          * "byte" address into a "word" address appropriate
 684          * for indexing a word-oriented device
 685          */
 686         if (info->reg_ndcr & NDCR_DWIDTH_M)
 687                 column /= 2;
 688
 689         /*
 690          * There may be different NAND chip hooked to
 691          * different chip select, so check whether
 692          * chip select has been changed, if yes, reset the timing
 693          */
 694         if (info->cs != host->cs) {
 695                 info->cs = host->cs;
 696                 nand_writel(info, NDTR0CS0, info->ndtr0cs0);
 697                 nand_writel(info, NDTR1CS0, info->ndtr1cs0);
 698         }
 699
 700         info->state = STATE_PREPARED;
 701         exec_cmd = prepare_command_pool(info, command, column, page_addr);
 702         if (exec_cmd) {
 703                 init_completion(&info->cmd_complete);
 704                 pxa3xx_nand_start(info);
 705
 706                 ret = wait_for_completion_timeout(&info->cmd_complete,
 707                                 CHIP_DELAY_TIMEOUT);
 708                 if (!ret) {
 709                         dev_err(&info->pdev->dev, "Wait time out!!!\n");
 710                         /* Stop State Machine for next command cycle */
 711                         pxa3xx_nand_stop(info);
 712                 }
 713         }
 714         info->state = STATE_IDLE;
 715 }
 716
 717 static int pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd,
 718                 struct nand_chip *chip, const uint8_t *buf, int oob_required)
 719 {
 720         chip->write_buf(mtd, buf, mtd->writesize);
 721         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 722
 723         return 0;
 724 }
 725
 726 static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd,
 727                 struct nand_chip *chip, uint8_t *buf, int oob_required,
 728                 int page)
 729 {
 730         struct pxa3xx_nand_host *host = mtd->priv;
 731         struct pxa3xx_nand_info *info = host->info_data;
 732
 733         chip->read_buf(mtd, buf, mtd->writesize);
 734         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 735
 736         if (info->retcode == ERR_SBERR) {
 737                 switch (info->use_ecc) {
 738                 case 1:
 739                         mtd->ecc_stats.corrected++;
 740                         break;
 741                 case 0:
 742                 default:
 743                         break;
 744                 }
 745         } else if (info->retcode == ERR_DBERR) {
 746                 /*
 747                  * for blank page (all 0xff), HW will calculate its ECC as
 748                  * 0, which is different from the ECC information within
 749                  * OOB, ignore such double bit errors
 750                  */
 751                 if (is_buf_blank(buf, mtd->writesize))
 752                         info->retcode = ERR_NONE;
 753                 else
 754                         mtd->ecc_stats.failed++;
 755         }
 756
 757         return 0;
 758 }
 759
 760 static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
 761 {
 762         struct pxa3xx_nand_host *host = mtd->priv;
 763         struct pxa3xx_nand_info *info = host->info_data;
 764         char retval = 0xFF;
 765
 766         if (info->buf_start < info->buf_count)
 767                 /* Has just send a new command? */
 768                 retval = info->data_buff[info->buf_start++];
 769
 770         return retval;
 771 }
 772
 773 static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
 774 {
 775         struct pxa3xx_nand_host *host = mtd->priv;
 776         struct pxa3xx_nand_info *info = host->info_data;
 777         u16 retval = 0xFFFF;
 778
 779         if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) {
 780                 retval = *((u16 *)(info->data_buff+info->buf_start));
 781                 info->buf_start += 2;
 782         }
 783         return retval;
 784 }
 785
 786 static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 787 {
 788         struct pxa3xx_nand_host *host = mtd->priv;
 789         struct pxa3xx_nand_info *info = host->info_data;
 790         int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
 791
 792         memcpy(buf, info->data_buff + info->buf_start, real_len);
 793         info->buf_start += real_len;
 794 }
 795
 796 static void pxa3xx_nand_write_buf(struct mtd_info *mtd,
 797                 const uint8_t *buf, int len)
 798 {
 799         struct pxa3xx_nand_host *host = mtd->priv;
 800         struct pxa3xx_nand_info *info = host->info_data;
 801         int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
 802
 803         memcpy(info->data_buff + info->buf_start, buf, real_len);
 804         info->buf_start += real_len;
 805 }
 806
 807 static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip)
 808 {
 809         return;
 810 }
 811
 812 static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
 813 {
 814         struct pxa3xx_nand_host *host = mtd->priv;
 815         struct pxa3xx_nand_info *info = host->info_data;
 816
 817         /* pxa3xx_nand_send_command has waited for command complete */
 818         if (this->state == FL_WRITING || this->state == FL_ERASING) {
 819                 if (info->retcode == ERR_NONE)
 820                         return 0;
 821                 else {
 822                         /*
 823                          * any error make it return 0x01 which will tell
 824                          * the caller the erase and write fail
 825                          */
 826                         return 0x01;
 827                 }
 828         }
 829
 830         return 0;
 831 }
 832
 833 static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
 834                                     const struct pxa3xx_nand_flash *f)
 835 {
 836         struct platform_device *pdev = info->pdev;
 837         struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
 838         struct pxa3xx_nand_host *host = info->host[info->cs];
 839         uint32_t ndcr = 0x0; /* enable all interrupts */
 840
 841         if (f->page_size != 2048 && f->page_size != 512) {
 842                 dev_err(&pdev->dev, "Current only support 2048 and 512 size\n");
 843                 return -EINVAL;
 844         }
 845
 846         if (f->flash_width != 16 && f->flash_width != 8) {
 847                 dev_err(&pdev->dev, "Only support 8bit and 16 bit!\n");
 848                 return -EINVAL;
 849         }
 850
 851         /* calculate flash information */
 852         host->page_size = f->page_size;
 853         host->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
 854
 855         /* calculate addressing information */
 856         host->col_addr_cycles = (f->page_size == 2048) ? 2 : 1;
 857
 858         if (f->num_blocks * f->page_per_block > 65536)
 859                 host->row_addr_cycles = 3;
 860         else
 861                 host->row_addr_cycles = 2;
 862
 863         ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
 864         ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0;
 865         ndcr |= (f->page_per_block == 64) ? NDCR_PG_PER_BLK : 0;
 866         ndcr |= (f->page_size == 2048) ? NDCR_PAGE_SZ : 0;
 867         ndcr |= (f->flash_width == 16) ? NDCR_DWIDTH_M : 0;
 868         ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0;
 869
 870         ndcr |= NDCR_RD_ID_CNT(host->read_id_bytes);
 871         ndcr |= NDCR_SPARE_EN; /* enable spare by default */
 872
 873         info->reg_ndcr = ndcr;
 874
 875         pxa3xx_nand_set_timing(host, f->timing);
 876         return 0;
 877 }
 878
 879 static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
 880 {
 881         /*
 882          * We set 0 by hard coding here, for we don't support keep_config
 883          * when there is more than one chip attached to the controller
 884          */
 885         struct pxa3xx_nand_host *host = info->host[0];
 886         uint32_t ndcr = nand_readl(info, NDCR);
 887
 888         if (ndcr & NDCR_PAGE_SZ) {
 889                 host->page_size = 2048;
 890                 host->read_id_bytes = 4;
 891         } else {
 892                 host->page_size = 512;
 893                 host->read_id_bytes = 2;
 894         }
 895
 896         info->reg_ndcr = ndcr & ~NDCR_INT_MASK;
 897         info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
 898         info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
 899         return 0;
 900 }
 901
 902 /* the maximum possible buffer size for large page with OOB data
 903  * is: 2048 + 64 = 2112 bytes, allocate a page here for both the
 904  * data buffer and the DMA descriptor
 905  */
 906 #define MAX_BUFF_SIZE   PAGE_SIZE
 907
 908 static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
 909 {
 910         struct platform_device *pdev = info->pdev;
 911         int data_desc_offset = MAX_BUFF_SIZE - sizeof(struct pxa_dma_desc);
 912
 913         if (use_dma == 0) {
 914                 info->data_buff = kmalloc(MAX_BUFF_SIZE, GFP_KERNEL);
 915                 if (info->data_buff == NULL)
 916                         return -ENOMEM;
 917                 return 0;
 918         }
 919
 920         info->data_buff = dma_alloc_coherent(&pdev->dev, MAX_BUFF_SIZE,
 921                                 &info->data_buff_phys, GFP_KERNEL);
 922         if (info->data_buff == NULL) {
 923                 dev_err(&pdev->dev, "failed to allocate dma buffer\n");
 924                 return -ENOMEM;
 925         }
 926
 927         info->data_desc = (void *)info->data_buff + data_desc_offset;
 928         info->data_desc_addr = info->data_buff_phys + data_desc_offset;
 929
 930         info->data_dma_ch = pxa_request_dma("nand-data", DMA_PRIO_LOW,
 931                                 pxa3xx_nand_data_dma_irq, info);
 932         if (info->data_dma_ch < 0) {
 933                 dev_err(&pdev->dev, "failed to request data dma\n");
 934                 dma_free_coherent(&pdev->dev, MAX_BUFF_SIZE,
 935                                 info->data_buff, info->data_buff_phys);
 936                 return info->data_dma_ch;
 937         }
 938
 939         return 0;
 940 }
 941
 942 static void pxa3xx_nand_free_buff(struct pxa3xx_nand_info *info)
 943 {
 944         struct platform_device *pdev = info->pdev;
 945         if (use_dma) {
 946                 pxa_free_dma(info->data_dma_ch);
 947                 dma_free_coherent(&pdev->dev, MAX_BUFF_SIZE,
 948                                   info->data_buff, info->data_buff_phys);
 949         } else {
 950                 kfree(info->data_buff);
 951         }
 952 }
 953
 954 static int pxa3xx_nand_sensing(struct pxa3xx_nand_info *info)
 955 {
 956         struct mtd_info *mtd;
 957         int ret;
 958         mtd = info->host[info->cs]->mtd;
 959         /* use the common timing to make a try */
 960         ret = pxa3xx_nand_config_flash(info, &builtin_flash_types[0]);
 961         if (ret)
 962                 return ret;
 963
 964         pxa3xx_nand_cmdfunc(mtd, NAND_CMD_RESET, 0, 0);
 965         if (info->is_ready)
 966                 return 0;
 967
 968         return -ENODEV;
 969 }
 970
 971 static int pxa3xx_nand_scan(struct mtd_info *mtd)
 972 {
 973         struct pxa3xx_nand_host *host = mtd->priv;
 974         struct pxa3xx_nand_info *info = host->info_data;
 975         struct platform_device *pdev = info->pdev;
 976         struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
 977         struct nand_flash_dev pxa3xx_flash_ids[2], *def = NULL;
 978         const struct pxa3xx_nand_flash *f = NULL;
 979         struct nand_chip *chip = mtd->priv;
 980         uint32_t id = -1;
 981         uint64_t chipsize;
 982         int i, ret, num;
 983
 984         if (pdata->keep_config && !pxa3xx_nand_detect_config(info))
 985                 goto KEEP_CONFIG;
 986
 987         ret = pxa3xx_nand_sensing(info);
 988         if (ret) {
 989                 dev_info(&info->pdev->dev, "There is no chip on cs %d!\n",
 990                          info->cs);
 991
 992                 return ret;
 993         }
 994
 995         chip->cmdfunc(mtd, NAND_CMD_READID, 0, 0);
 996         id = *((uint16_t *)(info->data_buff));
 997         if (id != 0)
 998                 dev_info(&info->pdev->dev, "Detect a flash id %x\n", id);
 999         else {
1000                 dev_warn(&info->pdev->dev,
1001                          "Read out ID 0, potential timing set wrong!!\n");
1002
1003                 return -EINVAL;
1004         }
1005
1006         num = ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1;
1007         for (i = 0; i < num; i++) {
1008                 if (i < pdata->num_flash)
1009                         f = pdata->flash + i;
1010                 else
1011                         f = &builtin_flash_types[i - pdata->num_flash + 1];
1012
1013                 /* find the chip in default list */
1014                 if (f->chip_id == id)
1015                         break;
1016         }
1017
1018         if (i >= (ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1)) {
1019                 dev_err(&info->pdev->dev, "ERROR!! flash not defined!!!\n");
1020
1021                 return -EINVAL;
1022         }
1023
1024         ret = pxa3xx_nand_config_flash(info, f);
1025         if (ret) {
1026                 dev_err(&info->pdev->dev, "ERROR! Configure failed\n");
1027                 return ret;
1028         }
1029
1030         pxa3xx_flash_ids[0].name = f->name;
1031         pxa3xx_flash_ids[0].dev_id = (f->chip_id >> 8) & 0xffff;
1032         pxa3xx_flash_ids[0].pagesize = f->page_size;
1033         chipsize = (uint64_t)f->num_blocks * f->page_per_block * f->page_size;
1034         pxa3xx_flash_ids[0].chipsize = chipsize >> 20;
1035         pxa3xx_flash_ids[0].erasesize = f->page_size * f->page_per_block;
1036         if (f->flash_width == 16)
1037                 pxa3xx_flash_ids[0].options = NAND_BUSWIDTH_16;
1038         pxa3xx_flash_ids[1].name = NULL;
1039         def = pxa3xx_flash_ids;
1040 KEEP_CONFIG:
1041         chip->ecc.mode = NAND_ECC_HW;
1042         chip->ecc.size = host->page_size;
1043         chip->ecc.strength = 1;
1044
1045         if (info->reg_ndcr & NDCR_DWIDTH_M)
1046                 chip->options |= NAND_BUSWIDTH_16;
1047
1048         if (nand_scan_ident(mtd, 1, def))
1049                 return -ENODEV;
1050         /* calculate addressing information */
1051         if (mtd->writesize >= 2048)
1052                 host->col_addr_cycles = 2;
1053         else
1054                 host->col_addr_cycles = 1;
1055
1056         info->oob_buff = info->data_buff + mtd->writesize;
1057         if ((mtd->size >> chip->page_shift) > 65536)
1058                 host->row_addr_cycles = 3;
1059         else
1060                 host->row_addr_cycles = 2;
1061         return nand_scan_tail(mtd);
1062 }
1063
1064 static int alloc_nand_resource(struct platform_device *pdev)
1065 {
1066         struct pxa3xx_nand_platform_data *pdata;
1067         struct pxa3xx_nand_info *info;
1068         struct pxa3xx_nand_host *host;
1069         struct nand_chip *chip = NULL;
1070         struct mtd_info *mtd;
1071         struct resource *r;
1072         int ret, irq, cs;
1073
1074         pdata = dev_get_platdata(&pdev->dev);
1075         info = devm_kzalloc(&pdev->dev, sizeof(*info) + (sizeof(*mtd) +
1076                             sizeof(*host)) * pdata->num_cs, GFP_KERNEL);
1077         if (!info)
1078                 return -ENOMEM;
1079
1080         info->pdev = pdev;
1081         for (cs = 0; cs < pdata->num_cs; cs++) {
1082                 mtd = (struct mtd_info *)((unsigned int)&info[1] +
1083                       (sizeof(*mtd) + sizeof(*host)) * cs);
1084                 chip = (struct nand_chip *)(&mtd[1]);
1085                 host = (struct pxa3xx_nand_host *)chip;
1086                 info->host[cs] = host;
1087                 host->mtd = mtd;
1088                 host->cs = cs;
1089                 host->info_data = info;
1090                 mtd->priv = host;
1091                 mtd->owner = THIS_MODULE;
1092
1093                 chip->ecc.read_page     = pxa3xx_nand_read_page_hwecc;
1094                 chip->ecc.write_page    = pxa3xx_nand_write_page_hwecc;
1095                 chip->controller        = &info->controller;
1096                 chip->waitfunc          = pxa3xx_nand_waitfunc;
1097                 chip->select_chip       = pxa3xx_nand_select_chip;
1098                 chip->cmdfunc           = pxa3xx_nand_cmdfunc;
1099                 chip->read_word         = pxa3xx_nand_read_word;
1100                 chip->read_byte         = pxa3xx_nand_read_byte;
1101                 chip->read_buf          = pxa3xx_nand_read_buf;
1102                 chip->write_buf         = pxa3xx_nand_write_buf;
1103         }
1104
1105         spin_lock_init(&chip->controller->lock);
1106         init_waitqueue_head(&chip->controller->wq);
1107         info->clk = devm_clk_get(&pdev->dev, NULL);
1108         if (IS_ERR(info->clk)) {
1109                 dev_err(&pdev->dev, "failed to get nand clock\n");
1110                 return PTR_ERR(info->clk);
1111         }
1112         ret = clk_prepare_enable(info->clk);
1113         if (ret < 0)
1114                 return ret;
1115
1116         /*
1117          * This is a dirty hack to make this driver work from devicetree
1118          * bindings. It can be removed once we have a prober DMA controller
1119          * framework for DT.
1120          */
1121         if (pdev->dev.of_node && of_machine_is_compatible("marvell,pxa3xx")) {
1122                 info->drcmr_dat = 97;
1123                 info->drcmr_cmd = 99;
1124         } else {
1125                 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1126                 if (r == NULL) {
1127                         dev_err(&pdev->dev, "no resource defined for data DMA\n");
1128                         ret = -ENXIO;
1129                         goto fail_disable_clk;
1130                 }
1131                 info->drcmr_dat = r->start;
1132
1133                 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1134                 if (r == NULL) {
1135                         dev_err(&pdev->dev, "no resource defined for command DMA\n");
1136                         ret = -ENXIO;
1137                         goto fail_disable_clk;
1138                 }
1139                 info->drcmr_cmd = r->start;
1140         }
1141
1142         irq = platform_get_irq(pdev, 0);
1143         if (irq < 0) {
1144                 dev_err(&pdev->dev, "no IRQ resource defined\n");
1145                 ret = -ENXIO;
1146                 goto fail_disable_clk;
1147         }
1148
1149         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1150         info->mmio_base = devm_ioremap_resource(&pdev->dev, r);
1151         if (IS_ERR(info->mmio_base)) {
1152                 ret = PTR_ERR(info->mmio_base);
1153                 goto fail_disable_clk;
1154         }
1155         info->mmio_phys = r->start;
1156
1157         ret = pxa3xx_nand_init_buff(info);
1158         if (ret)
1159                 goto fail_disable_clk;
1160
1161         /* initialize all interrupts to be disabled */
1162         disable_int(info, NDSR_MASK);
1163
1164         ret = request_irq(irq, pxa3xx_nand_irq, IRQF_DISABLED,
1165                           pdev->name, info);
1166         if (ret < 0) {
1167                 dev_err(&pdev->dev, "failed to request IRQ\n");
1168                 goto fail_free_buf;
1169         }
1170
1171         platform_set_drvdata(pdev, info);
1172
1173         return 0;
1174
1175 fail_free_buf:
1176         free_irq(irq, info);
1177         pxa3xx_nand_free_buff(info);
1178 fail_disable_clk:
1179         clk_disable_unprepare(info->clk);
1180         return ret;
1181 }
1182
1183 static int pxa3xx_nand_remove(struct platform_device *pdev)
1184 {
1185         struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
1186         struct pxa3xx_nand_platform_data *pdata;
1187         int irq, cs;
1188
1189         if (!info)
1190                 return 0;
1191
1192         pdata = dev_get_platdata(&pdev->dev);
1193
1194         irq = platform_get_irq(pdev, 0);
1195         if (irq >= 0)
1196                 free_irq(irq, info);
1197         pxa3xx_nand_free_buff(info);
1198
1199         clk_disable_unprepare(info->clk);
1200
1201         for (cs = 0; cs < pdata->num_cs; cs++)
1202                 nand_release(info->host[cs]->mtd);
1203         return 0;
1204 }
1205
1206 #ifdef CONFIG_OF
1207 static struct of_device_id pxa3xx_nand_dt_ids[] = {
1208         {
1209                 .compatible = "marvell,pxa3xx-nand",
1210                 .data       = (void *)PXA3XX_NAND_VARIANT_PXA,
1211         },
1212         {
1213                 .compatible = "marvell,armada370-nand",
1214                 .data       = (void *)PXA3XX_NAND_VARIANT_ARMADA370,
1215         },
1216         {}
1217 };
1218 MODULE_DEVICE_TABLE(of, pxa3xx_nand_dt_ids);
1219
1220 static enum pxa3xx_nand_variant
1221 pxa3xx_nand_get_variant(struct platform_device *pdev)
1222 {
1223         const struct of_device_id *of_id =
1224                         of_match_device(pxa3xx_nand_dt_ids, &pdev->dev);
1225         if (!of_id)
1226                 return PXA3XX_NAND_VARIANT_PXA;
1227         return (enum pxa3xx_nand_variant)of_id->data;
1228 }
1229
1230 static int pxa3xx_nand_probe_dt(struct platform_device *pdev)
1231 {
1232         struct pxa3xx_nand_platform_data *pdata;
1233         struct device_node *np = pdev->dev.of_node;
1234         const struct of_device_id *of_id =
1235                         of_match_device(pxa3xx_nand_dt_ids, &pdev->dev);
1236
1237         if (!of_id)
1238                 return 0;
1239
1240         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1241         if (!pdata)
1242                 return -ENOMEM;
1243
1244         if (of_get_property(np, "marvell,nand-enable-arbiter", NULL))
1245                 pdata->enable_arbiter = 1;
1246         if (of_get_property(np, "marvell,nand-keep-config", NULL))
1247                 pdata->keep_config = 1;
1248         of_property_read_u32(np, "num-cs", &pdata->num_cs);
1249
1250         pdev->dev.platform_data = pdata;
1251
1252         return 0;
1253 }
1254 #else
1255 static inline int pxa3xx_nand_probe_dt(struct platform_device *pdev)
1256 {
1257         return 0;
1258 }
1259 #endif
1260
1261 static int pxa3xx_nand_probe(struct platform_device *pdev)
1262 {
1263         struct pxa3xx_nand_platform_data *pdata;
1264         struct mtd_part_parser_data ppdata = {};
1265         struct pxa3xx_nand_info *info;
1266         int ret, cs, probe_success;
1267
1268         ret = pxa3xx_nand_probe_dt(pdev);
1269         if (ret)
1270                 return ret;
1271
1272         pdata = dev_get_platdata(&pdev->dev);
1273         if (!pdata) {
1274                 dev_err(&pdev->dev, "no platform data defined\n");
1275                 return -ENODEV;
1276         }
1277
1278         ret = alloc_nand_resource(pdev);
1279         if (ret) {
1280                 dev_err(&pdev->dev, "alloc nand resource failed\n");
1281                 return ret;
1282         }
1283
1284         info = platform_get_drvdata(pdev);
1285         info->variant = pxa3xx_nand_get_variant(pdev);
1286         probe_success = 0;
1287         for (cs = 0; cs < pdata->num_cs; cs++) {
1288                 struct mtd_info *mtd = info->host[cs]->mtd;
1289
1290                 mtd->name = pdev->name;
1291                 info->cs = cs;
1292                 ret = pxa3xx_nand_scan(mtd);
1293                 if (ret) {
1294                         dev_warn(&pdev->dev, "failed to scan nand at cs %d\n",
1295                                 cs);
1296                         continue;
1297                 }
1298
1299                 ppdata.of_node = pdev->dev.of_node;
1300                 ret = mtd_device_parse_register(mtd, NULL,
1301                                                 &ppdata, pdata->parts[cs],
1302                                                 pdata->nr_parts[cs]);
1303                 if (!ret)
1304                         probe_success = 1;
1305         }
1306
1307         if (!probe_success) {
1308                 pxa3xx_nand_remove(pdev);
1309                 return -ENODEV;
1310         }
1311
1312         return 0;
1313 }
1314
1315 #ifdef CONFIG_PM
1316 static int pxa3xx_nand_suspend(struct platform_device *pdev, pm_message_t state)
1317 {
1318         struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
1319         struct pxa3xx_nand_platform_data *pdata;
1320         struct mtd_info *mtd;
1321         int cs;
1322
1323         pdata = dev_get_platdata(&pdev->dev);
1324         if (info->state) {
1325                 dev_err(&pdev->dev, "driver busy, state = %d\n", info->state);
1326                 return -EAGAIN;
1327         }
1328
1329         for (cs = 0; cs < pdata->num_cs; cs++) {
1330                 mtd = info->host[cs]->mtd;
1331                 mtd_suspend(mtd);
1332         }
1333
1334         return 0;
1335 }
1336
1337 static int pxa3xx_nand_resume(struct platform_device *pdev)
1338 {
1339         struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
1340         struct pxa3xx_nand_platform_data *pdata;
1341         struct mtd_info *mtd;
1342         int cs;
1343
1344         pdata = dev_get_platdata(&pdev->dev);
1345         /* We don't want to handle interrupt without calling mtd routine */
1346         disable_int(info, NDCR_INT_MASK);
1347
1348         /*
1349          * Directly set the chip select to a invalid value,
1350          * then the driver would reset the timing according
1351          * to current chip select at the beginning of cmdfunc
1352          */
1353         info->cs = 0xff;
1354
1355         /*
1356          * As the spec says, the NDSR would be updated to 0x1800 when
1357          * doing the nand_clk disable/enable.
1358          * To prevent it damaging state machine of the driver, clear
1359          * all status before resume
1360          */
1361         nand_writel(info, NDSR, NDSR_MASK);
1362         for (cs = 0; cs < pdata->num_cs; cs++) {
1363                 mtd = info->host[cs]->mtd;
1364                 mtd_resume(mtd);
1365         }
1366
1367         return 0;
1368 }
1369 #else
1370 #define pxa3xx_nand_suspend     NULL
1371 #define pxa3xx_nand_resume      NULL
1372 #endif
1373
1374 static struct platform_driver pxa3xx_nand_driver = {
1375         .driver = {
1376                 .name   = "pxa3xx-nand",
1377                 .of_match_table = of_match_ptr(pxa3xx_nand_dt_ids),
1378         },
1379         .probe          = pxa3xx_nand_probe,
1380         .remove         = pxa3xx_nand_remove,
1381         .suspend        = pxa3xx_nand_suspend,
1382         .resume         = pxa3xx_nand_resume,
1383 };
1384
1385 module_platform_driver(pxa3xx_nand_driver);
1386
1387 MODULE_LICENSE("GPL");
1388 MODULE_DESCRIPTION("PXA3xx NAND controller driver");