2 * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
3 * Copyright © 2004 Micron Technology Inc.
4 * Copyright © 2004 David Brownell
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/platform_device.h>
12 #include <linux/dmaengine.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/delay.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/jiffies.h>
18 #include <linux/sched.h>
19 #include <linux/mtd/mtd.h>
20 #include <linux/mtd/nand.h>
21 #include <linux/mtd/partitions.h>
22 #include <linux/omap-dma.h>
24 #include <linux/slab.h>
26 #ifdef CONFIG_MTD_NAND_OMAP_BCH
27 #include <linux/bch.h>
31 #include <plat/gpmc.h>
32 #include <plat/nand.h>
34 #define DRIVER_NAME "omap2-nand"
35 #define OMAP_NAND_TIMEOUT_MS 5000
37 #define NAND_Ecc_P1e (1 << 0)
38 #define NAND_Ecc_P2e (1 << 1)
39 #define NAND_Ecc_P4e (1 << 2)
40 #define NAND_Ecc_P8e (1 << 3)
41 #define NAND_Ecc_P16e (1 << 4)
42 #define NAND_Ecc_P32e (1 << 5)
43 #define NAND_Ecc_P64e (1 << 6)
44 #define NAND_Ecc_P128e (1 << 7)
45 #define NAND_Ecc_P256e (1 << 8)
46 #define NAND_Ecc_P512e (1 << 9)
47 #define NAND_Ecc_P1024e (1 << 10)
48 #define NAND_Ecc_P2048e (1 << 11)
50 #define NAND_Ecc_P1o (1 << 16)
51 #define NAND_Ecc_P2o (1 << 17)
52 #define NAND_Ecc_P4o (1 << 18)
53 #define NAND_Ecc_P8o (1 << 19)
54 #define NAND_Ecc_P16o (1 << 20)
55 #define NAND_Ecc_P32o (1 << 21)
56 #define NAND_Ecc_P64o (1 << 22)
57 #define NAND_Ecc_P128o (1 << 23)
58 #define NAND_Ecc_P256o (1 << 24)
59 #define NAND_Ecc_P512o (1 << 25)
60 #define NAND_Ecc_P1024o (1 << 26)
61 #define NAND_Ecc_P2048o (1 << 27)
63 #define TF(value) (value ? 1 : 0)
65 #define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0)
66 #define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1)
67 #define P1e(a) (TF(a & NAND_Ecc_P1e) << 2)
68 #define P1o(a) (TF(a & NAND_Ecc_P1o) << 3)
69 #define P2e(a) (TF(a & NAND_Ecc_P2e) << 4)
70 #define P2o(a) (TF(a & NAND_Ecc_P2o) << 5)
71 #define P4e(a) (TF(a & NAND_Ecc_P4e) << 6)
72 #define P4o(a) (TF(a & NAND_Ecc_P4o) << 7)
74 #define P8e(a) (TF(a & NAND_Ecc_P8e) << 0)
75 #define P8o(a) (TF(a & NAND_Ecc_P8o) << 1)
76 #define P16e(a) (TF(a & NAND_Ecc_P16e) << 2)
77 #define P16o(a) (TF(a & NAND_Ecc_P16o) << 3)
78 #define P32e(a) (TF(a & NAND_Ecc_P32e) << 4)
79 #define P32o(a) (TF(a & NAND_Ecc_P32o) << 5)
80 #define P64e(a) (TF(a & NAND_Ecc_P64e) << 6)
81 #define P64o(a) (TF(a & NAND_Ecc_P64o) << 7)
83 #define P128e(a) (TF(a & NAND_Ecc_P128e) << 0)
84 #define P128o(a) (TF(a & NAND_Ecc_P128o) << 1)
85 #define P256e(a) (TF(a & NAND_Ecc_P256e) << 2)
86 #define P256o(a) (TF(a & NAND_Ecc_P256o) << 3)
87 #define P512e(a) (TF(a & NAND_Ecc_P512e) << 4)
88 #define P512o(a) (TF(a & NAND_Ecc_P512o) << 5)
89 #define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6)
90 #define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7)
92 #define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0)
93 #define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1)
94 #define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2)
95 #define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3)
96 #define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4)
97 #define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5)
98 #define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6)
99 #define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7)
101 #define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0)
102 #define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1)
104 /* oob info generated runtime depending on ecc algorithm and layout selected */
105 static struct nand_ecclayout omap_oobinfo;
106 /* Define some generic bad / good block scan pattern which are used
107 * while scanning a device for factory marked good / bad blocks
109 static uint8_t scan_ff_pattern[] = { 0xff };
110 static struct nand_bbt_descr bb_descrip_flashbased = {
111 .options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES,
114 .pattern = scan_ff_pattern,
118 struct omap_nand_info {
119 struct nand_hw_control controller;
120 struct omap_nand_platform_data *pdata;
122 struct nand_chip nand;
123 struct platform_device *pdev;
126 unsigned long phys_base;
127 struct completion comp;
128 struct dma_chan *dma;
131 OMAP_NAND_IO_READ = 0, /* read */
132 OMAP_NAND_IO_WRITE, /* write */
137 #ifdef CONFIG_MTD_NAND_OMAP_BCH
138 struct bch_control *bch;
139 struct nand_ecclayout ecclayout;
144 * omap_hwcontrol - hardware specific access to control-lines
145 * @mtd: MTD device structure
146 * @cmd: command to device
148 * NAND_NCE: bit 0 -> don't care
149 * NAND_CLE: bit 1 -> Command Latch
150 * NAND_ALE: bit 2 -> Address Latch
152 * NOTE: boards may use different bits for these!!
154 static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
156 struct omap_nand_info *info = container_of(mtd,
157 struct omap_nand_info, mtd);
159 if (cmd != NAND_CMD_NONE) {
161 gpmc_nand_write(info->gpmc_cs, GPMC_NAND_COMMAND, cmd);
163 else if (ctrl & NAND_ALE)
164 gpmc_nand_write(info->gpmc_cs, GPMC_NAND_ADDRESS, cmd);
167 gpmc_nand_write(info->gpmc_cs, GPMC_NAND_DATA, cmd);
172 * omap_read_buf8 - read data from NAND controller into buffer
173 * @mtd: MTD device structure
174 * @buf: buffer to store date
175 * @len: number of bytes to read
177 static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len)
179 struct nand_chip *nand = mtd->priv;
181 ioread8_rep(nand->IO_ADDR_R, buf, len);
185 * omap_write_buf8 - write buffer to NAND controller
186 * @mtd: MTD device structure
188 * @len: number of bytes to write
190 static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
192 struct omap_nand_info *info = container_of(mtd,
193 struct omap_nand_info, mtd);
194 u_char *p = (u_char *)buf;
198 iowrite8(*p++, info->nand.IO_ADDR_W);
199 /* wait until buffer is available for write */
201 status = gpmc_read_status(GPMC_STATUS_BUFFER);
207 * omap_read_buf16 - read data from NAND controller into buffer
208 * @mtd: MTD device structure
209 * @buf: buffer to store date
210 * @len: number of bytes to read
212 static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
214 struct nand_chip *nand = mtd->priv;
216 ioread16_rep(nand->IO_ADDR_R, buf, len / 2);
220 * omap_write_buf16 - write buffer to NAND controller
221 * @mtd: MTD device structure
223 * @len: number of bytes to write
225 static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
227 struct omap_nand_info *info = container_of(mtd,
228 struct omap_nand_info, mtd);
229 u16 *p = (u16 *) buf;
231 /* FIXME try bursts of writesw() or DMA ... */
235 iowrite16(*p++, info->nand.IO_ADDR_W);
236 /* wait until buffer is available for write */
238 status = gpmc_read_status(GPMC_STATUS_BUFFER);
244 * omap_read_buf_pref - read data from NAND controller into buffer
245 * @mtd: MTD device structure
246 * @buf: buffer to store date
247 * @len: number of bytes to read
249 static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
251 struct omap_nand_info *info = container_of(mtd,
252 struct omap_nand_info, mtd);
253 uint32_t r_count = 0;
257 /* take care of subpage reads */
259 if (info->nand.options & NAND_BUSWIDTH_16)
260 omap_read_buf16(mtd, buf, len % 4);
262 omap_read_buf8(mtd, buf, len % 4);
263 p = (u32 *) (buf + len % 4);
267 /* configure and start prefetch transfer */
268 ret = gpmc_prefetch_enable(info->gpmc_cs,
269 PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0);
271 /* PFPW engine is busy, use cpu copy method */
272 if (info->nand.options & NAND_BUSWIDTH_16)
273 omap_read_buf16(mtd, (u_char *)p, len);
275 omap_read_buf8(mtd, (u_char *)p, len);
278 r_count = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
279 r_count = r_count >> 2;
280 ioread32_rep(info->nand.IO_ADDR_R, p, r_count);
284 /* disable and stop the PFPW engine */
285 gpmc_prefetch_reset(info->gpmc_cs);
290 * omap_write_buf_pref - write buffer to NAND controller
291 * @mtd: MTD device structure
293 * @len: number of bytes to write
295 static void omap_write_buf_pref(struct mtd_info *mtd,
296 const u_char *buf, int len)
298 struct omap_nand_info *info = container_of(mtd,
299 struct omap_nand_info, mtd);
300 uint32_t w_count = 0;
303 unsigned long tim, limit;
305 /* take care of subpage writes */
307 writeb(*buf, info->nand.IO_ADDR_W);
308 p = (u16 *)(buf + 1);
312 /* configure and start prefetch transfer */
313 ret = gpmc_prefetch_enable(info->gpmc_cs,
314 PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1);
316 /* PFPW engine is busy, use cpu copy method */
317 if (info->nand.options & NAND_BUSWIDTH_16)
318 omap_write_buf16(mtd, (u_char *)p, len);
320 omap_write_buf8(mtd, (u_char *)p, len);
323 w_count = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
324 w_count = w_count >> 1;
325 for (i = 0; (i < w_count) && len; i++, len -= 2)
326 iowrite16(*p++, info->nand.IO_ADDR_W);
328 /* wait for data to flushed-out before reset the prefetch */
330 limit = (loops_per_jiffy *
331 msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
332 while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
335 /* disable and stop the PFPW engine */
336 gpmc_prefetch_reset(info->gpmc_cs);
341 * omap_nand_dma_callback: callback on the completion of dma transfer
342 * @data: pointer to completion data structure
344 static void omap_nand_dma_callback(void *data)
346 complete((struct completion *) data);
350 * omap_nand_dma_transfer: configure and start dma transfer
351 * @mtd: MTD device structure
352 * @addr: virtual address in RAM of source/destination
353 * @len: number of data bytes to be transferred
354 * @is_write: flag for read/write operation
356 static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
357 unsigned int len, int is_write)
359 struct omap_nand_info *info = container_of(mtd,
360 struct omap_nand_info, mtd);
361 struct dma_async_tx_descriptor *tx;
362 enum dma_data_direction dir = is_write ? DMA_TO_DEVICE :
364 struct scatterlist sg;
365 unsigned long tim, limit;
369 if (addr >= high_memory) {
372 if (((size_t)addr & PAGE_MASK) !=
373 ((size_t)(addr + len - 1) & PAGE_MASK))
375 p1 = vmalloc_to_page(addr);
378 addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK);
381 sg_init_one(&sg, addr, len);
382 n = dma_map_sg(info->dma->device->dev, &sg, 1, dir);
384 dev_err(&info->pdev->dev,
385 "Couldn't DMA map a %d byte buffer\n", len);
389 tx = dmaengine_prep_slave_sg(info->dma, &sg, n,
390 is_write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
391 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
395 tx->callback = omap_nand_dma_callback;
396 tx->callback_param = &info->comp;
397 dmaengine_submit(tx);
399 /* configure and start prefetch transfer */
400 ret = gpmc_prefetch_enable(info->gpmc_cs,
401 PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write);
403 /* PFPW engine is busy, use cpu copy method */
406 init_completion(&info->comp);
407 dma_async_issue_pending(info->dma);
409 /* setup and start DMA using dma_addr */
410 wait_for_completion(&info->comp);
412 limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
413 while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
416 /* disable and stop the PFPW engine */
417 gpmc_prefetch_reset(info->gpmc_cs);
419 dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
423 dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
425 if (info->nand.options & NAND_BUSWIDTH_16)
426 is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len)
427 : omap_write_buf16(mtd, (u_char *) addr, len);
429 is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len)
430 : omap_write_buf8(mtd, (u_char *) addr, len);
435 * omap_read_buf_dma_pref - read data from NAND controller into buffer
436 * @mtd: MTD device structure
437 * @buf: buffer to store date
438 * @len: number of bytes to read
440 static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len)
442 if (len <= mtd->oobsize)
443 omap_read_buf_pref(mtd, buf, len);
445 /* start transfer in DMA mode */
446 omap_nand_dma_transfer(mtd, buf, len, 0x0);
450 * omap_write_buf_dma_pref - write buffer to NAND controller
451 * @mtd: MTD device structure
453 * @len: number of bytes to write
455 static void omap_write_buf_dma_pref(struct mtd_info *mtd,
456 const u_char *buf, int len)
458 if (len <= mtd->oobsize)
459 omap_write_buf_pref(mtd, buf, len);
461 /* start transfer in DMA mode */
462 omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1);
466 * omap_nand_irq - GPMC irq handler
467 * @this_irq: gpmc irq number
468 * @dev: omap_nand_info structure pointer is passed here
470 static irqreturn_t omap_nand_irq(int this_irq, void *dev)
472 struct omap_nand_info *info = (struct omap_nand_info *) dev;
476 irq_stat = gpmc_read_status(GPMC_GET_IRQ_STATUS);
477 bytes = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
478 bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */
479 if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
483 if (info->buf_len && (info->buf_len < bytes))
484 bytes = info->buf_len;
485 else if (!info->buf_len)
487 iowrite32_rep(info->nand.IO_ADDR_W,
488 (u32 *)info->buf, bytes >> 2);
489 info->buf = info->buf + bytes;
490 info->buf_len -= bytes;
493 ioread32_rep(info->nand.IO_ADDR_R,
494 (u32 *)info->buf, bytes >> 2);
495 info->buf = info->buf + bytes;
500 gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat);
505 complete(&info->comp);
507 gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, 0);
510 gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat);
516 * omap_read_buf_irq_pref - read data from NAND controller into buffer
517 * @mtd: MTD device structure
518 * @buf: buffer to store date
519 * @len: number of bytes to read
521 static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len)
523 struct omap_nand_info *info = container_of(mtd,
524 struct omap_nand_info, mtd);
527 if (len <= mtd->oobsize) {
528 omap_read_buf_pref(mtd, buf, len);
532 info->iomode = OMAP_NAND_IO_READ;
534 init_completion(&info->comp);
536 /* configure and start prefetch transfer */
537 ret = gpmc_prefetch_enable(info->gpmc_cs,
538 PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0);
540 /* PFPW engine is busy, use cpu copy method */
545 gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ,
546 (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT));
548 /* waiting for read to complete */
549 wait_for_completion(&info->comp);
551 /* disable and stop the PFPW engine */
552 gpmc_prefetch_reset(info->gpmc_cs);
556 if (info->nand.options & NAND_BUSWIDTH_16)
557 omap_read_buf16(mtd, buf, len);
559 omap_read_buf8(mtd, buf, len);
563 * omap_write_buf_irq_pref - write buffer to NAND controller
564 * @mtd: MTD device structure
566 * @len: number of bytes to write
568 static void omap_write_buf_irq_pref(struct mtd_info *mtd,
569 const u_char *buf, int len)
571 struct omap_nand_info *info = container_of(mtd,
572 struct omap_nand_info, mtd);
574 unsigned long tim, limit;
576 if (len <= mtd->oobsize) {
577 omap_write_buf_pref(mtd, buf, len);
581 info->iomode = OMAP_NAND_IO_WRITE;
582 info->buf = (u_char *) buf;
583 init_completion(&info->comp);
585 /* configure and start prefetch transfer : size=24 */
586 ret = gpmc_prefetch_enable(info->gpmc_cs,
587 (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1);
589 /* PFPW engine is busy, use cpu copy method */
594 gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ,
595 (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT));
597 /* waiting for write to complete */
598 wait_for_completion(&info->comp);
599 /* wait for data to flushed-out before reset the prefetch */
601 limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
602 while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
605 /* disable and stop the PFPW engine */
606 gpmc_prefetch_reset(info->gpmc_cs);
610 if (info->nand.options & NAND_BUSWIDTH_16)
611 omap_write_buf16(mtd, buf, len);
613 omap_write_buf8(mtd, buf, len);
617 * gen_true_ecc - This function will generate true ECC value
618 * @ecc_buf: buffer to store ecc code
620 * This generated true ECC value can be used when correcting
621 * data read from NAND flash memory core
623 static void gen_true_ecc(u8 *ecc_buf)
625 u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) |
626 ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
628 ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) |
629 P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
630 ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) |
631 P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
632 ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) |
633 P1e(tmp) | P2048o(tmp) | P2048e(tmp));
637 * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
638 * @ecc_data1: ecc code from nand spare area
639 * @ecc_data2: ecc code from hardware register obtained from hardware ecc
640 * @page_data: page data
642 * This function compares two ECC's and indicates if there is an error.
643 * If the error can be corrected it will be corrected to the buffer.
644 * If there is no error, %0 is returned. If there is an error but it
645 * was corrected, %1 is returned. Otherwise, %-1 is returned.
647 static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */
648 u8 *ecc_data2, /* read from register */
652 u8 tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
653 u8 comp0_bit[8], comp1_bit[8], comp2_bit[8];
660 isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
662 gen_true_ecc(ecc_data1);
663 gen_true_ecc(ecc_data2);
665 for (i = 0; i <= 2; i++) {
666 *(ecc_data1 + i) = ~(*(ecc_data1 + i));
667 *(ecc_data2 + i) = ~(*(ecc_data2 + i));
670 for (i = 0; i < 8; i++) {
671 tmp0_bit[i] = *ecc_data1 % 2;
672 *ecc_data1 = *ecc_data1 / 2;
675 for (i = 0; i < 8; i++) {
676 tmp1_bit[i] = *(ecc_data1 + 1) % 2;
677 *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
680 for (i = 0; i < 8; i++) {
681 tmp2_bit[i] = *(ecc_data1 + 2) % 2;
682 *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
685 for (i = 0; i < 8; i++) {
686 comp0_bit[i] = *ecc_data2 % 2;
687 *ecc_data2 = *ecc_data2 / 2;
690 for (i = 0; i < 8; i++) {
691 comp1_bit[i] = *(ecc_data2 + 1) % 2;
692 *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
695 for (i = 0; i < 8; i++) {
696 comp2_bit[i] = *(ecc_data2 + 2) % 2;
697 *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
700 for (i = 0; i < 6; i++)
701 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
703 for (i = 0; i < 8; i++)
704 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
706 for (i = 0; i < 8; i++)
707 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
709 ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
710 ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
712 for (i = 0; i < 24; i++)
713 ecc_sum += ecc_bit[i];
717 /* Not reached because this function is not called if
718 * ECC values are equal
723 /* Uncorrectable error */
724 pr_debug("ECC UNCORRECTED_ERROR 1\n");
728 /* UN-Correctable error */
729 pr_debug("ECC UNCORRECTED_ERROR B\n");
733 /* Correctable error */
734 find_byte = (ecc_bit[23] << 8) +
744 find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
746 pr_debug("Correcting single bit ECC error at offset: "
747 "%d, bit: %d\n", find_byte, find_bit);
749 page_data[find_byte] ^= (1 << find_bit);
754 if (ecc_data2[0] == 0 &&
759 pr_debug("UNCORRECTED_ERROR default\n");
765 * omap_correct_data - Compares the ECC read with HW generated ECC
766 * @mtd: MTD device structure
768 * @read_ecc: ecc read from nand flash
769 * @calc_ecc: ecc read from HW ECC registers
771 * Compares the ecc read from nand spare area with ECC registers values
772 * and if ECC's mismatched, it will call 'omap_compare_ecc' for error
773 * detection and correction. If there are no errors, %0 is returned. If
774 * there were errors and all of the errors were corrected, the number of
775 * corrected errors is returned. If uncorrectable errors exist, %-1 is
778 static int omap_correct_data(struct mtd_info *mtd, u_char *dat,
779 u_char *read_ecc, u_char *calc_ecc)
781 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
783 int blockCnt = 0, i = 0, ret = 0;
786 /* Ex NAND_ECC_HW12_2048 */
787 if ((info->nand.ecc.mode == NAND_ECC_HW) &&
788 (info->nand.ecc.size == 2048))
793 for (i = 0; i < blockCnt; i++) {
794 if (memcmp(read_ecc, calc_ecc, 3) != 0) {
795 ret = omap_compare_ecc(read_ecc, calc_ecc, dat);
798 /* keep track of the number of corrected errors */
809 * omap_calcuate_ecc - Generate non-inverted ECC bytes.
810 * @mtd: MTD device structure
811 * @dat: The pointer to data on which ecc is computed
812 * @ecc_code: The ecc_code buffer
814 * Using noninverted ECC can be considered ugly since writing a blank
815 * page ie. padding will clear the ECC bytes. This is no problem as long
816 * nobody is trying to write data on the seemingly unused page. Reading
817 * an erased page will produce an ECC mismatch between generated and read
818 * ECC bytes that has to be dealt with separately.
820 static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
823 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
825 return gpmc_calculate_ecc(info->gpmc_cs, dat, ecc_code);
829 * omap_enable_hwecc - This function enables the hardware ecc functionality
830 * @mtd: MTD device structure
831 * @mode: Read/Write mode
833 static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
835 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
837 struct nand_chip *chip = mtd->priv;
838 unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
840 gpmc_enable_hwecc(info->gpmc_cs, mode, dev_width, info->nand.ecc.size);
844 * omap_wait - wait until the command is done
845 * @mtd: MTD device structure
846 * @chip: NAND Chip structure
848 * Wait function is called during Program and erase operations and
849 * the way it is called from MTD layer, we should wait till the NAND
850 * chip is ready after the programming/erase operation has completed.
852 * Erase can take up to 400ms and program up to 20ms according to
853 * general NAND and SmartMedia specs
855 static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
857 struct nand_chip *this = mtd->priv;
858 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
860 unsigned long timeo = jiffies;
861 int status, state = this->state;
863 if (state == FL_ERASING)
864 timeo += (HZ * 400) / 1000;
866 timeo += (HZ * 20) / 1000;
868 gpmc_nand_write(info->gpmc_cs,
869 GPMC_NAND_COMMAND, (NAND_CMD_STATUS & 0xFF));
870 while (time_before(jiffies, timeo)) {
871 status = gpmc_nand_read(info->gpmc_cs, GPMC_NAND_DATA);
872 if (status & NAND_STATUS_READY)
877 status = gpmc_nand_read(info->gpmc_cs, GPMC_NAND_DATA);
882 * omap_dev_ready - calls the platform specific dev_ready function
883 * @mtd: MTD device structure
885 static int omap_dev_ready(struct mtd_info *mtd)
887 unsigned int val = 0;
888 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
891 val = gpmc_read_status(GPMC_GET_IRQ_STATUS);
892 if ((val & 0x100) == 0x100) {
893 /* Clear IRQ Interrupt */
896 gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, val);
898 unsigned int cnt = 0;
899 while (cnt++ < 0x1FF) {
900 if ((val & 0x100) == 0x100)
902 val = gpmc_read_status(GPMC_GET_IRQ_STATUS);
909 #ifdef CONFIG_MTD_NAND_OMAP_BCH
912 * omap3_enable_hwecc_bch - Program OMAP3 GPMC to perform BCH ECC correction
913 * @mtd: MTD device structure
914 * @mode: Read/Write mode
916 static void omap3_enable_hwecc_bch(struct mtd_info *mtd, int mode)
919 unsigned int dev_width;
920 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
922 struct nand_chip *chip = mtd->priv;
924 nerrors = (info->nand.ecc.bytes == 13) ? 8 : 4;
925 dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
927 * Program GPMC to perform correction on one 512-byte sector at a time.
928 * Using 4 sectors at a time (i.e. ecc.size = 2048) is also possible and
929 * gives a slight (5%) performance gain (but requires additional code).
931 (void)gpmc_enable_hwecc_bch(info->gpmc_cs, mode, dev_width, 1, nerrors);
935 * omap3_calculate_ecc_bch4 - Generate 7 bytes of ECC bytes
936 * @mtd: MTD device structure
937 * @dat: The pointer to data on which ecc is computed
938 * @ecc_code: The ecc_code buffer
940 static int omap3_calculate_ecc_bch4(struct mtd_info *mtd, const u_char *dat,
943 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
945 return gpmc_calculate_ecc_bch4(info->gpmc_cs, dat, ecc_code);
949 * omap3_calculate_ecc_bch8 - Generate 13 bytes of ECC bytes
950 * @mtd: MTD device structure
951 * @dat: The pointer to data on which ecc is computed
952 * @ecc_code: The ecc_code buffer
954 static int omap3_calculate_ecc_bch8(struct mtd_info *mtd, const u_char *dat,
957 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
959 return gpmc_calculate_ecc_bch8(info->gpmc_cs, dat, ecc_code);
963 * omap3_correct_data_bch - Decode received data and correct errors
964 * @mtd: MTD device structure
966 * @read_ecc: ecc read from nand flash
967 * @calc_ecc: ecc read from HW ECC registers
969 static int omap3_correct_data_bch(struct mtd_info *mtd, u_char *data,
970 u_char *read_ecc, u_char *calc_ecc)
973 /* cannot correct more than 8 errors */
974 unsigned int errloc[8];
975 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
978 count = decode_bch(info->bch, NULL, 512, read_ecc, calc_ecc, NULL,
982 for (i = 0; i < count; i++) {
983 /* correct data only, not ecc bytes */
984 if (errloc[i] < 8*512)
985 data[errloc[i]/8] ^= 1 << (errloc[i] & 7);
986 pr_debug("corrected bitflip %u\n", errloc[i]);
988 } else if (count < 0) {
989 pr_err("ecc unrecoverable error\n");
995 * omap3_free_bch - Release BCH ecc resources
996 * @mtd: MTD device structure
998 static void omap3_free_bch(struct mtd_info *mtd)
1000 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1003 free_bch(info->bch);
1009 * omap3_init_bch - Initialize BCH ECC
1010 * @mtd: MTD device structure
1011 * @ecc_opt: OMAP ECC mode (OMAP_ECC_BCH4_CODE_HW or OMAP_ECC_BCH8_CODE_HW)
1013 static int omap3_init_bch(struct mtd_info *mtd, int ecc_opt)
1015 int ret, max_errors;
1016 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1018 #ifdef CONFIG_MTD_NAND_OMAP_BCH8
1019 const int hw_errors = 8;
1021 const int hw_errors = 4;
1025 max_errors = (ecc_opt == OMAP_ECC_BCH8_CODE_HW) ? 8 : 4;
1026 if (max_errors != hw_errors) {
1027 pr_err("cannot configure %d-bit BCH ecc, only %d-bit supported",
1028 max_errors, hw_errors);
1032 /* initialize GPMC BCH engine */
1033 ret = gpmc_init_hwecc_bch(info->gpmc_cs, 1, max_errors);
1037 /* software bch library is only used to detect and locate errors */
1038 info->bch = init_bch(13, max_errors, 0x201b /* hw polynomial */);
1042 info->nand.ecc.size = 512;
1043 info->nand.ecc.hwctl = omap3_enable_hwecc_bch;
1044 info->nand.ecc.correct = omap3_correct_data_bch;
1045 info->nand.ecc.mode = NAND_ECC_HW;
1048 * The number of corrected errors in an ecc block that will trigger
1049 * block scrubbing defaults to the ecc strength (4 or 8).
1050 * Set mtd->bitflip_threshold here to define a custom threshold.
1053 if (max_errors == 8) {
1054 info->nand.ecc.strength = 8;
1055 info->nand.ecc.bytes = 13;
1056 info->nand.ecc.calculate = omap3_calculate_ecc_bch8;
1058 info->nand.ecc.strength = 4;
1059 info->nand.ecc.bytes = 7;
1060 info->nand.ecc.calculate = omap3_calculate_ecc_bch4;
1063 pr_info("enabling NAND BCH ecc with %d-bit correction\n", max_errors);
1066 omap3_free_bch(mtd);
1071 * omap3_init_bch_tail - Build an oob layout for BCH ECC correction.
1072 * @mtd: MTD device structure
1074 static int omap3_init_bch_tail(struct mtd_info *mtd)
1077 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1079 struct nand_ecclayout *layout = &info->ecclayout;
1081 /* build oob layout */
1082 steps = mtd->writesize/info->nand.ecc.size;
1083 layout->eccbytes = steps*info->nand.ecc.bytes;
1085 /* do not bother creating special oob layouts for small page devices */
1086 if (mtd->oobsize < 64) {
1087 pr_err("BCH ecc is not supported on small page devices\n");
1091 /* reserve 2 bytes for bad block marker */
1092 if (layout->eccbytes+2 > mtd->oobsize) {
1093 pr_err("no oob layout available for oobsize %d eccbytes %u\n",
1094 mtd->oobsize, layout->eccbytes);
1098 /* put ecc bytes at oob tail */
1099 for (i = 0; i < layout->eccbytes; i++)
1100 layout->eccpos[i] = mtd->oobsize-layout->eccbytes+i;
1102 layout->oobfree[0].offset = 2;
1103 layout->oobfree[0].length = mtd->oobsize-2-layout->eccbytes;
1104 info->nand.ecc.layout = layout;
1106 if (!(info->nand.options & NAND_BUSWIDTH_16))
1107 info->nand.badblock_pattern = &bb_descrip_flashbased;
1110 omap3_free_bch(mtd);
1115 static int omap3_init_bch(struct mtd_info *mtd, int ecc_opt)
1117 pr_err("CONFIG_MTD_NAND_OMAP_BCH is not enabled\n");
1120 static int omap3_init_bch_tail(struct mtd_info *mtd)
1124 static void omap3_free_bch(struct mtd_info *mtd)
1127 #endif /* CONFIG_MTD_NAND_OMAP_BCH */
1129 static int __devinit omap_nand_probe(struct platform_device *pdev)
1131 struct omap_nand_info *info;
1132 struct omap_nand_platform_data *pdata;
1135 dma_cap_mask_t mask;
1138 pdata = pdev->dev.platform_data;
1139 if (pdata == NULL) {
1140 dev_err(&pdev->dev, "platform data missing\n");
1144 info = kzalloc(sizeof(struct omap_nand_info), GFP_KERNEL);
1148 platform_set_drvdata(pdev, info);
1150 spin_lock_init(&info->controller.lock);
1151 init_waitqueue_head(&info->controller.wq);
1155 info->gpmc_cs = pdata->cs;
1156 info->phys_base = pdata->phys_base;
1158 info->mtd.priv = &info->nand;
1159 info->mtd.name = dev_name(&pdev->dev);
1160 info->mtd.owner = THIS_MODULE;
1162 info->nand.options = pdata->devsize;
1163 info->nand.options |= NAND_SKIP_BBTSCAN;
1165 /* NAND write protect off */
1166 gpmc_cs_configure(info->gpmc_cs, GPMC_CONFIG_WP, 0);
1168 if (!request_mem_region(info->phys_base, NAND_IO_SIZE,
1169 pdev->dev.driver->name)) {
1174 info->nand.IO_ADDR_R = ioremap(info->phys_base, NAND_IO_SIZE);
1175 if (!info->nand.IO_ADDR_R) {
1177 goto out_release_mem_region;
1180 info->nand.controller = &info->controller;
1182 info->nand.IO_ADDR_W = info->nand.IO_ADDR_R;
1183 info->nand.cmd_ctrl = omap_hwcontrol;
1186 * If RDY/BSY line is connected to OMAP then use the omap ready
1187 * function and the generic nand_wait function which reads the status
1188 * register after monitoring the RDY/BSY line. Otherwise use a standard
1189 * chip delay which is slightly more than tR (AC Timing) of the NAND
1190 * device and read status register until you get a failure or success
1192 if (pdata->dev_ready) {
1193 info->nand.dev_ready = omap_dev_ready;
1194 info->nand.chip_delay = 0;
1196 info->nand.waitfunc = omap_wait;
1197 info->nand.chip_delay = 50;
1200 switch (pdata->xfer_type) {
1201 case NAND_OMAP_PREFETCH_POLLED:
1202 info->nand.read_buf = omap_read_buf_pref;
1203 info->nand.write_buf = omap_write_buf_pref;
1206 case NAND_OMAP_POLLED:
1207 if (info->nand.options & NAND_BUSWIDTH_16) {
1208 info->nand.read_buf = omap_read_buf16;
1209 info->nand.write_buf = omap_write_buf16;
1211 info->nand.read_buf = omap_read_buf8;
1212 info->nand.write_buf = omap_write_buf8;
1216 case NAND_OMAP_PREFETCH_DMA:
1218 dma_cap_set(DMA_SLAVE, mask);
1219 sig = OMAP24XX_DMA_GPMC;
1220 info->dma = dma_request_channel(mask, omap_dma_filter_fn, &sig);
1222 dev_err(&pdev->dev, "DMA engine request failed\n");
1224 goto out_release_mem_region;
1226 struct dma_slave_config cfg;
1228 memset(&cfg, 0, sizeof(cfg));
1229 cfg.src_addr = info->phys_base;
1230 cfg.dst_addr = info->phys_base;
1231 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1232 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1233 cfg.src_maxburst = 16;
1234 cfg.dst_maxburst = 16;
1235 err = dmaengine_slave_config(info->dma, &cfg);
1237 dev_err(&pdev->dev, "DMA engine slave config failed: %d\n",
1239 goto out_release_mem_region;
1241 info->nand.read_buf = omap_read_buf_dma_pref;
1242 info->nand.write_buf = omap_write_buf_dma_pref;
1246 case NAND_OMAP_PREFETCH_IRQ:
1247 err = request_irq(pdata->gpmc_irq,
1248 omap_nand_irq, IRQF_SHARED, "gpmc-nand", info);
1250 dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1251 pdata->gpmc_irq, err);
1252 goto out_release_mem_region;
1254 info->gpmc_irq = pdata->gpmc_irq;
1255 info->nand.read_buf = omap_read_buf_irq_pref;
1256 info->nand.write_buf = omap_write_buf_irq_pref;
1262 "xfer_type(%d) not supported!\n", pdata->xfer_type);
1264 goto out_release_mem_region;
1267 /* select the ecc type */
1268 if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT)
1269 info->nand.ecc.mode = NAND_ECC_SOFT;
1270 else if ((pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW) ||
1271 (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE)) {
1272 info->nand.ecc.bytes = 3;
1273 info->nand.ecc.size = 512;
1274 info->nand.ecc.strength = 1;
1275 info->nand.ecc.calculate = omap_calculate_ecc;
1276 info->nand.ecc.hwctl = omap_enable_hwecc;
1277 info->nand.ecc.correct = omap_correct_data;
1278 info->nand.ecc.mode = NAND_ECC_HW;
1279 } else if ((pdata->ecc_opt == OMAP_ECC_BCH4_CODE_HW) ||
1280 (pdata->ecc_opt == OMAP_ECC_BCH8_CODE_HW)) {
1281 err = omap3_init_bch(&info->mtd, pdata->ecc_opt);
1284 goto out_release_mem_region;
1288 /* DIP switches on some boards change between 8 and 16 bit
1289 * bus widths for flash. Try the other width if the first try fails.
1291 if (nand_scan_ident(&info->mtd, 1, NULL)) {
1292 info->nand.options ^= NAND_BUSWIDTH_16;
1293 if (nand_scan_ident(&info->mtd, 1, NULL)) {
1295 goto out_release_mem_region;
1299 /* rom code layout */
1300 if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE) {
1302 if (info->nand.options & NAND_BUSWIDTH_16)
1306 info->nand.badblock_pattern = &bb_descrip_flashbased;
1308 omap_oobinfo.eccbytes = 3 * (info->mtd.oobsize/16);
1309 for (i = 0; i < omap_oobinfo.eccbytes; i++)
1310 omap_oobinfo.eccpos[i] = i+offset;
1312 omap_oobinfo.oobfree->offset = offset + omap_oobinfo.eccbytes;
1313 omap_oobinfo.oobfree->length = info->mtd.oobsize -
1314 (offset + omap_oobinfo.eccbytes);
1316 info->nand.ecc.layout = &omap_oobinfo;
1317 } else if ((pdata->ecc_opt == OMAP_ECC_BCH4_CODE_HW) ||
1318 (pdata->ecc_opt == OMAP_ECC_BCH8_CODE_HW)) {
1319 /* build OOB layout for BCH ECC correction */
1320 err = omap3_init_bch_tail(&info->mtd);
1323 goto out_release_mem_region;
1327 /* second phase scan */
1328 if (nand_scan_tail(&info->mtd)) {
1330 goto out_release_mem_region;
1333 mtd_device_parse_register(&info->mtd, NULL, NULL, pdata->parts,
1336 platform_set_drvdata(pdev, &info->mtd);
1340 out_release_mem_region:
1342 dma_release_channel(info->dma);
1343 release_mem_region(info->phys_base, NAND_IO_SIZE);
1350 static int omap_nand_remove(struct platform_device *pdev)
1352 struct mtd_info *mtd = platform_get_drvdata(pdev);
1353 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1355 omap3_free_bch(&info->mtd);
1357 platform_set_drvdata(pdev, NULL);
1359 dma_release_channel(info->dma);
1362 free_irq(info->gpmc_irq, info);
1364 /* Release NAND device, its internal structures and partitions */
1365 nand_release(&info->mtd);
1366 iounmap(info->nand.IO_ADDR_R);
1371 static struct platform_driver omap_nand_driver = {
1372 .probe = omap_nand_probe,
1373 .remove = omap_nand_remove,
1375 .name = DRIVER_NAME,
1376 .owner = THIS_MODULE,
1380 module_platform_driver(omap_nand_driver);
1382 MODULE_ALIAS("platform:" DRIVER_NAME);
1383 MODULE_LICENSE("GPL");
1384 MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");