drivers/mtd/nand/omap2.c

   1 /*
   2  * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
   3  * Copyright © 2004 Micron Technology Inc.
   4  * Copyright © 2004 David Brownell
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/platform_device.h>
  12 #include <linux/dmaengine.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/delay.h>
  15 #include <linux/module.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/jiffies.h>
  18 #include <linux/sched.h>
  19 #include <linux/mtd/mtd.h>
  20 #include <linux/mtd/nand.h>
  21 #include <linux/mtd/partitions.h>
  22 #include <linux/omap-dma.h>
  23 #include <linux/io.h>
  24 #include <linux/slab.h>
  25
  26 #ifdef CONFIG_MTD_NAND_OMAP_BCH
  27 #include <linux/bch.h>
  28 #endif
  29
  30 #include <plat/dma.h>
  31 #include <plat/gpmc.h>
  32 #include <plat/nand.h>
  33
  34 #define DRIVER_NAME     "omap2-nand"
  35 #define OMAP_NAND_TIMEOUT_MS    5000
  36
  37 #define NAND_Ecc_P1e            (1 << 0)
  38 #define NAND_Ecc_P2e            (1 << 1)
  39 #define NAND_Ecc_P4e            (1 << 2)
  40 #define NAND_Ecc_P8e            (1 << 3)
  41 #define NAND_Ecc_P16e           (1 << 4)
  42 #define NAND_Ecc_P32e           (1 << 5)
  43 #define NAND_Ecc_P64e           (1 << 6)
  44 #define NAND_Ecc_P128e          (1 << 7)
  45 #define NAND_Ecc_P256e          (1 << 8)
  46 #define NAND_Ecc_P512e          (1 << 9)
  47 #define NAND_Ecc_P1024e         (1 << 10)
  48 #define NAND_Ecc_P2048e         (1 << 11)
  49
  50 #define NAND_Ecc_P1o            (1 << 16)
  51 #define NAND_Ecc_P2o            (1 << 17)
  52 #define NAND_Ecc_P4o            (1 << 18)
  53 #define NAND_Ecc_P8o            (1 << 19)
  54 #define NAND_Ecc_P16o           (1 << 20)
  55 #define NAND_Ecc_P32o           (1 << 21)
  56 #define NAND_Ecc_P64o           (1 << 22)
  57 #define NAND_Ecc_P128o          (1 << 23)
  58 #define NAND_Ecc_P256o          (1 << 24)
  59 #define NAND_Ecc_P512o          (1 << 25)
  60 #define NAND_Ecc_P1024o         (1 << 26)
  61 #define NAND_Ecc_P2048o         (1 << 27)
  62
  63 #define TF(value)       (value ? 1 : 0)
  64
  65 #define P2048e(a)       (TF(a & NAND_Ecc_P2048e)        << 0)
  66 #define P2048o(a)       (TF(a & NAND_Ecc_P2048o)        << 1)
  67 #define P1e(a)          (TF(a & NAND_Ecc_P1e)           << 2)
  68 #define P1o(a)          (TF(a & NAND_Ecc_P1o)           << 3)
  69 #define P2e(a)          (TF(a & NAND_Ecc_P2e)           << 4)
  70 #define P2o(a)          (TF(a & NAND_Ecc_P2o)           << 5)
  71 #define P4e(a)          (TF(a & NAND_Ecc_P4e)           << 6)
  72 #define P4o(a)          (TF(a & NAND_Ecc_P4o)           << 7)
  73
  74 #define P8e(a)          (TF(a & NAND_Ecc_P8e)           << 0)
  75 #define P8o(a)          (TF(a & NAND_Ecc_P8o)           << 1)
  76 #define P16e(a)         (TF(a & NAND_Ecc_P16e)          << 2)
  77 #define P16o(a)         (TF(a & NAND_Ecc_P16o)          << 3)
  78 #define P32e(a)         (TF(a & NAND_Ecc_P32e)          << 4)
  79 #define P32o(a)         (TF(a & NAND_Ecc_P32o)          << 5)
  80 #define P64e(a)         (TF(a & NAND_Ecc_P64e)          << 6)
  81 #define P64o(a)         (TF(a & NAND_Ecc_P64o)          << 7)
  82
  83 #define P128e(a)        (TF(a & NAND_Ecc_P128e)         << 0)
  84 #define P128o(a)        (TF(a & NAND_Ecc_P128o)         << 1)
  85 #define P256e(a)        (TF(a & NAND_Ecc_P256e)         << 2)
  86 #define P256o(a)        (TF(a & NAND_Ecc_P256o)         << 3)
  87 #define P512e(a)        (TF(a & NAND_Ecc_P512e)         << 4)
  88 #define P512o(a)        (TF(a & NAND_Ecc_P512o)         << 5)
  89 #define P1024e(a)       (TF(a & NAND_Ecc_P1024e)        << 6)
  90 #define P1024o(a)       (TF(a & NAND_Ecc_P1024o)        << 7)
  91
  92 #define P8e_s(a)        (TF(a & NAND_Ecc_P8e)           << 0)
  93 #define P8o_s(a)        (TF(a & NAND_Ecc_P8o)           << 1)
  94 #define P16e_s(a)       (TF(a & NAND_Ecc_P16e)          << 2)
  95 #define P16o_s(a)       (TF(a & NAND_Ecc_P16o)          << 3)
  96 #define P1e_s(a)        (TF(a & NAND_Ecc_P1e)           << 4)
  97 #define P1o_s(a)        (TF(a & NAND_Ecc_P1o)           << 5)
  98 #define P2e_s(a)        (TF(a & NAND_Ecc_P2e)           << 6)
  99 #define P2o_s(a)        (TF(a & NAND_Ecc_P2o)           << 7)
 100
 101 #define P4e_s(a)        (TF(a & NAND_Ecc_P4e)           << 0)
 102 #define P4o_s(a)        (TF(a & NAND_Ecc_P4o)           << 1)
 103
 104 #define PREFETCH_CONFIG1_CS_SHIFT       24
 105 #define ECC_CONFIG_CS_SHIFT             1
 106 #define CS_MASK                         0x7
 107 #define ENABLE_PREFETCH                 (0x1 << 7)
 108 #define DMA_MPU_MODE_SHIFT              2
 109 #define ECCSIZE1_SHIFT                  22
 110 #define ECC1RESULTSIZE                  0x1
 111 #define ECCCLEAR                        0x100
 112 #define ECC1                            0x1
 113
 114 /* oob info generated runtime depending on ecc algorithm and layout selected */
 115 static struct nand_ecclayout omap_oobinfo;
 116 /* Define some generic bad / good block scan pattern which are used
 117  * while scanning a device for factory marked good / bad blocks
 118  */
 119 static uint8_t scan_ff_pattern[] = { 0xff };
 120 static struct nand_bbt_descr bb_descrip_flashbased = {
 121         .options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES,
 122         .offs = 0,
 123         .len = 1,
 124         .pattern = scan_ff_pattern,
 125 };
 126
 127
 128 struct omap_nand_info {
 129         struct nand_hw_control          controller;
 130         struct omap_nand_platform_data  *pdata;
 131         struct mtd_info                 mtd;
 132         struct nand_chip                nand;
 133         struct platform_device          *pdev;
 134
 135         int                             gpmc_cs;
 136         unsigned long                   phys_base;
 137         unsigned long                   mem_size;
 138         struct completion               comp;
 139         struct dma_chan                 *dma;
 140         int                             gpmc_irq_fifo;
 141         int                             gpmc_irq_count;
 142         enum {
 143                 OMAP_NAND_IO_READ = 0,  /* read */
 144                 OMAP_NAND_IO_WRITE,     /* write */
 145         } iomode;
 146         u_char                          *buf;
 147         int                                     buf_len;
 148         struct gpmc_nand_regs           reg;
 149
 150 #ifdef CONFIG_MTD_NAND_OMAP_BCH
 151         struct bch_control             *bch;
 152         struct nand_ecclayout           ecclayout;
 153 #endif
 154 };
 155
 156 /**
 157  * omap_prefetch_enable - configures and starts prefetch transfer
 158  * @cs: cs (chip select) number
 159  * @fifo_th: fifo threshold to be used for read/ write
 160  * @dma_mode: dma mode enable (1) or disable (0)
 161  * @u32_count: number of bytes to be transferred
 162  * @is_write: prefetch read(0) or write post(1) mode
 163  */
 164 static int omap_prefetch_enable(int cs, int fifo_th, int dma_mode,
 165         unsigned int u32_count, int is_write, struct omap_nand_info *info)
 166 {
 167         u32 val;
 168
 169         if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX)
 170                 return -1;
 171
 172         if (readl(info->reg.gpmc_prefetch_control))
 173                 return -EBUSY;
 174
 175         /* Set the amount of bytes to be prefetched */
 176         writel(u32_count, info->reg.gpmc_prefetch_config2);
 177
 178         /* Set dma/mpu mode, the prefetch read / post write and
 179          * enable the engine. Set which cs is has requested for.
 180          */
 181         val = ((cs << PREFETCH_CONFIG1_CS_SHIFT) |
 182                 PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH |
 183                 (dma_mode << DMA_MPU_MODE_SHIFT) | (0x1 & is_write));
 184         writel(val, info->reg.gpmc_prefetch_config1);
 185
 186         /*  Start the prefetch engine */
 187         writel(0x1, info->reg.gpmc_prefetch_control);
 188
 189         return 0;
 190 }
 191
 192 /**
 193  * omap_prefetch_reset - disables and stops the prefetch engine
 194  */
 195 static int omap_prefetch_reset(int cs, struct omap_nand_info *info)
 196 {
 197         u32 config1;
 198
 199         /* check if the same module/cs is trying to reset */
 200         config1 = readl(info->reg.gpmc_prefetch_config1);
 201         if (((config1 >> PREFETCH_CONFIG1_CS_SHIFT) & CS_MASK) != cs)
 202                 return -EINVAL;
 203
 204         /* Stop the PFPW engine */
 205         writel(0x0, info->reg.gpmc_prefetch_control);
 206
 207         /* Reset/disable the PFPW engine */
 208         writel(0x0, info->reg.gpmc_prefetch_config1);
 209
 210         return 0;
 211 }
 212
 213 /**
 214  * omap_hwcontrol - hardware specific access to control-lines
 215  * @mtd: MTD device structure
 216  * @cmd: command to device
 217  * @ctrl:
 218  * NAND_NCE: bit 0 -> don't care
 219  * NAND_CLE: bit 1 -> Command Latch
 220  * NAND_ALE: bit 2 -> Address Latch
 221  *
 222  * NOTE: boards may use different bits for these!!
 223  */
 224 static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 225 {
 226         struct omap_nand_info *info = container_of(mtd,
 227                                         struct omap_nand_info, mtd);
 228
 229         if (cmd != NAND_CMD_NONE) {
 230                 if (ctrl & NAND_CLE)
 231                         writeb(cmd, info->reg.gpmc_nand_command);
 232
 233                 else if (ctrl & NAND_ALE)
 234                         writeb(cmd, info->reg.gpmc_nand_address);
 235
 236                 else /* NAND_NCE */
 237                         writeb(cmd, info->reg.gpmc_nand_data);
 238         }
 239 }
 240
 241 /**
 242  * omap_read_buf8 - read data from NAND controller into buffer
 243  * @mtd: MTD device structure
 244  * @buf: buffer to store date
 245  * @len: number of bytes to read
 246  */
 247 static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len)
 248 {
 249         struct nand_chip *nand = mtd->priv;
 250
 251         ioread8_rep(nand->IO_ADDR_R, buf, len);
 252 }
 253
 254 /**
 255  * omap_write_buf8 - write buffer to NAND controller
 256  * @mtd: MTD device structure
 257  * @buf: data buffer
 258  * @len: number of bytes to write
 259  */
 260 static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
 261 {
 262         struct omap_nand_info *info = container_of(mtd,
 263                                                 struct omap_nand_info, mtd);
 264         u_char *p = (u_char *)buf;
 265         u32     status = 0;
 266
 267         while (len--) {
 268                 iowrite8(*p++, info->nand.IO_ADDR_W);
 269                 /* wait until buffer is available for write */
 270                 do {
 271                         status = readl(info->reg.gpmc_status) &
 272                                         GPMC_STATUS_BUFF_EMPTY;
 273                 } while (!status);
 274         }
 275 }
 276
 277 /**
 278  * omap_read_buf16 - read data from NAND controller into buffer
 279  * @mtd: MTD device structure
 280  * @buf: buffer to store date
 281  * @len: number of bytes to read
 282  */
 283 static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
 284 {
 285         struct nand_chip *nand = mtd->priv;
 286
 287         ioread16_rep(nand->IO_ADDR_R, buf, len / 2);
 288 }
 289
 290 /**
 291  * omap_write_buf16 - write buffer to NAND controller
 292  * @mtd: MTD device structure
 293  * @buf: data buffer
 294  * @len: number of bytes to write
 295  */
 296 static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
 297 {
 298         struct omap_nand_info *info = container_of(mtd,
 299                                                 struct omap_nand_info, mtd);
 300         u16 *p = (u16 *) buf;
 301         u32     status = 0;
 302         /* FIXME try bursts of writesw() or DMA ... */
 303         len >>= 1;
 304
 305         while (len--) {
 306                 iowrite16(*p++, info->nand.IO_ADDR_W);
 307                 /* wait until buffer is available for write */
 308                 do {
 309                         status = readl(info->reg.gpmc_status) &
 310                                         GPMC_STATUS_BUFF_EMPTY;
 311                 } while (!status);
 312         }
 313 }
 314
 315 /**
 316  * omap_read_buf_pref - read data from NAND controller into buffer
 317  * @mtd: MTD device structure
 318  * @buf: buffer to store date
 319  * @len: number of bytes to read
 320  */
 321 static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
 322 {
 323         struct omap_nand_info *info = container_of(mtd,
 324                                                 struct omap_nand_info, mtd);
 325         uint32_t r_count = 0;
 326         int ret = 0;
 327         u32 *p = (u32 *)buf;
 328
 329         /* take care of subpage reads */
 330         if (len % 4) {
 331                 if (info->nand.options & NAND_BUSWIDTH_16)
 332                         omap_read_buf16(mtd, buf, len % 4);
 333                 else
 334                         omap_read_buf8(mtd, buf, len % 4);
 335                 p = (u32 *) (buf + len % 4);
 336                 len -= len % 4;
 337         }
 338
 339         /* configure and start prefetch transfer */
 340         ret = omap_prefetch_enable(info->gpmc_cs,
 341                         PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0, info);
 342         if (ret) {
 343                 /* PFPW engine is busy, use cpu copy method */
 344                 if (info->nand.options & NAND_BUSWIDTH_16)
 345                         omap_read_buf16(mtd, (u_char *)p, len);
 346                 else
 347                         omap_read_buf8(mtd, (u_char *)p, len);
 348         } else {
 349                 do {
 350                         r_count = readl(info->reg.gpmc_prefetch_status);
 351                         r_count = GPMC_PREFETCH_STATUS_FIFO_CNT(r_count);
 352                         r_count = r_count >> 2;
 353                         ioread32_rep(info->nand.IO_ADDR_R, p, r_count);
 354                         p += r_count;
 355                         len -= r_count << 2;
 356                 } while (len);
 357                 /* disable and stop the PFPW engine */
 358                 omap_prefetch_reset(info->gpmc_cs, info);
 359         }
 360 }
 361
 362 /**
 363  * omap_write_buf_pref - write buffer to NAND controller
 364  * @mtd: MTD device structure
 365  * @buf: data buffer
 366  * @len: number of bytes to write
 367  */
 368 static void omap_write_buf_pref(struct mtd_info *mtd,
 369                                         const u_char *buf, int len)
 370 {
 371         struct omap_nand_info *info = container_of(mtd,
 372                                                 struct omap_nand_info, mtd);
 373         uint32_t w_count = 0;
 374         int i = 0, ret = 0;
 375         u16 *p = (u16 *)buf;
 376         unsigned long tim, limit;
 377         u32 val;
 378
 379         /* take care of subpage writes */
 380         if (len % 2 != 0) {
 381                 writeb(*buf, info->nand.IO_ADDR_W);
 382                 p = (u16 *)(buf + 1);
 383                 len--;
 384         }
 385
 386         /*  configure and start prefetch transfer */
 387         ret = omap_prefetch_enable(info->gpmc_cs,
 388                         PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1, info);
 389         if (ret) {
 390                 /* PFPW engine is busy, use cpu copy method */
 391                 if (info->nand.options & NAND_BUSWIDTH_16)
 392                         omap_write_buf16(mtd, (u_char *)p, len);
 393                 else
 394                         omap_write_buf8(mtd, (u_char *)p, len);
 395         } else {
 396                 while (len) {
 397                         w_count = readl(info->reg.gpmc_prefetch_status);
 398                         w_count = GPMC_PREFETCH_STATUS_FIFO_CNT(w_count);
 399                         w_count = w_count >> 1;
 400                         for (i = 0; (i < w_count) && len; i++, len -= 2)
 401                                 iowrite16(*p++, info->nand.IO_ADDR_W);
 402                 }
 403                 /* wait for data to flushed-out before reset the prefetch */
 404                 tim = 0;
 405                 limit = (loops_per_jiffy *
 406                                         msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 407                 do {
 408                         cpu_relax();
 409                         val = readl(info->reg.gpmc_prefetch_status);
 410                         val = GPMC_PREFETCH_STATUS_COUNT(val);
 411                 } while (val && (tim++ < limit));
 412
 413                 /* disable and stop the PFPW engine */
 414                 omap_prefetch_reset(info->gpmc_cs, info);
 415         }
 416 }
 417
 418 /*
 419  * omap_nand_dma_callback: callback on the completion of dma transfer
 420  * @data: pointer to completion data structure
 421  */
 422 static void omap_nand_dma_callback(void *data)
 423 {
 424         complete((struct completion *) data);
 425 }
 426
 427 /*
 428  * omap_nand_dma_transfer: configer and start dma transfer
 429  * @mtd: MTD device structure
 430  * @addr: virtual address in RAM of source/destination
 431  * @len: number of data bytes to be transferred
 432  * @is_write: flag for read/write operation
 433  */
 434 static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
 435                                         unsigned int len, int is_write)
 436 {
 437         struct omap_nand_info *info = container_of(mtd,
 438                                         struct omap_nand_info, mtd);
 439         struct dma_async_tx_descriptor *tx;
 440         enum dma_data_direction dir = is_write ? DMA_TO_DEVICE :
 441                                                         DMA_FROM_DEVICE;
 442         struct scatterlist sg;
 443         unsigned long tim, limit;
 444         unsigned n;
 445         int ret;
 446         u32 val;
 447
 448         if (addr >= high_memory) {
 449                 struct page *p1;
 450
 451                 if (((size_t)addr & PAGE_MASK) !=
 452                         ((size_t)(addr + len - 1) & PAGE_MASK))
 453                         goto out_copy;
 454                 p1 = vmalloc_to_page(addr);
 455                 if (!p1)
 456                         goto out_copy;
 457                 addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK);
 458         }
 459
 460         sg_init_one(&sg, addr, len);
 461         n = dma_map_sg(info->dma->device->dev, &sg, 1, dir);
 462         if (n == 0) {
 463                 dev_err(&info->pdev->dev,
 464                         "Couldn't DMA map a %d byte buffer\n", len);
 465                 goto out_copy;
 466         }
 467
 468         tx = dmaengine_prep_slave_sg(info->dma, &sg, n,
 469                 is_write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
 470                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 471         if (!tx)
 472                 goto out_copy_unmap;
 473
 474         tx->callback = omap_nand_dma_callback;
 475         tx->callback_param = &info->comp;
 476         dmaengine_submit(tx);
 477
 478         /*  configure and start prefetch transfer */
 479         ret = omap_prefetch_enable(info->gpmc_cs,
 480                 PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write, info);
 481         if (ret)
 482                 /* PFPW engine is busy, use cpu copy method */
 483                 goto out_copy_unmap;
 484
 485         init_completion(&info->comp);
 486         dma_async_issue_pending(info->dma);
 487
 488         /* setup and start DMA using dma_addr */
 489         wait_for_completion(&info->comp);
 490         tim = 0;
 491         limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 492
 493         do {
 494                 cpu_relax();
 495                 val = readl(info->reg.gpmc_prefetch_status);
 496                 val = GPMC_PREFETCH_STATUS_COUNT(val);
 497         } while (val && (tim++ < limit));
 498
 499         /* disable and stop the PFPW engine */
 500         omap_prefetch_reset(info->gpmc_cs, info);
 501
 502         dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
 503         return 0;
 504
 505 out_copy_unmap:
 506         dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
 507 out_copy:
 508         if (info->nand.options & NAND_BUSWIDTH_16)
 509                 is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len)
 510                         : omap_write_buf16(mtd, (u_char *) addr, len);
 511         else
 512                 is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len)
 513                         : omap_write_buf8(mtd, (u_char *) addr, len);
 514         return 0;
 515 }
 516
 517 /**
 518  * omap_read_buf_dma_pref - read data from NAND controller into buffer
 519  * @mtd: MTD device structure
 520  * @buf: buffer to store date
 521  * @len: number of bytes to read
 522  */
 523 static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len)
 524 {
 525         if (len <= mtd->oobsize)
 526                 omap_read_buf_pref(mtd, buf, len);
 527         else
 528                 /* start transfer in DMA mode */
 529                 omap_nand_dma_transfer(mtd, buf, len, 0x0);
 530 }
 531
 532 /**
 533  * omap_write_buf_dma_pref - write buffer to NAND controller
 534  * @mtd: MTD device structure
 535  * @buf: data buffer
 536  * @len: number of bytes to write
 537  */
 538 static void omap_write_buf_dma_pref(struct mtd_info *mtd,
 539                                         const u_char *buf, int len)
 540 {
 541         if (len <= mtd->oobsize)
 542                 omap_write_buf_pref(mtd, buf, len);
 543         else
 544                 /* start transfer in DMA mode */
 545                 omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1);
 546 }
 547
 548 /*
 549  * omap_nand_irq - GMPC irq handler
 550  * @this_irq: gpmc irq number
 551  * @dev: omap_nand_info structure pointer is passed here
 552  */
 553 static irqreturn_t omap_nand_irq(int this_irq, void *dev)
 554 {
 555         struct omap_nand_info *info = (struct omap_nand_info *) dev;
 556         u32 bytes;
 557
 558         bytes = readl(info->reg.gpmc_prefetch_status);
 559         bytes = GPMC_PREFETCH_STATUS_FIFO_CNT(bytes);
 560         bytes = bytes  & 0xFFFC; /* io in multiple of 4 bytes */
 561         if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
 562                 if (this_irq == info->gpmc_irq_count)
 563                         goto done;
 564
 565                 if (info->buf_len && (info->buf_len < bytes))
 566                         bytes = info->buf_len;
 567                 else if (!info->buf_len)
 568                         bytes = 0;
 569                 iowrite32_rep(info->nand.IO_ADDR_W,
 570                                                 (u32 *)info->buf, bytes >> 2);
 571                 info->buf = info->buf + bytes;
 572                 info->buf_len -= bytes;
 573
 574         } else {
 575                 ioread32_rep(info->nand.IO_ADDR_R,
 576                                                 (u32 *)info->buf, bytes >> 2);
 577                 info->buf = info->buf + bytes;
 578
 579                 if (this_irq == info->gpmc_irq_count)
 580                         goto done;
 581         }
 582
 583         return IRQ_HANDLED;
 584
 585 done:
 586         complete(&info->comp);
 587
 588         disable_irq_nosync(info->gpmc_irq_fifo);
 589         disable_irq_nosync(info->gpmc_irq_count);
 590
 591         return IRQ_HANDLED;
 592 }
 593
 594 /*
 595  * omap_read_buf_irq_pref - read data from NAND controller into buffer
 596  * @mtd: MTD device structure
 597  * @buf: buffer to store date
 598  * @len: number of bytes to read
 599  */
 600 static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len)
 601 {
 602         struct omap_nand_info *info = container_of(mtd,
 603                                                 struct omap_nand_info, mtd);
 604         int ret = 0;
 605
 606         if (len <= mtd->oobsize) {
 607                 omap_read_buf_pref(mtd, buf, len);
 608                 return;
 609         }
 610
 611         info->iomode = OMAP_NAND_IO_READ;
 612         info->buf = buf;
 613         init_completion(&info->comp);
 614
 615         /*  configure and start prefetch transfer */
 616         ret = omap_prefetch_enable(info->gpmc_cs,
 617                         PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0, info);
 618         if (ret)
 619                 /* PFPW engine is busy, use cpu copy method */
 620                 goto out_copy;
 621
 622         info->buf_len = len;
 623
 624         enable_irq(info->gpmc_irq_count);
 625         enable_irq(info->gpmc_irq_fifo);
 626
 627         /* waiting for read to complete */
 628         wait_for_completion(&info->comp);
 629
 630         /* disable and stop the PFPW engine */
 631         omap_prefetch_reset(info->gpmc_cs, info);
 632         return;
 633
 634 out_copy:
 635         if (info->nand.options & NAND_BUSWIDTH_16)
 636                 omap_read_buf16(mtd, buf, len);
 637         else
 638                 omap_read_buf8(mtd, buf, len);
 639 }
 640
 641 /*
 642  * omap_write_buf_irq_pref - write buffer to NAND controller
 643  * @mtd: MTD device structure
 644  * @buf: data buffer
 645  * @len: number of bytes to write
 646  */
 647 static void omap_write_buf_irq_pref(struct mtd_info *mtd,
 648                                         const u_char *buf, int len)
 649 {
 650         struct omap_nand_info *info = container_of(mtd,
 651                                                 struct omap_nand_info, mtd);
 652         int ret = 0;
 653         unsigned long tim, limit;
 654         u32 val;
 655
 656         if (len <= mtd->oobsize) {
 657                 omap_write_buf_pref(mtd, buf, len);
 658                 return;
 659         }
 660
 661         info->iomode = OMAP_NAND_IO_WRITE;
 662         info->buf = (u_char *) buf;
 663         init_completion(&info->comp);
 664
 665         /* configure and start prefetch transfer : size=24 */
 666         ret = omap_prefetch_enable(info->gpmc_cs,
 667                 (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1, info);
 668         if (ret)
 669                 /* PFPW engine is busy, use cpu copy method */
 670                 goto out_copy;
 671
 672         info->buf_len = len;
 673
 674         enable_irq(info->gpmc_irq_count);
 675         enable_irq(info->gpmc_irq_fifo);
 676
 677         /* waiting for write to complete */
 678         wait_for_completion(&info->comp);
 679
 680         /* wait for data to flushed-out before reset the prefetch */
 681         tim = 0;
 682         limit = (loops_per_jiffy *  msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 683         do {
 684                 val = readl(info->reg.gpmc_prefetch_status);
 685                 val = GPMC_PREFETCH_STATUS_COUNT(val);
 686                 cpu_relax();
 687         } while (val && (tim++ < limit));
 688
 689         /* disable and stop the PFPW engine */
 690         omap_prefetch_reset(info->gpmc_cs, info);
 691         return;
 692
 693 out_copy:
 694         if (info->nand.options & NAND_BUSWIDTH_16)
 695                 omap_write_buf16(mtd, buf, len);
 696         else
 697                 omap_write_buf8(mtd, buf, len);
 698 }
 699
 700 /**
 701  * omap_verify_buf - Verify chip data against buffer
 702  * @mtd: MTD device structure
 703  * @buf: buffer containing the data to compare
 704  * @len: number of bytes to compare
 705  */
 706 static int omap_verify_buf(struct mtd_info *mtd, const u_char * buf, int len)
 707 {
 708         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 709                                                         mtd);
 710         u16 *p = (u16 *) buf;
 711
 712         len >>= 1;
 713         while (len--) {
 714                 if (*p++ != cpu_to_le16(readw(info->nand.IO_ADDR_R)))
 715                         return -EFAULT;
 716         }
 717
 718         return 0;
 719 }
 720
 721 /**
 722  * gen_true_ecc - This function will generate true ECC value
 723  * @ecc_buf: buffer to store ecc code
 724  *
 725  * This generated true ECC value can be used when correcting
 726  * data read from NAND flash memory core
 727  */
 728 static void gen_true_ecc(u8 *ecc_buf)
 729 {
 730         u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) |
 731                 ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
 732
 733         ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) |
 734                         P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
 735         ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) |
 736                         P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
 737         ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) |
 738                         P1e(tmp) | P2048o(tmp) | P2048e(tmp));
 739 }
 740
 741 /**
 742  * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
 743  * @ecc_data1:  ecc code from nand spare area
 744  * @ecc_data2:  ecc code from hardware register obtained from hardware ecc
 745  * @page_data:  page data
 746  *
 747  * This function compares two ECC's and indicates if there is an error.
 748  * If the error can be corrected it will be corrected to the buffer.
 749  * If there is no error, %0 is returned. If there is an error but it
 750  * was corrected, %1 is returned. Otherwise, %-1 is returned.
 751  */
 752 static int omap_compare_ecc(u8 *ecc_data1,      /* read from NAND memory */
 753                             u8 *ecc_data2,      /* read from register */
 754                             u8 *page_data)
 755 {
 756         uint    i;
 757         u8      tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
 758         u8      comp0_bit[8], comp1_bit[8], comp2_bit[8];
 759         u8      ecc_bit[24];
 760         u8      ecc_sum = 0;
 761         u8      find_bit = 0;
 762         uint    find_byte = 0;
 763         int     isEccFF;
 764
 765         isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
 766
 767         gen_true_ecc(ecc_data1);
 768         gen_true_ecc(ecc_data2);
 769
 770         for (i = 0; i <= 2; i++) {
 771                 *(ecc_data1 + i) = ~(*(ecc_data1 + i));
 772                 *(ecc_data2 + i) = ~(*(ecc_data2 + i));
 773         }
 774
 775         for (i = 0; i < 8; i++) {
 776                 tmp0_bit[i]     = *ecc_data1 % 2;
 777                 *ecc_data1      = *ecc_data1 / 2;
 778         }
 779
 780         for (i = 0; i < 8; i++) {
 781                 tmp1_bit[i]      = *(ecc_data1 + 1) % 2;
 782                 *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
 783         }
 784
 785         for (i = 0; i < 8; i++) {
 786                 tmp2_bit[i]      = *(ecc_data1 + 2) % 2;
 787                 *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
 788         }
 789
 790         for (i = 0; i < 8; i++) {
 791                 comp0_bit[i]     = *ecc_data2 % 2;
 792                 *ecc_data2       = *ecc_data2 / 2;
 793         }
 794
 795         for (i = 0; i < 8; i++) {
 796                 comp1_bit[i]     = *(ecc_data2 + 1) % 2;
 797                 *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
 798         }
 799
 800         for (i = 0; i < 8; i++) {
 801                 comp2_bit[i]     = *(ecc_data2 + 2) % 2;
 802                 *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
 803         }
 804
 805         for (i = 0; i < 6; i++)
 806                 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
 807
 808         for (i = 0; i < 8; i++)
 809                 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
 810
 811         for (i = 0; i < 8; i++)
 812                 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
 813
 814         ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
 815         ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
 816
 817         for (i = 0; i < 24; i++)
 818                 ecc_sum += ecc_bit[i];
 819
 820         switch (ecc_sum) {
 821         case 0:
 822                 /* Not reached because this function is not called if
 823                  *  ECC values are equal
 824                  */
 825                 return 0;
 826
 827         case 1:
 828                 /* Uncorrectable error */
 829                 pr_debug("ECC UNCORRECTED_ERROR 1\n");
 830                 return -1;
 831
 832         case 11:
 833                 /* UN-Correctable error */
 834                 pr_debug("ECC UNCORRECTED_ERROR B\n");
 835                 return -1;
 836
 837         case 12:
 838                 /* Correctable error */
 839                 find_byte = (ecc_bit[23] << 8) +
 840                             (ecc_bit[21] << 7) +
 841                             (ecc_bit[19] << 6) +
 842                             (ecc_bit[17] << 5) +
 843                             (ecc_bit[15] << 4) +
 844                             (ecc_bit[13] << 3) +
 845                             (ecc_bit[11] << 2) +
 846                             (ecc_bit[9]  << 1) +
 847                             ecc_bit[7];
 848
 849                 find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
 850
 851                 pr_debug("Correcting single bit ECC error at offset: "
 852                                 "%d, bit: %d\n", find_byte, find_bit);
 853
 854                 page_data[find_byte] ^= (1 << find_bit);
 855
 856                 return 1;
 857         default:
 858                 if (isEccFF) {
 859                         if (ecc_data2[0] == 0 &&
 860                             ecc_data2[1] == 0 &&
 861                             ecc_data2[2] == 0)
 862                                 return 0;
 863                 }
 864                 pr_debug("UNCORRECTED_ERROR default\n");
 865                 return -1;
 866         }
 867 }
 868
 869 /**
 870  * omap_correct_data - Compares the ECC read with HW generated ECC
 871  * @mtd: MTD device structure
 872  * @dat: page data
 873  * @read_ecc: ecc read from nand flash
 874  * @calc_ecc: ecc read from HW ECC registers
 875  *
 876  * Compares the ecc read from nand spare area with ECC registers values
 877  * and if ECC's mismatched, it will call 'omap_compare_ecc' for error
 878  * detection and correction. If there are no errors, %0 is returned. If
 879  * there were errors and all of the errors were corrected, the number of
 880  * corrected errors is returned. If uncorrectable errors exist, %-1 is
 881  * returned.
 882  */
 883 static int omap_correct_data(struct mtd_info *mtd, u_char *dat,
 884                                 u_char *read_ecc, u_char *calc_ecc)
 885 {
 886         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 887                                                         mtd);
 888         int blockCnt = 0, i = 0, ret = 0;
 889         int stat = 0;
 890
 891         /* Ex NAND_ECC_HW12_2048 */
 892         if ((info->nand.ecc.mode == NAND_ECC_HW) &&
 893                         (info->nand.ecc.size  == 2048))
 894                 blockCnt = 4;
 895         else
 896                 blockCnt = 1;
 897
 898         for (i = 0; i < blockCnt; i++) {
 899                 if (memcmp(read_ecc, calc_ecc, 3) != 0) {
 900                         ret = omap_compare_ecc(read_ecc, calc_ecc, dat);
 901                         if (ret < 0)
 902                                 return ret;
 903                         /* keep track of the number of corrected errors */
 904                         stat += ret;
 905                 }
 906                 read_ecc += 3;
 907                 calc_ecc += 3;
 908                 dat      += 512;
 909         }
 910         return stat;
 911 }
 912
 913 /**
 914  * omap_calcuate_ecc - Generate non-inverted ECC bytes.
 915  * @mtd: MTD device structure
 916  * @dat: The pointer to data on which ecc is computed
 917  * @ecc_code: The ecc_code buffer
 918  *
 919  * Using noninverted ECC can be considered ugly since writing a blank
 920  * page ie. padding will clear the ECC bytes. This is no problem as long
 921  * nobody is trying to write data on the seemingly unused page. Reading
 922  * an erased page will produce an ECC mismatch between generated and read
 923  * ECC bytes that has to be dealt with separately.
 924  */
 925 static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 926                                 u_char *ecc_code)
 927 {
 928         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 929                                                         mtd);
 930         u32 val;
 931
 932         val = readl(info->reg.gpmc_ecc_config);
 933         if (((val >> ECC_CONFIG_CS_SHIFT)  & ~CS_MASK) != info->gpmc_cs)
 934                 return -EINVAL;
 935
 936         /* read ecc result */
 937         val = readl(info->reg.gpmc_ecc1_result);
 938         *ecc_code++ = val;          /* P128e, ..., P1e */
 939         *ecc_code++ = val >> 16;    /* P128o, ..., P1o */
 940         /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
 941         *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
 942
 943         return 0;
 944 }
 945
 946 /**
 947  * omap_enable_hwecc - This function enables the hardware ecc functionality
 948  * @mtd: MTD device structure
 949  * @mode: Read/Write mode
 950  */
 951 static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
 952 {
 953         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 954                                                         mtd);
 955         struct nand_chip *chip = mtd->priv;
 956         unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
 957         u32 val;
 958
 959         /* clear ecc and enable bits */
 960         val = ECCCLEAR | ECC1;
 961         writel(val, info->reg.gpmc_ecc_control);
 962
 963         /* program ecc and result sizes */
 964         val = ((((info->nand.ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) |
 965                          ECC1RESULTSIZE);
 966         writel(val, info->reg.gpmc_ecc_size_config);
 967
 968         switch (mode) {
 969         case NAND_ECC_READ:
 970         case NAND_ECC_WRITE:
 971                 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
 972                 break;
 973         case NAND_ECC_READSYN:
 974                 writel(ECCCLEAR, info->reg.gpmc_ecc_control);
 975                 break;
 976         default:
 977                 dev_info(&info->pdev->dev,
 978                         "error: unrecognized Mode[%d]!\n", mode);
 979                 break;
 980         }
 981
 982         /* (ECC 16 or 8 bit col) | ( CS  )  | ECC Enable */
 983         val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
 984         writel(val, info->reg.gpmc_ecc_config);
 985 }
 986
 987 /**
 988  * omap_wait - wait until the command is done
 989  * @mtd: MTD device structure
 990  * @chip: NAND Chip structure
 991  *
 992  * Wait function is called during Program and erase operations and
 993  * the way it is called from MTD layer, we should wait till the NAND
 994  * chip is ready after the programming/erase operation has completed.
 995  *
 996  * Erase can take up to 400ms and program up to 20ms according to
 997  * general NAND and SmartMedia specs
 998  */
 999 static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
1000 {
1001         struct nand_chip *this = mtd->priv;
1002         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1003                                                         mtd);
1004         unsigned long timeo = jiffies;
1005         int status, state = this->state;
1006
1007         if (state == FL_ERASING)
1008                 timeo += (HZ * 400) / 1000;
1009         else
1010                 timeo += (HZ * 20) / 1000;
1011
1012         writeb(NAND_CMD_STATUS & 0xFF, info->reg.gpmc_nand_command);
1013         while (time_before(jiffies, timeo)) {
1014                 status = readb(info->reg.gpmc_nand_data);
1015                 if (status & NAND_STATUS_READY)
1016                         break;
1017                 cond_resched();
1018         }
1019
1020         status = gpmc_nand_read(info->gpmc_cs, GPMC_NAND_DATA);
1021         return status;
1022 }
1023
1024 /**
1025  * omap_dev_ready - calls the platform specific dev_ready function
1026  * @mtd: MTD device structure
1027  */
1028 static int omap_dev_ready(struct mtd_info *mtd)
1029 {
1030         unsigned int val = 0;
1031         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1032                                                         mtd);
1033
1034         val = readl(info->reg.gpmc_status);
1035
1036         if ((val & 0x100) == 0x100) {
1037                 return 1;
1038         } else {
1039                 return 0;
1040         }
1041 }
1042
1043 #ifdef CONFIG_MTD_NAND_OMAP_BCH
1044
1045 /**
1046  * omap3_enable_hwecc_bch - Program OMAP3 GPMC to perform BCH ECC correction
1047  * @mtd: MTD device structure
1048  * @mode: Read/Write mode
1049  */
1050 static void omap3_enable_hwecc_bch(struct mtd_info *mtd, int mode)
1051 {
1052         int nerrors;
1053         unsigned int dev_width;
1054         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1055                                                    mtd);
1056         struct nand_chip *chip = mtd->priv;
1057
1058         nerrors = (info->nand.ecc.bytes == 13) ? 8 : 4;
1059         dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
1060         /*
1061          * Program GPMC to perform correction on one 512-byte sector at a time.
1062          * Using 4 sectors at a time (i.e. ecc.size = 2048) is also possible and
1063          * gives a slight (5%) performance gain (but requires additional code).
1064          */
1065         (void)gpmc_enable_hwecc_bch(info->gpmc_cs, mode, dev_width, 1, nerrors);
1066 }
1067
1068 /**
1069  * omap3_calculate_ecc_bch4 - Generate 7 bytes of ECC bytes
1070  * @mtd: MTD device structure
1071  * @dat: The pointer to data on which ecc is computed
1072  * @ecc_code: The ecc_code buffer
1073  */
1074 static int omap3_calculate_ecc_bch4(struct mtd_info *mtd, const u_char *dat,
1075                                     u_char *ecc_code)
1076 {
1077         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1078                                                    mtd);
1079         return gpmc_calculate_ecc_bch4(info->gpmc_cs, dat, ecc_code);
1080 }
1081
1082 /**
1083  * omap3_calculate_ecc_bch8 - Generate 13 bytes of ECC bytes
1084  * @mtd: MTD device structure
1085  * @dat: The pointer to data on which ecc is computed
1086  * @ecc_code: The ecc_code buffer
1087  */
1088 static int omap3_calculate_ecc_bch8(struct mtd_info *mtd, const u_char *dat,
1089                                     u_char *ecc_code)
1090 {
1091         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1092                                                    mtd);
1093         return gpmc_calculate_ecc_bch8(info->gpmc_cs, dat, ecc_code);
1094 }
1095
1096 /**
1097  * omap3_correct_data_bch - Decode received data and correct errors
1098  * @mtd: MTD device structure
1099  * @data: page data
1100  * @read_ecc: ecc read from nand flash
1101  * @calc_ecc: ecc read from HW ECC registers
1102  */
1103 static int omap3_correct_data_bch(struct mtd_info *mtd, u_char *data,
1104                                   u_char *read_ecc, u_char *calc_ecc)
1105 {
1106         int i, count;
1107         /* cannot correct more than 8 errors */
1108         unsigned int errloc[8];
1109         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1110                                                    mtd);
1111
1112         count = decode_bch(info->bch, NULL, 512, read_ecc, calc_ecc, NULL,
1113                            errloc);
1114         if (count > 0) {
1115                 /* correct errors */
1116                 for (i = 0; i < count; i++) {
1117                         /* correct data only, not ecc bytes */
1118                         if (errloc[i] < 8*512)
1119                                 data[errloc[i]/8] ^= 1 << (errloc[i] & 7);
1120                         pr_debug("corrected bitflip %u\n", errloc[i]);
1121                 }
1122         } else if (count < 0) {
1123                 pr_err("ecc unrecoverable error\n");
1124         }
1125         return count;
1126 }
1127
1128 /**
1129  * omap3_free_bch - Release BCH ecc resources
1130  * @mtd: MTD device structure
1131  */
1132 static void omap3_free_bch(struct mtd_info *mtd)
1133 {
1134         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1135                                                    mtd);
1136         if (info->bch) {
1137                 free_bch(info->bch);
1138                 info->bch = NULL;
1139         }
1140 }
1141
1142 /**
1143  * omap3_init_bch - Initialize BCH ECC
1144  * @mtd: MTD device structure
1145  * @ecc_opt: OMAP ECC mode (OMAP_ECC_BCH4_CODE_HW or OMAP_ECC_BCH8_CODE_HW)
1146  */
1147 static int omap3_init_bch(struct mtd_info *mtd, int ecc_opt)
1148 {
1149         int ret, max_errors;
1150         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1151                                                    mtd);
1152 #ifdef CONFIG_MTD_NAND_OMAP_BCH8
1153         const int hw_errors = 8;
1154 #else
1155         const int hw_errors = 4;
1156 #endif
1157         info->bch = NULL;
1158
1159         max_errors = (ecc_opt == OMAP_ECC_BCH8_CODE_HW) ? 8 : 4;
1160         if (max_errors != hw_errors) {
1161                 pr_err("cannot configure %d-bit BCH ecc, only %d-bit supported",
1162                        max_errors, hw_errors);
1163                 goto fail;
1164         }
1165
1166         /* initialize GPMC BCH engine */
1167         ret = gpmc_init_hwecc_bch(info->gpmc_cs, 1, max_errors);
1168         if (ret)
1169                 goto fail;
1170
1171         /* software bch library is only used to detect and locate errors */
1172         info->bch = init_bch(13, max_errors, 0x201b /* hw polynomial */);
1173         if (!info->bch)
1174                 goto fail;
1175
1176         info->nand.ecc.size    = 512;
1177         info->nand.ecc.hwctl   = omap3_enable_hwecc_bch;
1178         info->nand.ecc.correct = omap3_correct_data_bch;
1179         info->nand.ecc.mode    = NAND_ECC_HW;
1180
1181         /*
1182          * The number of corrected errors in an ecc block that will trigger
1183          * block scrubbing defaults to the ecc strength (4 or 8).
1184          * Set mtd->bitflip_threshold here to define a custom threshold.
1185          */
1186
1187         if (max_errors == 8) {
1188                 info->nand.ecc.strength  = 8;
1189                 info->nand.ecc.bytes     = 13;
1190                 info->nand.ecc.calculate = omap3_calculate_ecc_bch8;
1191         } else {
1192                 info->nand.ecc.strength  = 4;
1193                 info->nand.ecc.bytes     = 7;
1194                 info->nand.ecc.calculate = omap3_calculate_ecc_bch4;
1195         }
1196
1197         pr_info("enabling NAND BCH ecc with %d-bit correction\n", max_errors);
1198         return 0;
1199 fail:
1200         omap3_free_bch(mtd);
1201         return -1;
1202 }
1203
1204 /**
1205  * omap3_init_bch_tail - Build an oob layout for BCH ECC correction.
1206  * @mtd: MTD device structure
1207  */
1208 static int omap3_init_bch_tail(struct mtd_info *mtd)
1209 {
1210         int i, steps;
1211         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1212                                                    mtd);
1213         struct nand_ecclayout *layout = &info->ecclayout;
1214
1215         /* build oob layout */
1216         steps = mtd->writesize/info->nand.ecc.size;
1217         layout->eccbytes = steps*info->nand.ecc.bytes;
1218
1219         /* do not bother creating special oob layouts for small page devices */
1220         if (mtd->oobsize < 64) {
1221                 pr_err("BCH ecc is not supported on small page devices\n");
1222                 goto fail;
1223         }
1224
1225         /* reserve 2 bytes for bad block marker */
1226         if (layout->eccbytes+2 > mtd->oobsize) {
1227                 pr_err("no oob layout available for oobsize %d eccbytes %u\n",
1228                        mtd->oobsize, layout->eccbytes);
1229                 goto fail;
1230         }
1231
1232         /* put ecc bytes at oob tail */
1233         for (i = 0; i < layout->eccbytes; i++)
1234                 layout->eccpos[i] = mtd->oobsize-layout->eccbytes+i;
1235
1236         layout->oobfree[0].offset = 2;
1237         layout->oobfree[0].length = mtd->oobsize-2-layout->eccbytes;
1238         info->nand.ecc.layout = layout;
1239
1240         if (!(info->nand.options & NAND_BUSWIDTH_16))
1241                 info->nand.badblock_pattern = &bb_descrip_flashbased;
1242         return 0;
1243 fail:
1244         omap3_free_bch(mtd);
1245         return -1;
1246 }
1247
1248 #else
1249 static int omap3_init_bch(struct mtd_info *mtd, int ecc_opt)
1250 {
1251         pr_err("CONFIG_MTD_NAND_OMAP_BCH is not enabled\n");
1252         return -1;
1253 }
1254 static int omap3_init_bch_tail(struct mtd_info *mtd)
1255 {
1256         return -1;
1257 }
1258 static void omap3_free_bch(struct mtd_info *mtd)
1259 {
1260 }
1261 #endif /* CONFIG_MTD_NAND_OMAP_BCH */
1262
1263 static int __devinit omap_nand_probe(struct platform_device *pdev)
1264 {
1265         struct omap_nand_info           *info;
1266         struct omap_nand_platform_data  *pdata;
1267         int                             err;
1268         int                             i, offset;
1269         dma_cap_mask_t mask;
1270         unsigned sig;
1271         struct resource                 *res;
1272
1273         pdata = pdev->dev.platform_data;
1274         if (pdata == NULL) {
1275                 dev_err(&pdev->dev, "platform data missing\n");
1276                 return -ENODEV;
1277         }
1278
1279         info = kzalloc(sizeof(struct omap_nand_info), GFP_KERNEL);
1280         if (!info)
1281                 return -ENOMEM;
1282
1283         platform_set_drvdata(pdev, info);
1284
1285         spin_lock_init(&info->controller.lock);
1286         init_waitqueue_head(&info->controller.wq);
1287
1288         info->pdev = pdev;
1289
1290         info->gpmc_cs           = pdata->cs;
1291         info->reg               = pdata->reg;
1292
1293         info->mtd.priv          = &info->nand;
1294         info->mtd.name          = dev_name(&pdev->dev);
1295         info->mtd.owner         = THIS_MODULE;
1296
1297         info->nand.options      = pdata->devsize;
1298         info->nand.options      |= NAND_SKIP_BBTSCAN;
1299
1300         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1301         if (res == NULL) {
1302                 err = -EINVAL;
1303                 dev_err(&pdev->dev, "error getting memory resource\n");
1304                 goto out_free_info;
1305         }
1306
1307         info->phys_base = res->start;
1308         info->mem_size = resource_size(res);
1309
1310         if (!request_mem_region(info->phys_base, info->mem_size,
1311                                 pdev->dev.driver->name)) {
1312                 err = -EBUSY;
1313                 goto out_free_info;
1314         }
1315
1316         info->nand.IO_ADDR_R = ioremap(info->phys_base, info->mem_size);
1317         if (!info->nand.IO_ADDR_R) {
1318                 err = -ENOMEM;
1319                 goto out_release_mem_region;
1320         }
1321
1322         info->nand.controller = &info->controller;
1323
1324         info->nand.IO_ADDR_W = info->nand.IO_ADDR_R;
1325         info->nand.cmd_ctrl  = omap_hwcontrol;
1326
1327         /*
1328          * If RDY/BSY line is connected to OMAP then use the omap ready
1329          * funcrtion and the generic nand_wait function which reads the status
1330          * register after monitoring the RDY/BSY line.Otherwise use a standard
1331          * chip delay which is slightly more than tR (AC Timing) of the NAND
1332          * device and read status register until you get a failure or success
1333          */
1334         if (pdata->dev_ready) {
1335                 info->nand.dev_ready = omap_dev_ready;
1336                 info->nand.chip_delay = 0;
1337         } else {
1338                 info->nand.waitfunc = omap_wait;
1339                 info->nand.chip_delay = 50;
1340         }
1341
1342         switch (pdata->xfer_type) {
1343         case NAND_OMAP_PREFETCH_POLLED:
1344                 info->nand.read_buf   = omap_read_buf_pref;
1345                 info->nand.write_buf  = omap_write_buf_pref;
1346                 break;
1347
1348         case NAND_OMAP_POLLED:
1349                 if (info->nand.options & NAND_BUSWIDTH_16) {
1350                         info->nand.read_buf   = omap_read_buf16;
1351                         info->nand.write_buf  = omap_write_buf16;
1352                 } else {
1353                         info->nand.read_buf   = omap_read_buf8;
1354                         info->nand.write_buf  = omap_write_buf8;
1355                 }
1356                 break;
1357
1358         case NAND_OMAP_PREFETCH_DMA:
1359                 dma_cap_zero(mask);
1360                 dma_cap_set(DMA_SLAVE, mask);
1361                 sig = OMAP24XX_DMA_GPMC;
1362                 info->dma = dma_request_channel(mask, omap_dma_filter_fn, &sig);
1363                 if (!info->dma) {
1364                         dev_err(&pdev->dev, "DMA engine request failed\n");
1365                         err = -ENXIO;
1366                         goto out_release_mem_region;
1367                 } else {
1368                         struct dma_slave_config cfg;
1369
1370                         memset(&cfg, 0, sizeof(cfg));
1371                         cfg.src_addr = info->phys_base;
1372                         cfg.dst_addr = info->phys_base;
1373                         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1374                         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1375                         cfg.src_maxburst = 16;
1376                         cfg.dst_maxburst = 16;
1377                         err = dmaengine_slave_config(info->dma, &cfg);
1378                         if (err) {
1379                                 dev_err(&pdev->dev, "DMA engine slave config failed: %d\n",
1380                                         err);
1381                                 goto out_release_mem_region;
1382                         }
1383                         info->nand.read_buf   = omap_read_buf_dma_pref;
1384                         info->nand.write_buf  = omap_write_buf_dma_pref;
1385                 }
1386                 break;
1387
1388         case NAND_OMAP_PREFETCH_IRQ:
1389                 info->gpmc_irq_fifo = platform_get_irq(pdev, 0);
1390                 if (info->gpmc_irq_fifo <= 0) {
1391                         dev_err(&pdev->dev, "error getting fifo irq\n");
1392                         err = -ENODEV;
1393                         goto out_release_mem_region;
1394                 }
1395                 err = request_irq(info->gpmc_irq_fifo,  omap_nand_irq,
1396                                         IRQF_SHARED, "gpmc-nand-fifo", info);
1397                 if (err) {
1398                         dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1399                                                 info->gpmc_irq_fifo, err);
1400                         info->gpmc_irq_fifo = 0;
1401                         goto out_release_mem_region;
1402                 }
1403
1404                 info->gpmc_irq_count = platform_get_irq(pdev, 1);
1405                 if (info->gpmc_irq_count <= 0) {
1406                         dev_err(&pdev->dev, "error getting count irq\n");
1407                         err = -ENODEV;
1408                         goto out_release_mem_region;
1409                 }
1410                 err = request_irq(info->gpmc_irq_count, omap_nand_irq,
1411                                         IRQF_SHARED, "gpmc-nand-count", info);
1412                 if (err) {
1413                         dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1414                                                 info->gpmc_irq_count, err);
1415                         info->gpmc_irq_count = 0;
1416                         goto out_release_mem_region;
1417                 }
1418
1419                 info->nand.read_buf  = omap_read_buf_irq_pref;
1420                 info->nand.write_buf = omap_write_buf_irq_pref;
1421
1422                 break;
1423
1424         default:
1425                 dev_err(&pdev->dev,
1426                         "xfer_type(%d) not supported!\n", pdata->xfer_type);
1427                 err = -EINVAL;
1428                 goto out_release_mem_region;
1429         }
1430
1431         info->nand.verify_buf = omap_verify_buf;
1432
1433         /* selsect the ecc type */
1434         if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT)
1435                 info->nand.ecc.mode = NAND_ECC_SOFT;
1436         else if ((pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW) ||
1437                 (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE)) {
1438                 info->nand.ecc.bytes            = 3;
1439                 info->nand.ecc.size             = 512;
1440                 info->nand.ecc.strength         = 1;
1441                 info->nand.ecc.calculate        = omap_calculate_ecc;
1442                 info->nand.ecc.hwctl            = omap_enable_hwecc;
1443                 info->nand.ecc.correct          = omap_correct_data;
1444                 info->nand.ecc.mode             = NAND_ECC_HW;
1445         } else if ((pdata->ecc_opt == OMAP_ECC_BCH4_CODE_HW) ||
1446                    (pdata->ecc_opt == OMAP_ECC_BCH8_CODE_HW)) {
1447                 err = omap3_init_bch(&info->mtd, pdata->ecc_opt);
1448                 if (err) {
1449                         err = -EINVAL;
1450                         goto out_release_mem_region;
1451                 }
1452         }
1453
1454         /* DIP switches on some boards change between 8 and 16 bit
1455          * bus widths for flash.  Try the other width if the first try fails.
1456          */
1457         if (nand_scan_ident(&info->mtd, 1, NULL)) {
1458                 info->nand.options ^= NAND_BUSWIDTH_16;
1459                 if (nand_scan_ident(&info->mtd, 1, NULL)) {
1460                         err = -ENXIO;
1461                         goto out_release_mem_region;
1462                 }
1463         }
1464
1465         /* rom code layout */
1466         if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE) {
1467
1468                 if (info->nand.options & NAND_BUSWIDTH_16)
1469                         offset = 2;
1470                 else {
1471                         offset = 1;
1472                         info->nand.badblock_pattern = &bb_descrip_flashbased;
1473                 }
1474                 omap_oobinfo.eccbytes = 3 * (info->mtd.oobsize/16);
1475                 for (i = 0; i < omap_oobinfo.eccbytes; i++)
1476                         omap_oobinfo.eccpos[i] = i+offset;
1477
1478                 omap_oobinfo.oobfree->offset = offset + omap_oobinfo.eccbytes;
1479                 omap_oobinfo.oobfree->length = info->mtd.oobsize -
1480                                         (offset + omap_oobinfo.eccbytes);
1481
1482                 info->nand.ecc.layout = &omap_oobinfo;
1483         } else if ((pdata->ecc_opt == OMAP_ECC_BCH4_CODE_HW) ||
1484                    (pdata->ecc_opt == OMAP_ECC_BCH8_CODE_HW)) {
1485                 /* build OOB layout for BCH ECC correction */
1486                 err = omap3_init_bch_tail(&info->mtd);
1487                 if (err) {
1488                         err = -EINVAL;
1489                         goto out_release_mem_region;
1490                 }
1491         }
1492
1493         /* second phase scan */
1494         if (nand_scan_tail(&info->mtd)) {
1495                 err = -ENXIO;
1496                 goto out_release_mem_region;
1497         }
1498
1499         mtd_device_parse_register(&info->mtd, NULL, NULL, pdata->parts,
1500                                   pdata->nr_parts);
1501
1502         platform_set_drvdata(pdev, &info->mtd);
1503
1504         return 0;
1505
1506 out_release_mem_region:
1507         if (info->dma)
1508                 dma_release_channel(info->dma);
1509         if (info->gpmc_irq_count > 0)
1510                 free_irq(info->gpmc_irq_count, info);
1511         if (info->gpmc_irq_fifo > 0)
1512                 free_irq(info->gpmc_irq_fifo, info);
1513         release_mem_region(info->phys_base, info->mem_size);
1514 out_free_info:
1515         kfree(info);
1516
1517         return err;
1518 }
1519
1520 static int omap_nand_remove(struct platform_device *pdev)
1521 {
1522         struct mtd_info *mtd = platform_get_drvdata(pdev);
1523         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1524                                                         mtd);
1525         omap3_free_bch(&info->mtd);
1526
1527         platform_set_drvdata(pdev, NULL);
1528         if (info->dma)
1529                 dma_release_channel(info->dma);
1530
1531         if (info->gpmc_irq_count > 0)
1532                 free_irq(info->gpmc_irq_count, info);
1533         if (info->gpmc_irq_fifo > 0)
1534                 free_irq(info->gpmc_irq_fifo, info);
1535
1536         /* Release NAND device, its internal structures and partitions */
1537         nand_release(&info->mtd);
1538         iounmap(info->nand.IO_ADDR_R);
1539         kfree(&info->mtd);
1540         return 0;
1541 }
1542
1543 static struct platform_driver omap_nand_driver = {
1544         .probe          = omap_nand_probe,
1545         .remove         = omap_nand_remove,
1546         .driver         = {
1547                 .name   = DRIVER_NAME,
1548                 .owner  = THIS_MODULE,
1549         },
1550 };
1551
1552 module_platform_driver(omap_nand_driver);
1553
1554 MODULE_ALIAS("platform:" DRIVER_NAME);
1555 MODULE_LICENSE("GPL");
1556 MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");