3 * Platform independend driver for NDFC (NanD Flash Controller)
4 * integrated into IBM/AMCC PPC4xx cores
6 * (C) Copyright 2006-2009
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
9 * Based on original work by
13 * See file CREDITS for list of people who contributed to this
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #include <linux/mtd/ndfc.h>
35 #include <linux/mtd/nand_ecc.h>
36 #include <asm/processor.h>
41 * We need to store the info, which chip-select (CS) is used for the
42 * chip number. For example on Sequoia NAND chip #0 uses
45 static int ndfc_cs[NDFC_MAX_BANKS];
47 static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
49 struct nand_chip *this = mtd->priv;
50 ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
52 if (cmd == NAND_CMD_NONE)
56 out_8((u8 *)(base + NDFC_CMD), cmd & 0xFF);
58 out_8((u8 *)(base + NDFC_ALE), cmd & 0xFF);
61 static int ndfc_dev_ready(struct mtd_info *mtdinfo)
63 struct nand_chip *this = mtdinfo->priv;
64 ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
66 return (in_be32((u32 *)(base + NDFC_STAT)) & NDFC_STAT_IS_READY);
69 static void ndfc_enable_hwecc(struct mtd_info *mtdinfo, int mode)
71 struct nand_chip *this = mtdinfo->priv;
72 ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
75 ccr = in_be32((u32 *)(base + NDFC_CCR));
76 ccr |= NDFC_CCR_RESET_ECC;
77 out_be32((u32 *)(base + NDFC_CCR), ccr);
80 static int ndfc_calculate_ecc(struct mtd_info *mtdinfo,
81 const u_char *dat, u_char *ecc_code)
83 struct nand_chip *this = mtdinfo->priv;
84 ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
88 ecc = in_be32((u32 *)(base + NDFC_ECC));
90 /* The NDFC uses Smart Media (SMC) bytes order
100 * Speedups for buffer read/write/verify
102 * NDFC allows 32bit read/write of data. So we can speed up the buffer
103 * functions. No further checking, as nand_base will always read/write
106 static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
108 struct nand_chip *this = mtdinfo->priv;
109 ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
110 uint32_t *p = (uint32_t *) buf;
112 for (;len > 0; len -= 4)
113 *p++ = in_be32((u32 *)(base + NDFC_DATA));
116 #ifndef CONFIG_NAND_SPL
118 * Don't use these speedup functions in NAND boot image, since the image
119 * has to fit into 4kByte.
121 static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
123 struct nand_chip *this = mtdinfo->priv;
124 ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
125 uint32_t *p = (uint32_t *) buf;
127 for (; len > 0; len -= 4)
128 out_be32((u32 *)(base + NDFC_DATA), *p++);
131 static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
133 struct nand_chip *this = mtdinfo->priv;
134 ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
135 uint32_t *p = (uint32_t *) buf;
137 for (; len > 0; len -= 4)
138 if (*p++ != in_be32((u32 *)(base + NDFC_DATA)))
143 #endif /* #ifndef CONFIG_NAND_SPL */
145 #ifndef CONFIG_SYS_NAND_BCR
146 #define CONFIG_SYS_NAND_BCR 0x80002222
149 void board_nand_select_device(struct nand_chip *nand, int chip)
152 * Don't use "chip" to address the NAND device,
153 * generate the cs from the address where it is encoded.
155 ulong base = (ulong)nand->IO_ADDR_W & 0xffffff00;
156 int cs = ndfc_cs[chip];
158 /* Set NandFlash Core Configuration Register */
160 out_be32((u32 *)(base + NDFC_CCR), 0x00000000 | (cs << 24));
161 out_be32((u32 *)(base + NDFC_BCFG0 + (cs << 2)), CONFIG_SYS_NAND_BCR);
164 static void ndfc_select_chip(struct mtd_info *mtd, int chip)
167 * Nothing to do here!
171 int board_nand_init(struct nand_chip *nand)
173 int cs = (ulong)nand->IO_ADDR_W & 0x00000003;
174 ulong base = (ulong)nand->IO_ADDR_W & 0xffffff00;
178 * Save chip-select for this chip #
183 * Select required NAND chip in NDFC
185 board_nand_select_device(nand, chip);
187 nand->IO_ADDR_R = (void __iomem *)(base + NDFC_DATA);
188 nand->IO_ADDR_W = (void __iomem *)(base + NDFC_DATA);
189 nand->cmd_ctrl = ndfc_hwcontrol;
190 nand->chip_delay = 50;
191 nand->read_buf = ndfc_read_buf;
192 nand->dev_ready = ndfc_dev_ready;
193 nand->ecc.correct = nand_correct_data;
194 nand->ecc.hwctl = ndfc_enable_hwecc;
195 nand->ecc.calculate = ndfc_calculate_ecc;
196 nand->ecc.mode = NAND_ECC_HW;
197 nand->ecc.size = 256;
199 nand->select_chip = ndfc_select_chip;
201 #ifndef CONFIG_NAND_SPL
202 nand->write_buf = ndfc_write_buf;
203 nand->verify_buf = ndfc_verify_buf;
206 * Setup EBC (CS0 only right now)
208 mtebc(EBC0_CFG, 0xb8400000);
210 mtebc(pb0cr, CONFIG_SYS_EBC_PB0CR);
211 mtebc(pb0ap, CONFIG_SYS_EBC_PB0AP);