3 * Platform independend driver for NDFC (NanD Flash Controller)
4 * integrated into IBM/AMCC PPC4xx cores
6 * (C) Copyright 2006-2009
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
9 * Based on original work by
13 * See file CREDITS for list of people who contributed to this
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #if defined(CONFIG_CMD_NAND) && !defined(CONFIG_NAND_LEGACY) && \
35 defined(CONFIG_NAND_NDFC)
38 #include <linux/mtd/ndfc.h>
39 #include <linux/mtd/nand_ecc.h>
40 #include <asm/processor.h>
45 * We need to store the info, which chip-select (CS) is used for the
46 * chip number. For example on Sequoia NAND chip #0 uses
49 static int ndfc_cs[NDFC_MAX_BANKS];
51 static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
53 struct nand_chip *this = mtd->priv;
54 ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
56 if (cmd == NAND_CMD_NONE)
60 out_8((u8 *)(base + NDFC_CMD), cmd & 0xFF);
62 out_8((u8 *)(base + NDFC_ALE), cmd & 0xFF);
65 static int ndfc_dev_ready(struct mtd_info *mtdinfo)
67 struct nand_chip *this = mtdinfo->priv;
68 ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
70 return (in_be32((u32 *)(base + NDFC_STAT)) & NDFC_STAT_IS_READY);
73 static void ndfc_enable_hwecc(struct mtd_info *mtdinfo, int mode)
75 struct nand_chip *this = mtdinfo->priv;
76 ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
79 ccr = in_be32((u32 *)(base + NDFC_CCR));
80 ccr |= NDFC_CCR_RESET_ECC;
81 out_be32((u32 *)(base + NDFC_CCR), ccr);
84 static int ndfc_calculate_ecc(struct mtd_info *mtdinfo,
85 const u_char *dat, u_char *ecc_code)
87 struct nand_chip *this = mtdinfo->priv;
88 ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
92 ecc = in_be32((u32 *)(base + NDFC_ECC));
94 /* The NDFC uses Smart Media (SMC) bytes order
104 * Speedups for buffer read/write/verify
106 * NDFC allows 32bit read/write of data. So we can speed up the buffer
107 * functions. No further checking, as nand_base will always read/write
110 static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
112 struct nand_chip *this = mtdinfo->priv;
113 ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
114 uint32_t *p = (uint32_t *) buf;
116 for (;len > 0; len -= 4)
117 *p++ = in_be32((u32 *)(base + NDFC_DATA));
120 #ifndef CONFIG_NAND_SPL
122 * Don't use these speedup functions in NAND boot image, since the image
123 * has to fit into 4kByte.
125 static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
127 struct nand_chip *this = mtdinfo->priv;
128 ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
129 uint32_t *p = (uint32_t *) buf;
131 for (; len > 0; len -= 4)
132 out_be32((u32 *)(base + NDFC_DATA), *p++);
135 static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
137 struct nand_chip *this = mtdinfo->priv;
138 ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
139 uint32_t *p = (uint32_t *) buf;
141 for (; len > 0; len -= 4)
142 if (*p++ != in_be32((u32 *)(base + NDFC_DATA)))
147 #endif /* #ifndef CONFIG_NAND_SPL */
149 #ifndef CONFIG_SYS_NAND_BCR
150 #define CONFIG_SYS_NAND_BCR 0x80002222
153 void board_nand_select_device(struct nand_chip *nand, int chip)
156 * Don't use "chip" to address the NAND device,
157 * generate the cs from the address where it is encoded.
159 ulong base = (ulong)nand->IO_ADDR_W & 0xffffff00;
160 int cs = ndfc_cs[chip];
162 /* Set NandFlash Core Configuration Register */
164 out_be32((u32 *)(base + NDFC_CCR), 0x00000000 | (cs << 24));
165 out_be32((u32 *)(base + NDFC_BCFG0 + (cs << 2)), CONFIG_SYS_NAND_BCR);
168 static void ndfc_select_chip(struct mtd_info *mtd, int chip)
171 * Nothing to do here!
175 int board_nand_init(struct nand_chip *nand)
177 int cs = (ulong)nand->IO_ADDR_W & 0x00000003;
178 ulong base = (ulong)nand->IO_ADDR_W & 0xffffff00;
182 * Save chip-select for this chip #
187 * Select required NAND chip in NDFC
189 board_nand_select_device(nand, chip);
191 nand->IO_ADDR_R = (void __iomem *)(base + NDFC_DATA);
192 nand->IO_ADDR_W = (void __iomem *)(base + NDFC_DATA);
193 nand->cmd_ctrl = ndfc_hwcontrol;
194 nand->chip_delay = 50;
195 nand->read_buf = ndfc_read_buf;
196 nand->dev_ready = ndfc_dev_ready;
197 nand->ecc.correct = nand_correct_data;
198 nand->ecc.hwctl = ndfc_enable_hwecc;
199 nand->ecc.calculate = ndfc_calculate_ecc;
200 nand->ecc.mode = NAND_ECC_HW;
201 nand->ecc.size = 256;
203 nand->select_chip = ndfc_select_chip;
205 #ifndef CONFIG_NAND_SPL
206 nand->write_buf = ndfc_write_buf;
207 nand->verify_buf = ndfc_verify_buf;
210 * Setup EBC (CS0 only right now)
212 mtebc(EBC0_CFG, 0xb8400000);
214 mtebc(pb0cr, CONFIG_SYS_EBC_PB0CR);
215 mtebc(pb0ap, CONFIG_SYS_EBC_PB0AP);