drivers/mtd/nand/nand_base.c

   1 /*
   2  *  drivers/mtd/nand.c
   3  *
   4  *  Overview:
   5  *   This is the generic MTD driver for NAND flash devices. It should be
   6  *   capable of working with almost all NAND chips currently available.
   7  *   Basic support for AG-AND chips is provided.
   8  *
   9  *      Additional technical information is available on
  10  *      http://www.linux-mtd.infradead.org/doc/nand.html
  11  *
  12  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  13  *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
  14  *
  15  *  Credits:
  16  *      David Woodhouse for adding multichip support
  17  *
  18  *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  19  *      rework for 2K page size chips
  20  *
  21  *  TODO:
  22  *      Enable cached programming for 2k page size chips
  23  *      Check, if mtd->ecctype should be set to MTD_ECC_HW
  24  *      if we have HW ecc support.
  25  *      The AG-AND chips have nice features for speed improvement,
  26  *      which are not supported yet. Read / program 4 pages in one go.
  27  *      BBT table is not serialized, has to be fixed
  28  *
  29  * This program is free software; you can redistribute it and/or modify
  30  * it under the terms of the GNU General Public License version 2 as
  31  * published by the Free Software Foundation.
  32  *
  33  */
  34
  35 #include <common.h>
  36
  37 #define ENOTSUPP        524     /* Operation is not supported */
  38
  39 #include <malloc.h>
  40 #include <watchdog.h>
  41 #include <linux/err.h>
  42 #include <linux/mtd/compat.h>
  43 #include <linux/mtd/mtd.h>
  44 #include <linux/mtd/nand.h>
  45 #include <linux/mtd/nand_ecc.h>
  46 #include <linux/mtd/nand_bch.h>
  47
  48 #ifdef CONFIG_MTD_PARTITIONS
  49 #include <linux/mtd/partitions.h>
  50 #endif
  51
  52 #include <asm/io.h>
  53 #include <asm/errno.h>
  54
  55 /*
  56  * CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting
  57  * a flash.  NAND flash is initialized prior to interrupts so standard timers
  58  * can't be used.  CONFIG_SYS_NAND_RESET_CNT should be set to a value
  59  * which is greater than (max NAND reset time / NAND status read time).
  60  * A conservative default of 200000 (500 us / 25 ns) is used as a default.
  61  */
  62 #ifndef CONFIG_SYS_NAND_RESET_CNT
  63 #define CONFIG_SYS_NAND_RESET_CNT 200000
  64 #endif
  65
  66 /* Define default oob placement schemes for large and small page devices */
  67 static struct nand_ecclayout nand_oob_8 = {
  68         .eccbytes = 3,
  69         .eccpos = {0, 1, 2},
  70         .oobfree = {
  71                 {.offset = 3,
  72                  .length = 2},
  73                 {.offset = 6,
  74                  .length = 2}}
  75 };
  76
  77 static struct nand_ecclayout nand_oob_16 = {
  78         .eccbytes = 6,
  79         .eccpos = {0, 1, 2, 3, 6, 7},
  80         .oobfree = {
  81                 {.offset = 8,
  82                  . length = 8}}
  83 };
  84
  85 static struct nand_ecclayout nand_oob_64 = {
  86         .eccbytes = 24,
  87         .eccpos = {
  88                    40, 41, 42, 43, 44, 45, 46, 47,
  89                    48, 49, 50, 51, 52, 53, 54, 55,
  90                    56, 57, 58, 59, 60, 61, 62, 63},
  91         .oobfree = {
  92                 {.offset = 2,
  93                  .length = 38}}
  94 };
  95
  96 static struct nand_ecclayout nand_oob_128 = {
  97         .eccbytes = 48,
  98         .eccpos = {
  99                     80,  81,  82,  83,  84,  85,  86,  87,
 100                     88,  89,  90,  91,  92,  93,  94,  95,
 101                     96,  97,  98,  99, 100, 101, 102, 103,
 102                    104, 105, 106, 107, 108, 109, 110, 111,
 103                    112, 113, 114, 115, 116, 117, 118, 119,
 104                    120, 121, 122, 123, 124, 125, 126, 127},
 105         .oobfree = {
 106                 {.offset = 2,
 107                  .length = 78}}
 108 };
 109
 110
 111 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
 112                            int new_state);
 113
 114 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
 115                              struct mtd_oob_ops *ops);
 116
 117 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this);
 118
 119 /**
 120  * nand_release_device - [GENERIC] release chip
 121  * @mtd:        MTD device structure
 122  *
 123  * Deselect, release chip lock and wake up anyone waiting on the device
 124  */
 125 static void nand_release_device (struct mtd_info *mtd)
 126 {
 127         struct nand_chip *this = mtd->priv;
 128         this->select_chip(mtd, -1);     /* De-select the NAND device */
 129 }
 130
 131 /**
 132  * nand_read_byte - [DEFAULT] read one byte from the chip
 133  * @mtd:        MTD device structure
 134  *
 135  * Default read function for 8bit buswith
 136  */
 137 uint8_t nand_read_byte(struct mtd_info *mtd)
 138 {
 139         struct nand_chip *chip = mtd->priv;
 140         return readb(chip->IO_ADDR_R);
 141 }
 142
 143 /**
 144  * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
 145  * @mtd:        MTD device structure
 146  *
 147  * Default read function for 16bit buswith with
 148  * endianess conversion
 149  */
 150 static uint8_t nand_read_byte16(struct mtd_info *mtd)
 151 {
 152         struct nand_chip *chip = mtd->priv;
 153         return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
 154 }
 155
 156 /**
 157  * nand_read_word - [DEFAULT] read one word from the chip
 158  * @mtd:        MTD device structure
 159  *
 160  * Default read function for 16bit buswith without
 161  * endianess conversion
 162  */
 163 static u16 nand_read_word(struct mtd_info *mtd)
 164 {
 165         struct nand_chip *chip = mtd->priv;
 166         return readw(chip->IO_ADDR_R);
 167 }
 168
 169 /**
 170  * nand_select_chip - [DEFAULT] control CE line
 171  * @mtd:        MTD device structure
 172  * @chipnr:     chipnumber to select, -1 for deselect
 173  *
 174  * Default select function for 1 chip devices.
 175  */
 176 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 177 {
 178         struct nand_chip *chip = mtd->priv;
 179
 180         switch (chipnr) {
 181         case -1:
 182                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
 183                 break;
 184         case 0:
 185                 break;
 186
 187         default:
 188                 BUG();
 189         }
 190 }
 191
 192 /**
 193  * nand_write_buf - [DEFAULT] write buffer to chip
 194  * @mtd:        MTD device structure
 195  * @buf:        data buffer
 196  * @len:        number of bytes to write
 197  *
 198  * Default write function for 8bit buswith
 199  */
 200 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 201 {
 202         int i;
 203         struct nand_chip *chip = mtd->priv;
 204
 205         for (i = 0; i < len; i++)
 206                 writeb(buf[i], chip->IO_ADDR_W);
 207 }
 208
 209 /**
 210  * nand_read_buf - [DEFAULT] read chip data into buffer
 211  * @mtd:        MTD device structure
 212  * @buf:        buffer to store date
 213  * @len:        number of bytes to read
 214  *
 215  * Default read function for 8bit buswith
 216  */
 217 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 218 {
 219         int i;
 220         struct nand_chip *chip = mtd->priv;
 221
 222         for (i = 0; i < len; i++)
 223                 buf[i] = readb(chip->IO_ADDR_R);
 224 }
 225
 226 /**
 227  * nand_verify_buf - [DEFAULT] Verify chip data against buffer
 228  * @mtd:        MTD device structure
 229  * @buf:        buffer containing the data to compare
 230  * @len:        number of bytes to compare
 231  *
 232  * Default verify function for 8bit buswith
 233  */
 234 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 235 {
 236         int i;
 237         struct nand_chip *chip = mtd->priv;
 238
 239         for (i = 0; i < len; i++)
 240                 if (buf[i] != readb(chip->IO_ADDR_R))
 241                         return -EFAULT;
 242         return 0;
 243 }
 244
 245 /**
 246  * nand_write_buf16 - [DEFAULT] write buffer to chip
 247  * @mtd:        MTD device structure
 248  * @buf:        data buffer
 249  * @len:        number of bytes to write
 250  *
 251  * Default write function for 16bit buswith
 252  */
 253 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 254 {
 255         int i;
 256         struct nand_chip *chip = mtd->priv;
 257         u16 *p = (u16 *) buf;
 258         len >>= 1;
 259
 260         for (i = 0; i < len; i++)
 261                 writew(p[i], chip->IO_ADDR_W);
 262
 263 }
 264
 265 /**
 266  * nand_read_buf16 - [DEFAULT] read chip data into buffer
 267  * @mtd:        MTD device structure
 268  * @buf:        buffer to store date
 269  * @len:        number of bytes to read
 270  *
 271  * Default read function for 16bit buswith
 272  */
 273 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 274 {
 275         int i;
 276         struct nand_chip *chip = mtd->priv;
 277         u16 *p = (u16 *) buf;
 278         len >>= 1;
 279
 280         for (i = 0; i < len; i++)
 281                 p[i] = readw(chip->IO_ADDR_R);
 282 }
 283
 284 /**
 285  * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
 286  * @mtd:        MTD device structure
 287  * @buf:        buffer containing the data to compare
 288  * @len:        number of bytes to compare
 289  *
 290  * Default verify function for 16bit buswith
 291  */
 292 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 293 {
 294         int i;
 295         struct nand_chip *chip = mtd->priv;
 296         u16 *p = (u16 *) buf;
 297         len >>= 1;
 298
 299         for (i = 0; i < len; i++)
 300                 if (p[i] != readw(chip->IO_ADDR_R))
 301                         return -EFAULT;
 302
 303         return 0;
 304 }
 305
 306 /**
 307  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
 308  * @mtd:        MTD device structure
 309  * @ofs:        offset from device start
 310  * @getchip:    0, if the chip is already selected
 311  *
 312  * Check, if the block is bad.
 313  */
 314 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 315 {
 316         int page, chipnr, res = 0;
 317         struct nand_chip *chip = mtd->priv;
 318         u16 bad;
 319
 320         page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 321
 322         if (getchip) {
 323                 chipnr = (int)(ofs >> chip->chip_shift);
 324
 325                 nand_get_device(chip, mtd, FL_READING);
 326
 327                 /* Select the NAND device */
 328                 chip->select_chip(mtd, chipnr);
 329         }
 330
 331         if (chip->options & NAND_BUSWIDTH_16) {
 332                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
 333                               page);
 334                 bad = cpu_to_le16(chip->read_word(mtd));
 335                 if (chip->badblockpos & 0x1)
 336                         bad >>= 8;
 337                 if ((bad & 0xFF) != 0xff)
 338                         res = 1;
 339         } else {
 340                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
 341                 if (chip->read_byte(mtd) != 0xff)
 342                         res = 1;
 343         }
 344
 345         if (getchip)
 346                 nand_release_device(mtd);
 347
 348         return res;
 349 }
 350
 351 /**
 352  * nand_default_block_markbad - [DEFAULT] mark a block bad
 353  * @mtd:        MTD device structure
 354  * @ofs:        offset from device start
 355  *
 356  * This is the default implementation, which can be overridden by
 357  * a hardware specific driver.
 358 */
 359 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 360 {
 361         struct nand_chip *chip = mtd->priv;
 362         uint8_t buf[2] = { 0, 0 };
 363         int block, ret;
 364
 365         /* Get block number */
 366         block = (int)(ofs >> chip->bbt_erase_shift);
 367         if (chip->bbt)
 368                 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
 369
 370         /* Do we have a flash based bad block table ? */
 371         if (chip->options & NAND_USE_FLASH_BBT)
 372                 ret = nand_update_bbt(mtd, ofs);
 373         else {
 374                 /* We write two bytes, so we dont have to mess with 16 bit
 375                  * access
 376                  */
 377                 nand_get_device(chip, mtd, FL_WRITING);
 378                 ofs += mtd->oobsize;
 379                 chip->ops.len = chip->ops.ooblen = 2;
 380                 chip->ops.datbuf = NULL;
 381                 chip->ops.oobbuf = buf;
 382                 chip->ops.ooboffs = chip->badblockpos & ~0x01;
 383
 384                 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
 385                 nand_release_device(mtd);
 386         }
 387         if (!ret)
 388                 mtd->ecc_stats.badblocks++;
 389
 390         return ret;
 391 }
 392
 393 /**
 394  * nand_check_wp - [GENERIC] check if the chip is write protected
 395  * @mtd:        MTD device structure
 396  * Check, if the device is write protected
 397  *
 398  * The function expects, that the device is already selected
 399  */
 400 static int nand_check_wp(struct mtd_info *mtd)
 401 {
 402         struct nand_chip *chip = mtd->priv;
 403         /* Check the WP bit */
 404         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 405         return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
 406 }
 407
 408 /**
 409  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
 410  * @mtd:        MTD device structure
 411  * @ofs:        offset from device start
 412  * @getchip:    0, if the chip is already selected
 413  * @allowbbt:   1, if its allowed to access the bbt area
 414  *
 415  * Check, if the block is bad. Either by reading the bad block table or
 416  * calling of the scan function.
 417  */
 418 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
 419                                int allowbbt)
 420 {
 421         struct nand_chip *chip = mtd->priv;
 422
 423         if (!(chip->options & NAND_BBT_SCANNED)) {
 424                 chip->options |= NAND_BBT_SCANNED;
 425                 chip->scan_bbt(mtd);
 426         }
 427
 428         if (!chip->bbt)
 429                 return chip->block_bad(mtd, ofs, getchip);
 430
 431         /* Return info from the table */
 432         return nand_isbad_bbt(mtd, ofs, allowbbt);
 433 }
 434
 435 /*
 436  * Wait for the ready pin, after a command
 437  * The timeout is catched later.
 438  */
 439 void nand_wait_ready(struct mtd_info *mtd)
 440 {
 441         struct nand_chip *chip = mtd->priv;
 442         u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
 443         u32 time_start;
 444
 445         time_start = get_timer(0);
 446
 447         /* wait until command is processed or timeout occures */
 448         while (get_timer(time_start) < timeo) {
 449                 if (chip->dev_ready)
 450                         if (chip->dev_ready(mtd))
 451                                 break;
 452         }
 453 }
 454
 455 /**
 456  * nand_command - [DEFAULT] Send command to NAND device
 457  * @mtd:        MTD device structure
 458  * @command:    the command to be sent
 459  * @column:     the column address for this command, -1 if none
 460  * @page_addr:  the page address for this command, -1 if none
 461  *
 462  * Send command to NAND device. This function is used for small page
 463  * devices (256/512 Bytes per page)
 464  */
 465 static void nand_command(struct mtd_info *mtd, unsigned int command,
 466                          int column, int page_addr)
 467 {
 468         register struct nand_chip *chip = mtd->priv;
 469         int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
 470         uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
 471
 472         /*
 473          * Write out the command to the device.
 474          */
 475         if (command == NAND_CMD_SEQIN) {
 476                 int readcmd;
 477
 478                 if (column >= mtd->writesize) {
 479                         /* OOB area */
 480                         column -= mtd->writesize;
 481                         readcmd = NAND_CMD_READOOB;
 482                 } else if (column < 256) {
 483                         /* First 256 bytes --> READ0 */
 484                         readcmd = NAND_CMD_READ0;
 485                 } else {
 486                         column -= 256;
 487                         readcmd = NAND_CMD_READ1;
 488                 }
 489                 chip->cmd_ctrl(mtd, readcmd, ctrl);
 490                 ctrl &= ~NAND_CTRL_CHANGE;
 491         }
 492         chip->cmd_ctrl(mtd, command, ctrl);
 493
 494         /*
 495          * Address cycle, when necessary
 496          */
 497         ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
 498         /* Serially input address */
 499         if (column != -1) {
 500                 /* Adjust columns for 16 bit buswidth */
 501                 if (chip->options & NAND_BUSWIDTH_16)
 502                         column >>= 1;
 503                 chip->cmd_ctrl(mtd, column, ctrl);
 504                 ctrl &= ~NAND_CTRL_CHANGE;
 505         }
 506         if (page_addr != -1) {
 507                 chip->cmd_ctrl(mtd, page_addr, ctrl);
 508                 ctrl &= ~NAND_CTRL_CHANGE;
 509                 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
 510                 /* One more address cycle for devices > 32MiB */
 511                 if (chip->chipsize > (32 << 20))
 512                         chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
 513         }
 514         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 515
 516         /*
 517          * program and erase have their own busy handlers
 518          * status and sequential in needs no delay
 519          */
 520         switch (command) {
 521
 522         case NAND_CMD_PAGEPROG:
 523         case NAND_CMD_ERASE1:
 524         case NAND_CMD_ERASE2:
 525         case NAND_CMD_SEQIN:
 526         case NAND_CMD_STATUS:
 527                 return;
 528
 529         case NAND_CMD_RESET:
 530                 if (chip->dev_ready)
 531                         break;
 532                 udelay(chip->chip_delay);
 533                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 534                                NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 535                 chip->cmd_ctrl(mtd,
 536                                NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 537                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
 538                         (rst_sts_cnt--));
 539                 return;
 540
 541                 /* This applies to read commands */
 542         default:
 543                 /*
 544                  * If we don't have access to the busy pin, we apply the given
 545                  * command delay
 546                  */
 547                 if (!chip->dev_ready) {
 548                         udelay(chip->chip_delay);
 549                         return;
 550                 }
 551         }
 552         /* Apply this short delay always to ensure that we do wait tWB in
 553          * any case on any machine. */
 554         ndelay(100);
 555
 556         nand_wait_ready(mtd);
 557 }
 558
 559 /**
 560  * nand_command_lp - [DEFAULT] Send command to NAND large page device
 561  * @mtd:        MTD device structure
 562  * @command:    the command to be sent
 563  * @column:     the column address for this command, -1 if none
 564  * @page_addr:  the page address for this command, -1 if none
 565  *
 566  * Send command to NAND device. This is the version for the new large page
 567  * devices We dont have the separate regions as we have in the small page
 568  * devices.  We must emulate NAND_CMD_READOOB to keep the code compatible.
 569  */
 570 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
 571                             int column, int page_addr)
 572 {
 573         register struct nand_chip *chip = mtd->priv;
 574         uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
 575
 576         /* Emulate NAND_CMD_READOOB */
 577         if (command == NAND_CMD_READOOB) {
 578                 column += mtd->writesize;
 579                 command = NAND_CMD_READ0;
 580         }
 581
 582         /* Command latch cycle */
 583         chip->cmd_ctrl(mtd, command & 0xff,
 584                        NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 585
 586         if (column != -1 || page_addr != -1) {
 587                 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
 588
 589                 /* Serially input address */
 590                 if (column != -1) {
 591                         /* Adjust columns for 16 bit buswidth */
 592                         if (chip->options & NAND_BUSWIDTH_16)
 593                                 column >>= 1;
 594                         chip->cmd_ctrl(mtd, column, ctrl);
 595                         ctrl &= ~NAND_CTRL_CHANGE;
 596                         chip->cmd_ctrl(mtd, column >> 8, ctrl);
 597                 }
 598                 if (page_addr != -1) {
 599                         chip->cmd_ctrl(mtd, page_addr, ctrl);
 600                         chip->cmd_ctrl(mtd, page_addr >> 8,
 601                                        NAND_NCE | NAND_ALE);
 602                         /* One more address cycle for devices > 128MiB */
 603                         if (chip->chipsize > (128 << 20))
 604                                 chip->cmd_ctrl(mtd, page_addr >> 16,
 605                                                NAND_NCE | NAND_ALE);
 606                 }
 607         }
 608         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 609
 610         /*
 611          * program and erase have their own busy handlers
 612          * status, sequential in, and deplete1 need no delay
 613          */
 614         switch (command) {
 615
 616         case NAND_CMD_CACHEDPROG:
 617         case NAND_CMD_PAGEPROG:
 618         case NAND_CMD_ERASE1:
 619         case NAND_CMD_ERASE2:
 620         case NAND_CMD_SEQIN:
 621         case NAND_CMD_RNDIN:
 622         case NAND_CMD_STATUS:
 623         case NAND_CMD_DEPLETE1:
 624                 return;
 625
 626                 /*
 627                  * read error status commands require only a short delay
 628                  */
 629         case NAND_CMD_STATUS_ERROR:
 630         case NAND_CMD_STATUS_ERROR0:
 631         case NAND_CMD_STATUS_ERROR1:
 632         case NAND_CMD_STATUS_ERROR2:
 633         case NAND_CMD_STATUS_ERROR3:
 634                 udelay(chip->chip_delay);
 635                 return;
 636
 637         case NAND_CMD_RESET:
 638                 if (chip->dev_ready)
 639                         break;
 640                 udelay(chip->chip_delay);
 641                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 642                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 643                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 644                                NAND_NCE | NAND_CTRL_CHANGE);
 645                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
 646                         (rst_sts_cnt--));
 647                 return;
 648
 649         case NAND_CMD_RNDOUT:
 650                 /* No ready / busy check necessary */
 651                 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
 652                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 653                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 654                                NAND_NCE | NAND_CTRL_CHANGE);
 655                 return;
 656
 657         case NAND_CMD_READ0:
 658                 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
 659                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 660                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 661                                NAND_NCE | NAND_CTRL_CHANGE);
 662
 663                 /* This applies to read commands */
 664         default:
 665                 /*
 666                  * If we don't have access to the busy pin, we apply the given
 667                  * command delay
 668                  */
 669                 if (!chip->dev_ready) {
 670                         udelay(chip->chip_delay);
 671                         return;
 672                 }
 673         }
 674
 675         /* Apply this short delay always to ensure that we do wait tWB in
 676          * any case on any machine. */
 677         ndelay(100);
 678
 679         nand_wait_ready(mtd);
 680 }
 681
 682 /**
 683  * nand_get_device - [GENERIC] Get chip for selected access
 684  * @chip:       the nand chip descriptor
 685  * @mtd:        MTD device structure
 686  * @new_state:  the state which is requested
 687  *
 688  * Get the device and lock it for exclusive access
 689  */
 690 static int nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state)
 691 {
 692         this->state = new_state;
 693         return 0;
 694 }
 695
 696 /**
 697  * nand_wait - [DEFAULT]  wait until the command is done
 698  * @mtd:        MTD device structure
 699  * @chip:       NAND chip structure
 700  *
 701  * Wait for command done. This applies to erase and program only
 702  * Erase can take up to 400ms and program up to 20ms according to
 703  * general NAND and SmartMedia specs
 704  */
 705 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this)
 706 {
 707         unsigned long   timeo;
 708         int state = this->state;
 709         u32 time_start;
 710
 711         if (state == FL_ERASING)
 712                 timeo = (CONFIG_SYS_HZ * 400) / 1000;
 713         else
 714                 timeo = (CONFIG_SYS_HZ * 20) / 1000;
 715
 716         if ((state == FL_ERASING) && (this->options & NAND_IS_AND))
 717                 this->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
 718         else
 719                 this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 720
 721         time_start = get_timer(0);
 722
 723         while (1) {
 724                 if (get_timer(time_start) > timeo) {
 725                         printf("Timeout!");
 726                         return 0x01;
 727                 }
 728
 729                 if (this->dev_ready) {
 730                         if (this->dev_ready(mtd))
 731                                 break;
 732                 } else {
 733                         if (this->read_byte(mtd) & NAND_STATUS_READY)
 734                                 break;
 735                 }
 736         }
 737 #ifdef PPCHAMELON_NAND_TIMER_HACK
 738         time_start = get_timer(0);
 739         while (get_timer(time_start) < 10)
 740                 ;
 741 #endif /*  PPCHAMELON_NAND_TIMER_HACK */
 742
 743         return this->read_byte(mtd);
 744 }
 745
 746 /**
 747  * nand_read_page_raw - [Intern] read raw page data without ecc
 748  * @mtd:        mtd info structure
 749  * @chip:       nand chip info structure
 750  * @buf:        buffer to store read data
 751  * @page:       page number to read
 752  *
 753  * Not for syndrome calculating ecc controllers, which use a special oob layout
 754  */
 755 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
 756                               uint8_t *buf, int page)
 757 {
 758         chip->read_buf(mtd, buf, mtd->writesize);
 759         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 760         return 0;
 761 }
 762
 763 /**
 764  * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
 765  * @mtd:        mtd info structure
 766  * @chip:       nand chip info structure
 767  * @buf:        buffer to store read data
 768  * @page:       page number to read
 769  *
 770  * We need a special oob layout and handling even when OOB isn't used.
 771  */
 772 static int nand_read_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
 773                               uint8_t *buf, int page)
 774 {
 775         int eccsize = chip->ecc.size;
 776         int eccbytes = chip->ecc.bytes;
 777         uint8_t *oob = chip->oob_poi;
 778         int steps, size;
 779
 780         for (steps = chip->ecc.steps; steps > 0; steps--) {
 781                 chip->read_buf(mtd, buf, eccsize);
 782                 buf += eccsize;
 783
 784                 if (chip->ecc.prepad) {
 785                         chip->read_buf(mtd, oob, chip->ecc.prepad);
 786                         oob += chip->ecc.prepad;
 787                 }
 788
 789                 chip->read_buf(mtd, oob, eccbytes);
 790                 oob += eccbytes;
 791
 792                 if (chip->ecc.postpad) {
 793                         chip->read_buf(mtd, oob, chip->ecc.postpad);
 794                         oob += chip->ecc.postpad;
 795                 }
 796         }
 797
 798         size = mtd->oobsize - (oob - chip->oob_poi);
 799         if (size)
 800                 chip->read_buf(mtd, oob, size);
 801
 802         return 0;
 803 }
 804
 805 /**
 806  * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
 807  * @mtd:        mtd info structure
 808  * @chip:       nand chip info structure
 809  * @buf:        buffer to store read data
 810  * @page:       page number to read
 811  */
 812 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
 813                                 uint8_t *buf, int page)
 814 {
 815         int i, eccsize = chip->ecc.size;
 816         int eccbytes = chip->ecc.bytes;
 817         int eccsteps = chip->ecc.steps;
 818         uint8_t *p = buf;
 819         uint8_t *ecc_calc = chip->buffers->ecccalc;
 820         uint8_t *ecc_code = chip->buffers->ecccode;
 821         uint32_t *eccpos = chip->ecc.layout->eccpos;
 822
 823         chip->ecc.read_page_raw(mtd, chip, buf, page);
 824
 825         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
 826                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 827
 828         for (i = 0; i < chip->ecc.total; i++)
 829                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 830
 831         eccsteps = chip->ecc.steps;
 832         p = buf;
 833
 834         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 835                 int stat;
 836
 837                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 838                 if (stat < 0)
 839                         mtd->ecc_stats.failed++;
 840                 else
 841                         mtd->ecc_stats.corrected += stat;
 842         }
 843         return 0;
 844 }
 845
 846 /**
 847  * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
 848  * @mtd:        mtd info structure
 849  * @chip:       nand chip info structure
 850  * @data_offs:  offset of requested data within the page
 851  * @readlen:    data length
 852  * @bufpoi:     buffer to store read data
 853  */
 854 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
 855 {
 856         int start_step, end_step, num_steps;
 857         uint32_t *eccpos = chip->ecc.layout->eccpos;
 858         uint8_t *p;
 859         int data_col_addr, i, gaps = 0;
 860         int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
 861         int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
 862
 863         /* Column address wihin the page aligned to ECC size (256bytes). */
 864         start_step = data_offs / chip->ecc.size;
 865         end_step = (data_offs + readlen - 1) / chip->ecc.size;
 866         num_steps = end_step - start_step + 1;
 867
 868         /* Data size aligned to ECC ecc.size*/
 869         datafrag_len = num_steps * chip->ecc.size;
 870         eccfrag_len = num_steps * chip->ecc.bytes;
 871
 872         data_col_addr = start_step * chip->ecc.size;
 873         /* If we read not a page aligned data */
 874         if (data_col_addr != 0)
 875                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
 876
 877         p = bufpoi + data_col_addr;
 878         chip->read_buf(mtd, p, datafrag_len);
 879
 880         /* Calculate  ECC */
 881         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
 882                 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
 883
 884         /* The performance is faster if to position offsets
 885            according to ecc.pos. Let make sure here that
 886            there are no gaps in ecc positions */
 887         for (i = 0; i < eccfrag_len - 1; i++) {
 888                 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
 889                         eccpos[i + start_step * chip->ecc.bytes + 1]) {
 890                         gaps = 1;
 891                         break;
 892                 }
 893         }
 894         if (gaps) {
 895                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
 896                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 897         } else {
 898                 /* send the command to read the particular ecc bytes */
 899                 /* take care about buswidth alignment in read_buf */
 900                 aligned_pos = eccpos[start_step * chip->ecc.bytes] & ~(busw - 1);
 901                 aligned_len = eccfrag_len;
 902                 if (eccpos[start_step * chip->ecc.bytes] & (busw - 1))
 903                         aligned_len++;
 904                 if (eccpos[(start_step + num_steps) * chip->ecc.bytes] & (busw - 1))
 905                         aligned_len++;
 906
 907                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize + aligned_pos, -1);
 908                 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
 909         }
 910
 911         for (i = 0; i < eccfrag_len; i++)
 912                 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + start_step * chip->ecc.bytes]];
 913
 914         p = bufpoi + data_col_addr;
 915         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
 916                 int stat;
 917
 918                 stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
 919                 if (stat == -1)
 920                         mtd->ecc_stats.failed++;
 921                 else
 922                         mtd->ecc_stats.corrected += stat;
 923         }
 924         return 0;
 925 }
 926
 927 /**
 928  * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
 929  * @mtd:        mtd info structure
 930  * @chip:       nand chip info structure
 931  * @buf:        buffer to store read data
 932  * @page:       page number to read
 933  *
 934  * Not for syndrome calculating ecc controllers which need a special oob layout
 935  */
 936 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
 937                                 uint8_t *buf, int page)
 938 {
 939         int i, eccsize = chip->ecc.size;
 940         int eccbytes = chip->ecc.bytes;
 941         int eccsteps = chip->ecc.steps;
 942         uint8_t *p = buf;
 943         uint8_t *ecc_calc = chip->buffers->ecccalc;
 944         uint8_t *ecc_code = chip->buffers->ecccode;
 945         uint32_t *eccpos = chip->ecc.layout->eccpos;
 946
 947         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 948                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 949                 chip->read_buf(mtd, p, eccsize);
 950                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 951         }
 952         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 953
 954         for (i = 0; i < chip->ecc.total; i++)
 955                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 956
 957         eccsteps = chip->ecc.steps;
 958         p = buf;
 959
 960         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 961                 int stat;
 962
 963                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 964                 if (stat < 0)
 965                         mtd->ecc_stats.failed++;
 966                 else
 967                         mtd->ecc_stats.corrected += stat;
 968         }
 969         return 0;
 970 }
 971
 972 /**
 973  * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
 974  * @mtd:        mtd info structure
 975  * @chip:       nand chip info structure
 976  * @buf:        buffer to store read data
 977  * @page:       page number to read
 978  *
 979  * Hardware ECC for large page chips, require OOB to be read first.
 980  * For this ECC mode, the write_page method is re-used from ECC_HW.
 981  * These methods read/write ECC from the OOB area, unlike the
 982  * ECC_HW_SYNDROME support with multiple ECC steps, follows the
 983  * "infix ECC" scheme and reads/writes ECC from the data area, by
 984  * overwriting the NAND manufacturer bad block markings.
 985  */
 986 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
 987         struct nand_chip *chip, uint8_t *buf, int page)
 988 {
 989         int i, eccsize = chip->ecc.size;
 990         int eccbytes = chip->ecc.bytes;
 991         int eccsteps = chip->ecc.steps;
 992         uint8_t *p = buf;
 993         uint8_t *ecc_code = chip->buffers->ecccode;
 994         uint32_t *eccpos = chip->ecc.layout->eccpos;
 995         uint8_t *ecc_calc = chip->buffers->ecccalc;
 996
 997         /* Read the OOB area first */
 998         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
 999         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1000         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1001
1002         for (i = 0; i < chip->ecc.total; i++)
1003                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1004
1005         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1006                 int stat;
1007
1008                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1009                 chip->read_buf(mtd, p, eccsize);
1010                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1011
1012                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1013                 if (stat < 0)
1014                         mtd->ecc_stats.failed++;
1015                 else
1016                         mtd->ecc_stats.corrected += stat;
1017         }
1018         return 0;
1019 }
1020
1021 /**
1022  * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
1023  * @mtd:        mtd info structure
1024  * @chip:       nand chip info structure
1025  * @buf:        buffer to store read data
1026  * @page:       page number to read
1027  *
1028  * The hw generator calculates the error syndrome automatically. Therefor
1029  * we need a special oob layout and handling.
1030  */
1031 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1032                                    uint8_t *buf, int page)
1033 {
1034         int i, eccsize = chip->ecc.size;
1035         int eccbytes = chip->ecc.bytes;
1036         int eccsteps = chip->ecc.steps;
1037         uint8_t *p = buf;
1038         uint8_t *oob = chip->oob_poi;
1039
1040         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1041                 int stat;
1042
1043                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1044                 chip->read_buf(mtd, p, eccsize);
1045
1046                 if (chip->ecc.prepad) {
1047                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1048                         oob += chip->ecc.prepad;
1049                 }
1050
1051                 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1052                 chip->read_buf(mtd, oob, eccbytes);
1053                 stat = chip->ecc.correct(mtd, p, oob, NULL);
1054
1055                 if (stat < 0)
1056                         mtd->ecc_stats.failed++;
1057                 else
1058                         mtd->ecc_stats.corrected += stat;
1059
1060                 oob += eccbytes;
1061
1062                 if (chip->ecc.postpad) {
1063                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1064                         oob += chip->ecc.postpad;
1065                 }
1066         }
1067
1068         /* Calculate remaining oob bytes */
1069         i = mtd->oobsize - (oob - chip->oob_poi);
1070         if (i)
1071                 chip->read_buf(mtd, oob, i);
1072
1073         return 0;
1074 }
1075
1076 /**
1077  * nand_transfer_oob - [Internal] Transfer oob to client buffer
1078  * @chip:       nand chip structure
1079  * @oob:        oob destination address
1080  * @ops:        oob ops structure
1081  * @len:        size of oob to transfer
1082  */
1083 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1084                                   struct mtd_oob_ops *ops, size_t len)
1085 {
1086         switch(ops->mode) {
1087
1088         case MTD_OOB_PLACE:
1089         case MTD_OOB_RAW:
1090                 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1091                 return oob + len;
1092
1093         case MTD_OOB_AUTO: {
1094                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1095                 uint32_t boffs = 0, roffs = ops->ooboffs;
1096                 size_t bytes = 0;
1097
1098                 for(; free->length && len; free++, len -= bytes) {
1099                         /* Read request not from offset 0 ? */
1100                         if (unlikely(roffs)) {
1101                                 if (roffs >= free->length) {
1102                                         roffs -= free->length;
1103                                         continue;
1104                                 }
1105                                 boffs = free->offset + roffs;
1106                                 bytes = min_t(size_t, len,
1107                                               (free->length - roffs));
1108                                 roffs = 0;
1109                         } else {
1110                                 bytes = min_t(size_t, len, free->length);
1111                                 boffs = free->offset;
1112                         }
1113                         memcpy(oob, chip->oob_poi + boffs, bytes);
1114                         oob += bytes;
1115                 }
1116                 return oob;
1117         }
1118         default:
1119                 BUG();
1120         }
1121         return NULL;
1122 }
1123
1124 /**
1125  * nand_do_read_ops - [Internal] Read data with ECC
1126  *
1127  * @mtd:        MTD device structure
1128  * @from:       offset to read from
1129  * @ops:        oob ops structure
1130  *
1131  * Internal function. Called with chip held.
1132  */
1133 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1134                             struct mtd_oob_ops *ops)
1135 {
1136         int chipnr, page, realpage, col, bytes, aligned;
1137         struct nand_chip *chip = mtd->priv;
1138         struct mtd_ecc_stats stats;
1139         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1140         int sndcmd = 1;
1141         int ret = 0;
1142         uint32_t readlen = ops->len;
1143         uint32_t oobreadlen = ops->ooblen;
1144         uint8_t *bufpoi, *oob, *buf;
1145
1146         stats = mtd->ecc_stats;
1147
1148         chipnr = (int)(from >> chip->chip_shift);
1149         chip->select_chip(mtd, chipnr);
1150
1151         realpage = (int)(from >> chip->page_shift);
1152         page = realpage & chip->pagemask;
1153
1154         col = (int)(from & (mtd->writesize - 1));
1155
1156         buf = ops->datbuf;
1157         oob = ops->oobbuf;
1158
1159         while(1) {
1160                 WATCHDOG_RESET();
1161
1162                 bytes = min(mtd->writesize - col, readlen);
1163                 aligned = (bytes == mtd->writesize);
1164
1165                 /* Is the current page in the buffer ? */
1166                 if (realpage != chip->pagebuf || oob) {
1167                         bufpoi = aligned ? buf : chip->buffers->databuf;
1168
1169                         if (likely(sndcmd)) {
1170                                 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1171                                 sndcmd = 0;
1172                         }
1173
1174                         /* Now read the page into the buffer */
1175                         if (unlikely(ops->mode == MTD_OOB_RAW))
1176                                 ret = chip->ecc.read_page_raw(mtd, chip,
1177                                                 bufpoi, page);
1178                         else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1179                                 ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi);
1180                         else
1181                                 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1182                                                 page);
1183                         if (ret < 0)
1184                                 break;
1185
1186                         /* Transfer not aligned data */
1187                         if (!aligned) {
1188                                 if (!NAND_SUBPAGE_READ(chip) && !oob)
1189                                         chip->pagebuf = realpage;
1190                                 memcpy(buf, chip->buffers->databuf + col, bytes);
1191                         }
1192
1193                         buf += bytes;
1194
1195                         if (unlikely(oob)) {
1196                                 /* Raw mode does data:oob:data:oob */
1197                                 if (ops->mode != MTD_OOB_RAW) {
1198                                         int toread = min(oobreadlen,
1199                                                 chip->ecc.layout->oobavail);
1200                                         if (toread) {
1201                                                 oob = nand_transfer_oob(chip,
1202                                                         oob, ops, toread);
1203                                                 oobreadlen -= toread;
1204                                         }
1205                                 } else
1206                                         buf = nand_transfer_oob(chip,
1207                                                 buf, ops, mtd->oobsize);
1208                         }
1209
1210                         if (!(chip->options & NAND_NO_READRDY)) {
1211                                 /*
1212                                  * Apply delay or wait for ready/busy pin. Do
1213                                  * this before the AUTOINCR check, so no
1214                                  * problems arise if a chip which does auto
1215                                  * increment is marked as NOAUTOINCR by the
1216                                  * board driver.
1217                                  */
1218                                 if (!chip->dev_ready)
1219                                         udelay(chip->chip_delay);
1220                                 else
1221                                         nand_wait_ready(mtd);
1222                         }
1223                 } else {
1224                         memcpy(buf, chip->buffers->databuf + col, bytes);
1225                         buf += bytes;
1226                 }
1227
1228                 readlen -= bytes;
1229
1230                 if (!readlen)
1231                         break;
1232
1233                 /* For subsequent reads align to page boundary. */
1234                 col = 0;
1235                 /* Increment page address */
1236                 realpage++;
1237
1238                 page = realpage & chip->pagemask;
1239                 /* Check, if we cross a chip boundary */
1240                 if (!page) {
1241                         chipnr++;
1242                         chip->select_chip(mtd, -1);
1243                         chip->select_chip(mtd, chipnr);
1244                 }
1245
1246                 /* Check, if the chip supports auto page increment
1247                  * or if we have hit a block boundary.
1248                  */
1249                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1250                         sndcmd = 1;
1251         }
1252
1253         ops->retlen = ops->len - (size_t) readlen;
1254         if (oob)
1255                 ops->oobretlen = ops->ooblen - oobreadlen;
1256
1257         if (ret)
1258                 return ret;
1259
1260         if (mtd->ecc_stats.failed - stats.failed)
1261                 return -EBADMSG;
1262
1263         return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1264 }
1265
1266 /**
1267  * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1268  * @mtd:        MTD device structure
1269  * @from:       offset to read from
1270  * @len:        number of bytes to read
1271  * @retlen:     pointer to variable to store the number of read bytes
1272  * @buf:        the databuffer to put data
1273  *
1274  * Get hold of the chip and call nand_do_read
1275  */
1276 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1277                      size_t *retlen, uint8_t *buf)
1278 {
1279         struct nand_chip *chip = mtd->priv;
1280         int ret;
1281
1282         /* Do not allow reads past end of device */
1283         if ((from + len) > mtd->size)
1284                 return -EINVAL;
1285         if (!len)
1286                 return 0;
1287
1288         nand_get_device(chip, mtd, FL_READING);
1289
1290         chip->ops.len = len;
1291         chip->ops.datbuf = buf;
1292         chip->ops.oobbuf = NULL;
1293
1294         ret = nand_do_read_ops(mtd, from, &chip->ops);
1295
1296         *retlen = chip->ops.retlen;
1297
1298         nand_release_device(mtd);
1299
1300         return ret;
1301 }
1302
1303 /**
1304  * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1305  * @mtd:        mtd info structure
1306  * @chip:       nand chip info structure
1307  * @page:       page number to read
1308  * @sndcmd:     flag whether to issue read command or not
1309  */
1310 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1311                              int page, int sndcmd)
1312 {
1313         if (sndcmd) {
1314                 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1315                 sndcmd = 0;
1316         }
1317         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1318         return sndcmd;
1319 }
1320
1321 /**
1322  * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1323  *                          with syndromes
1324  * @mtd:        mtd info structure
1325  * @chip:       nand chip info structure
1326  * @page:       page number to read
1327  * @sndcmd:     flag whether to issue read command or not
1328  */
1329 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1330                                   int page, int sndcmd)
1331 {
1332         uint8_t *buf = chip->oob_poi;
1333         int length = mtd->oobsize;
1334         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1335         int eccsize = chip->ecc.size;
1336         uint8_t *bufpoi = buf;
1337         int i, toread, sndrnd = 0, pos;
1338
1339         chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1340         for (i = 0; i < chip->ecc.steps; i++) {
1341                 if (sndrnd) {
1342                         pos = eccsize + i * (eccsize + chunk);
1343                         if (mtd->writesize > 512)
1344                                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1345                         else
1346                                 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1347                 } else
1348                         sndrnd = 1;
1349                 toread = min_t(int, length, chunk);
1350                 chip->read_buf(mtd, bufpoi, toread);
1351                 bufpoi += toread;
1352                 length -= toread;
1353         }
1354         if (length > 0)
1355                 chip->read_buf(mtd, bufpoi, length);
1356
1357         return 1;
1358 }
1359
1360 /**
1361  * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1362  * @mtd:        mtd info structure
1363  * @chip:       nand chip info structure
1364  * @page:       page number to write
1365  */
1366 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1367                               int page)
1368 {
1369         int status = 0;
1370         const uint8_t *buf = chip->oob_poi;
1371         int length = mtd->oobsize;
1372
1373         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1374         chip->write_buf(mtd, buf, length);
1375         /* Send command to program the OOB data */
1376         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1377
1378         status = chip->waitfunc(mtd, chip);
1379
1380         return status & NAND_STATUS_FAIL ? -EIO : 0;
1381 }
1382
1383 /**
1384  * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1385  *                           with syndrome - only for large page flash !
1386  * @mtd:        mtd info structure
1387  * @chip:       nand chip info structure
1388  * @page:       page number to write
1389  */
1390 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1391                                    struct nand_chip *chip, int page)
1392 {
1393         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1394         int eccsize = chip->ecc.size, length = mtd->oobsize;
1395         int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1396         const uint8_t *bufpoi = chip->oob_poi;
1397
1398         /*
1399          * data-ecc-data-ecc ... ecc-oob
1400          * or
1401          * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1402          */
1403         if (!chip->ecc.prepad && !chip->ecc.postpad) {
1404                 pos = steps * (eccsize + chunk);
1405                 steps = 0;
1406         } else
1407                 pos = eccsize;
1408
1409         chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1410         for (i = 0; i < steps; i++) {
1411                 if (sndcmd) {
1412                         if (mtd->writesize <= 512) {
1413                                 uint32_t fill = 0xFFFFFFFF;
1414
1415                                 len = eccsize;
1416                                 while (len > 0) {
1417                                         int num = min_t(int, len, 4);
1418                                         chip->write_buf(mtd, (uint8_t *)&fill,
1419                                                         num);
1420                                         len -= num;
1421                                 }
1422                         } else {
1423                                 pos = eccsize + i * (eccsize + chunk);
1424                                 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1425                         }
1426                 } else
1427                         sndcmd = 1;
1428                 len = min_t(int, length, chunk);
1429                 chip->write_buf(mtd, bufpoi, len);
1430                 bufpoi += len;
1431                 length -= len;
1432         }
1433         if (length > 0)
1434                 chip->write_buf(mtd, bufpoi, length);
1435
1436         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1437         status = chip->waitfunc(mtd, chip);
1438
1439         return status & NAND_STATUS_FAIL ? -EIO : 0;
1440 }
1441
1442 /**
1443  * nand_do_read_oob - [Intern] NAND read out-of-band
1444  * @mtd:        MTD device structure
1445  * @from:       offset to read from
1446  * @ops:        oob operations description structure
1447  *
1448  * NAND read out-of-band data from the spare area
1449  */
1450 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1451                             struct mtd_oob_ops *ops)
1452 {
1453         int page, realpage, chipnr, sndcmd = 1;
1454         struct nand_chip *chip = mtd->priv;
1455         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1456         int readlen = ops->ooblen;
1457         int len;
1458         uint8_t *buf = ops->oobbuf;
1459
1460         MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n",
1461                   (unsigned long long)from, readlen);
1462
1463         if (ops->mode == MTD_OOB_AUTO)
1464                 len = chip->ecc.layout->oobavail;
1465         else
1466                 len = mtd->oobsize;
1467
1468         if (unlikely(ops->ooboffs >= len)) {
1469                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1470                           "Attempt to start read outside oob\n");
1471                 return -EINVAL;
1472         }
1473
1474         /* Do not allow reads past end of device */
1475         if (unlikely(from >= mtd->size ||
1476                      ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1477                                         (from >> chip->page_shift)) * len)) {
1478                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1479                           "Attempt read beyond end of device\n");
1480                 return -EINVAL;
1481         }
1482
1483         chipnr = (int)(from >> chip->chip_shift);
1484         chip->select_chip(mtd, chipnr);
1485
1486         /* Shift to get page */
1487         realpage = (int)(from >> chip->page_shift);
1488         page = realpage & chip->pagemask;
1489
1490         while(1) {
1491                 WATCHDOG_RESET();
1492                 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1493
1494                 len = min(len, readlen);
1495                 buf = nand_transfer_oob(chip, buf, ops, len);
1496
1497                 if (!(chip->options & NAND_NO_READRDY)) {
1498                         /*
1499                          * Apply delay or wait for ready/busy pin. Do this
1500                          * before the AUTOINCR check, so no problems arise if a
1501                          * chip which does auto increment is marked as
1502                          * NOAUTOINCR by the board driver.
1503                          */
1504                         if (!chip->dev_ready)
1505                                 udelay(chip->chip_delay);
1506                         else
1507                                 nand_wait_ready(mtd);
1508                 }
1509
1510                 readlen -= len;
1511                 if (!readlen)
1512                         break;
1513
1514                 /* Increment page address */
1515                 realpage++;
1516
1517                 page = realpage & chip->pagemask;
1518                 /* Check, if we cross a chip boundary */
1519                 if (!page) {
1520                         chipnr++;
1521                         chip->select_chip(mtd, -1);
1522                         chip->select_chip(mtd, chipnr);
1523                 }
1524
1525                 /* Check, if the chip supports auto page increment
1526                  * or if we have hit a block boundary.
1527                  */
1528                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1529                         sndcmd = 1;
1530         }
1531
1532         ops->oobretlen = ops->ooblen;
1533         return 0;
1534 }
1535
1536 /**
1537  * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1538  * @mtd:        MTD device structure
1539  * @from:       offset to read from
1540  * @ops:        oob operation description structure
1541  *
1542  * NAND read data and/or out-of-band data
1543  */
1544 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1545                          struct mtd_oob_ops *ops)
1546 {
1547         struct nand_chip *chip = mtd->priv;
1548         int ret = -ENOTSUPP;
1549
1550         ops->retlen = 0;
1551
1552         /* Do not allow reads past end of device */
1553         if (ops->datbuf && (from + ops->len) > mtd->size) {
1554                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1555                           "Attempt read beyond end of device\n");
1556                 return -EINVAL;
1557         }
1558
1559         nand_get_device(chip, mtd, FL_READING);
1560
1561         switch(ops->mode) {
1562         case MTD_OOB_PLACE:
1563         case MTD_OOB_AUTO:
1564         case MTD_OOB_RAW:
1565                 break;
1566
1567         default:
1568                 goto out;
1569         }
1570
1571         if (!ops->datbuf)
1572                 ret = nand_do_read_oob(mtd, from, ops);
1573         else
1574                 ret = nand_do_read_ops(mtd, from, ops);
1575
1576  out:
1577         nand_release_device(mtd);
1578         return ret;
1579 }
1580
1581
1582 /**
1583  * nand_write_page_raw - [Intern] raw page write function
1584  * @mtd:        mtd info structure
1585  * @chip:       nand chip info structure
1586  * @buf:        data buffer
1587  *
1588  * Not for syndrome calculating ecc controllers, which use a special oob layout
1589  */
1590 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1591                                 const uint8_t *buf)
1592 {
1593         chip->write_buf(mtd, buf, mtd->writesize);
1594         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1595 }
1596
1597 /**
1598  * nand_write_page_raw_syndrome - [Intern] raw page write function
1599  * @mtd:        mtd info structure
1600  * @chip:       nand chip info structure
1601  * @buf:        data buffer
1602  *
1603  * We need a special oob layout and handling even when ECC isn't checked.
1604  */
1605 static void nand_write_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1606                                 const uint8_t *buf)
1607 {
1608         int eccsize = chip->ecc.size;
1609         int eccbytes = chip->ecc.bytes;
1610         uint8_t *oob = chip->oob_poi;
1611         int steps, size;
1612
1613         for (steps = chip->ecc.steps; steps > 0; steps--) {
1614                 chip->write_buf(mtd, buf, eccsize);
1615                 buf += eccsize;
1616
1617                 if (chip->ecc.prepad) {
1618                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1619                         oob += chip->ecc.prepad;
1620                 }
1621
1622                 chip->read_buf(mtd, oob, eccbytes);
1623                 oob += eccbytes;
1624
1625                 if (chip->ecc.postpad) {
1626                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1627                         oob += chip->ecc.postpad;
1628                 }
1629         }
1630
1631         size = mtd->oobsize - (oob - chip->oob_poi);
1632         if (size)
1633                 chip->write_buf(mtd, oob, size);
1634 }
1635 /**
1636  * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1637  * @mtd:        mtd info structure
1638  * @chip:       nand chip info structure
1639  * @buf:        data buffer
1640  */
1641 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1642                                   const uint8_t *buf)
1643 {
1644         int i, eccsize = chip->ecc.size;
1645         int eccbytes = chip->ecc.bytes;
1646         int eccsteps = chip->ecc.steps;
1647         uint8_t *ecc_calc = chip->buffers->ecccalc;
1648         const uint8_t *p = buf;
1649         uint32_t *eccpos = chip->ecc.layout->eccpos;
1650
1651         /* Software ecc calculation */
1652         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1653                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1654
1655         for (i = 0; i < chip->ecc.total; i++)
1656                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1657
1658         chip->ecc.write_page_raw(mtd, chip, buf);
1659 }
1660
1661 /**
1662  * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1663  * @mtd:        mtd info structure
1664  * @chip:       nand chip info structure
1665  * @buf:        data buffer
1666  */
1667 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1668                                   const uint8_t *buf)
1669 {
1670         int i, eccsize = chip->ecc.size;
1671         int eccbytes = chip->ecc.bytes;
1672         int eccsteps = chip->ecc.steps;
1673         uint8_t *ecc_calc = chip->buffers->ecccalc;
1674         const uint8_t *p = buf;
1675         uint32_t *eccpos = chip->ecc.layout->eccpos;
1676
1677         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1678                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1679                 chip->write_buf(mtd, p, eccsize);
1680                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1681         }
1682
1683         for (i = 0; i < chip->ecc.total; i++)
1684                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1685
1686         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1687 }
1688
1689 /**
1690  * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1691  * @mtd:        mtd info structure
1692  * @chip:       nand chip info structure
1693  * @buf:        data buffer
1694  *
1695  * The hw generator calculates the error syndrome automatically. Therefor
1696  * we need a special oob layout and handling.
1697  */
1698 static void nand_write_page_syndrome(struct mtd_info *mtd,
1699                                     struct nand_chip *chip, const uint8_t *buf)
1700 {
1701         int i, eccsize = chip->ecc.size;
1702         int eccbytes = chip->ecc.bytes;
1703         int eccsteps = chip->ecc.steps;
1704         const uint8_t *p = buf;
1705         uint8_t *oob = chip->oob_poi;
1706
1707         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1708
1709                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1710                 chip->write_buf(mtd, p, eccsize);
1711
1712                 if (chip->ecc.prepad) {
1713                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1714                         oob += chip->ecc.prepad;
1715                 }
1716
1717                 chip->ecc.calculate(mtd, p, oob);
1718                 chip->write_buf(mtd, oob, eccbytes);
1719                 oob += eccbytes;
1720
1721                 if (chip->ecc.postpad) {
1722                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1723                         oob += chip->ecc.postpad;
1724                 }
1725         }
1726
1727         /* Calculate remaining oob bytes */
1728         i = mtd->oobsize - (oob - chip->oob_poi);
1729         if (i)
1730                 chip->write_buf(mtd, oob, i);
1731 }
1732
1733 /**
1734  * nand_write_page - [REPLACEABLE] write one page
1735  * @mtd:        MTD device structure
1736  * @chip:       NAND chip descriptor
1737  * @buf:        the data to write
1738  * @page:       page number to write
1739  * @cached:     cached programming
1740  * @raw:        use _raw version of write_page
1741  */
1742 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1743                            const uint8_t *buf, int page, int cached, int raw)
1744 {
1745         int status;
1746
1747         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1748
1749         if (unlikely(raw))
1750                 chip->ecc.write_page_raw(mtd, chip, buf);
1751         else
1752                 chip->ecc.write_page(mtd, chip, buf);
1753
1754         /*
1755          * Cached progamming disabled for now, Not sure if its worth the
1756          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1757          */
1758         cached = 0;
1759
1760         if (!cached || !(chip->options & NAND_CACHEPRG)) {
1761
1762                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1763                 status = chip->waitfunc(mtd, chip);
1764                 /*
1765                  * See if operation failed and additional status checks are
1766                  * available
1767                  */
1768                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1769                         status = chip->errstat(mtd, chip, FL_WRITING, status,
1770                                                page);
1771
1772                 if (status & NAND_STATUS_FAIL)
1773                         return -EIO;
1774         } else {
1775                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1776                 status = chip->waitfunc(mtd, chip);
1777         }
1778
1779 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1780         /* Send command to read back the data */
1781         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1782
1783         if (chip->verify_buf(mtd, buf, mtd->writesize))
1784                 return -EIO;
1785 #endif
1786         return 0;
1787 }
1788
1789 /**
1790  * nand_fill_oob - [Internal] Transfer client buffer to oob
1791  * @chip:       nand chip structure
1792  * @oob:        oob data buffer
1793  * @ops:        oob ops structure
1794  */
1795 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
1796                                   struct mtd_oob_ops *ops)
1797 {
1798         size_t len = ops->ooblen;
1799
1800         switch(ops->mode) {
1801
1802         case MTD_OOB_PLACE:
1803         case MTD_OOB_RAW:
1804                 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1805                 return oob + len;
1806
1807         case MTD_OOB_AUTO: {
1808                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1809                 uint32_t boffs = 0, woffs = ops->ooboffs;
1810                 size_t bytes = 0;
1811
1812                 for(; free->length && len; free++, len -= bytes) {
1813                         /* Write request not from offset 0 ? */
1814                         if (unlikely(woffs)) {
1815                                 if (woffs >= free->length) {
1816                                         woffs -= free->length;
1817                                         continue;
1818                                 }
1819                                 boffs = free->offset + woffs;
1820                                 bytes = min_t(size_t, len,
1821                                               (free->length - woffs));
1822                                 woffs = 0;
1823                         } else {
1824                                 bytes = min_t(size_t, len, free->length);
1825                                 boffs = free->offset;
1826                         }
1827                         memcpy(chip->oob_poi + boffs, oob, bytes);
1828                         oob += bytes;
1829                 }
1830                 return oob;
1831         }
1832         default:
1833                 BUG();
1834         }
1835         return NULL;
1836 }
1837
1838 #define NOTALIGNED(x)   (x & (chip->subpagesize - 1)) != 0
1839
1840 /**
1841  * nand_do_write_ops - [Internal] NAND write with ECC
1842  * @mtd:        MTD device structure
1843  * @to:         offset to write to
1844  * @ops:        oob operations description structure
1845  *
1846  * NAND write with ECC
1847  */
1848 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1849                              struct mtd_oob_ops *ops)
1850 {
1851         int chipnr, realpage, page, blockmask, column;
1852         struct nand_chip *chip = mtd->priv;
1853         uint32_t writelen = ops->len;
1854         uint8_t *oob = ops->oobbuf;
1855         uint8_t *buf = ops->datbuf;
1856         int ret, subpage;
1857
1858         ops->retlen = 0;
1859         if (!writelen)
1860                 return 0;
1861
1862         column = to & (mtd->writesize - 1);
1863         subpage = column || (writelen & (mtd->writesize - 1));
1864
1865         if (subpage && oob)
1866                 return -EINVAL;
1867
1868         chipnr = (int)(to >> chip->chip_shift);
1869         chip->select_chip(mtd, chipnr);
1870
1871         /* Check, if it is write protected */
1872         if (nand_check_wp(mtd)) {
1873                 printk (KERN_NOTICE "nand_do_write_ops: Device is write protected\n");
1874                 return -EIO;
1875         }
1876
1877         realpage = (int)(to >> chip->page_shift);
1878         page = realpage & chip->pagemask;
1879         blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1880
1881         /* Invalidate the page cache, when we write to the cached page */
1882         if (to <= (chip->pagebuf << chip->page_shift) &&
1883             (chip->pagebuf << chip->page_shift) < (to + ops->len))
1884                 chip->pagebuf = -1;
1885
1886         /* If we're not given explicit OOB data, let it be 0xFF */
1887         if (likely(!oob))
1888                 memset(chip->oob_poi, 0xff, mtd->oobsize);
1889
1890         while(1) {
1891                 WATCHDOG_RESET();
1892
1893                 int bytes = mtd->writesize;
1894                 int cached = writelen > bytes && page != blockmask;
1895                 uint8_t *wbuf = buf;
1896
1897                 /* Partial page write ? */
1898                 if (unlikely(column || writelen < (mtd->writesize - 1))) {
1899                         cached = 0;
1900                         bytes = min_t(int, bytes - column, (int) writelen);
1901                         chip->pagebuf = -1;
1902                         memset(chip->buffers->databuf, 0xff, mtd->writesize);
1903                         memcpy(&chip->buffers->databuf[column], buf, bytes);
1904                         wbuf = chip->buffers->databuf;
1905                 }
1906
1907                 if (unlikely(oob))
1908                         oob = nand_fill_oob(chip, oob, ops);
1909
1910                 ret = chip->write_page(mtd, chip, wbuf, page, cached,
1911                                        (ops->mode == MTD_OOB_RAW));
1912                 if (ret)
1913                         break;
1914
1915                 writelen -= bytes;
1916                 if (!writelen)
1917                         break;
1918
1919                 column = 0;
1920                 buf += bytes;
1921                 realpage++;
1922
1923                 page = realpage & chip->pagemask;
1924                 /* Check, if we cross a chip boundary */
1925                 if (!page) {
1926                         chipnr++;
1927                         chip->select_chip(mtd, -1);
1928                         chip->select_chip(mtd, chipnr);
1929                 }
1930         }
1931
1932         ops->retlen = ops->len - writelen;
1933         if (unlikely(oob))
1934                 ops->oobretlen = ops->ooblen;
1935         return ret;
1936 }
1937
1938 /**
1939  * nand_write - [MTD Interface] NAND write with ECC
1940  * @mtd:        MTD device structure
1941  * @to:         offset to write to
1942  * @len:        number of bytes to write
1943  * @retlen:     pointer to variable to store the number of written bytes
1944  * @buf:        the data to write
1945  *
1946  * NAND write with ECC
1947  */
1948 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
1949                           size_t *retlen, const uint8_t *buf)
1950 {
1951         struct nand_chip *chip = mtd->priv;
1952         int ret;
1953
1954         /* Do not allow writes past end of device */
1955         if ((to + len) > mtd->size)
1956                 return -EINVAL;
1957         if (!len)
1958                 return 0;
1959
1960         nand_get_device(chip, mtd, FL_WRITING);
1961
1962         chip->ops.len = len;
1963         chip->ops.datbuf = (uint8_t *)buf;
1964         chip->ops.oobbuf = NULL;
1965
1966         ret = nand_do_write_ops(mtd, to, &chip->ops);
1967
1968         *retlen = chip->ops.retlen;
1969
1970         nand_release_device(mtd);
1971
1972         return ret;
1973 }
1974
1975 /**
1976  * nand_do_write_oob - [MTD Interface] NAND write out-of-band
1977  * @mtd:        MTD device structure
1978  * @to:         offset to write to
1979  * @ops:        oob operation description structure
1980  *
1981  * NAND write out-of-band
1982  */
1983 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
1984                              struct mtd_oob_ops *ops)
1985 {
1986         int chipnr, page, status, len;
1987         struct nand_chip *chip = mtd->priv;
1988
1989         MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n",
1990                   (unsigned int)to, (int)ops->ooblen);
1991
1992         if (ops->mode == MTD_OOB_AUTO)
1993                 len = chip->ecc.layout->oobavail;
1994         else
1995                 len = mtd->oobsize;
1996
1997         /* Do not allow write past end of page */
1998         if ((ops->ooboffs + ops->ooblen) > len) {
1999                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: "
2000                           "Attempt to write past end of page\n");
2001                 return -EINVAL;
2002         }
2003
2004         if (unlikely(ops->ooboffs >= len)) {
2005                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2006                           "Attempt to start write outside oob\n");
2007                 return -EINVAL;
2008         }
2009
2010         /* Do not allow reads past end of device */
2011         if (unlikely(to >= mtd->size ||
2012                      ops->ooboffs + ops->ooblen >
2013                         ((mtd->size >> chip->page_shift) -
2014                          (to >> chip->page_shift)) * len)) {
2015                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2016                           "Attempt write beyond end of device\n");
2017                 return -EINVAL;
2018         }
2019
2020         chipnr = (int)(to >> chip->chip_shift);
2021         chip->select_chip(mtd, chipnr);
2022
2023         /* Shift to get page */
2024         page = (int)(to >> chip->page_shift);
2025
2026         /*
2027          * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2028          * of my DiskOnChip 2000 test units) will clear the whole data page too
2029          * if we don't do this. I have no clue why, but I seem to have 'fixed'
2030          * it in the doc2000 driver in August 1999.  dwmw2.
2031          */
2032         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2033
2034         /* Check, if it is write protected */
2035         if (nand_check_wp(mtd))
2036                 return -EROFS;
2037
2038         /* Invalidate the page cache, if we write to the cached page */
2039         if (page == chip->pagebuf)
2040                 chip->pagebuf = -1;
2041
2042         memset(chip->oob_poi, 0xff, mtd->oobsize);
2043         nand_fill_oob(chip, ops->oobbuf, ops);
2044         status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2045         memset(chip->oob_poi, 0xff, mtd->oobsize);
2046
2047         if (status)
2048                 return status;
2049
2050         ops->oobretlen = ops->ooblen;
2051
2052         return 0;
2053 }
2054
2055 /**
2056  * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2057  * @mtd:        MTD device structure
2058  * @to:         offset to write to
2059  * @ops:        oob operation description structure
2060  */
2061 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2062                           struct mtd_oob_ops *ops)
2063 {
2064         struct nand_chip *chip = mtd->priv;
2065         int ret = -ENOTSUPP;
2066
2067         ops->retlen = 0;
2068
2069         /* Do not allow writes past end of device */
2070         if (ops->datbuf && (to + ops->len) > mtd->size) {
2071                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2072                           "Attempt read beyond end of device\n");
2073                 return -EINVAL;
2074         }
2075
2076         nand_get_device(chip, mtd, FL_WRITING);
2077
2078         switch(ops->mode) {
2079         case MTD_OOB_PLACE:
2080         case MTD_OOB_AUTO:
2081         case MTD_OOB_RAW:
2082                 break;
2083
2084         default:
2085                 goto out;
2086         }
2087
2088         if (!ops->datbuf)
2089                 ret = nand_do_write_oob(mtd, to, ops);
2090         else
2091                 ret = nand_do_write_ops(mtd, to, ops);
2092
2093  out:
2094         nand_release_device(mtd);
2095         return ret;
2096 }
2097
2098 /**
2099  * single_erease_cmd - [GENERIC] NAND standard block erase command function
2100  * @mtd:        MTD device structure
2101  * @page:       the page address of the block which will be erased
2102  *
2103  * Standard erase command for NAND chips
2104  */
2105 static void single_erase_cmd(struct mtd_info *mtd, int page)
2106 {
2107         struct nand_chip *chip = mtd->priv;
2108         /* Send commands to erase a block */
2109         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2110         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2111 }
2112
2113 /**
2114  * multi_erease_cmd - [GENERIC] AND specific block erase command function
2115  * @mtd:        MTD device structure
2116  * @page:       the page address of the block which will be erased
2117  *
2118  * AND multi block erase command function
2119  * Erase 4 consecutive blocks
2120  */
2121 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2122 {
2123         struct nand_chip *chip = mtd->priv;
2124         /* Send commands to erase a block */
2125         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2126         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2127         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2128         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2129         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2130 }
2131
2132 /**
2133  * nand_erase - [MTD Interface] erase block(s)
2134  * @mtd:        MTD device structure
2135  * @instr:      erase instruction
2136  *
2137  * Erase one ore more blocks
2138  */
2139 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2140 {
2141         return nand_erase_nand(mtd, instr, 0);
2142 }
2143
2144 #define BBT_PAGE_MASK   0xffffff3f
2145 /**
2146  * nand_erase_nand - [Internal] erase block(s)
2147  * @mtd:        MTD device structure
2148  * @instr:      erase instruction
2149  * @allowbbt:   allow erasing the bbt area
2150  *
2151  * Erase one ore more blocks
2152  */
2153 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2154                     int allowbbt)
2155 {
2156         int page, status, pages_per_block, ret, chipnr;
2157         struct nand_chip *chip = mtd->priv;
2158         loff_t rewrite_bbt[CONFIG_SYS_NAND_MAX_CHIPS] = {0};
2159         unsigned int bbt_masked_page = 0xffffffff;
2160         loff_t len;
2161
2162         MTDDEBUG(MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%012llx, "
2163                  "len = %llu\n", (unsigned long long) instr->addr,
2164                  (unsigned long long) instr->len);
2165
2166         /* Start address must align on block boundary */
2167         if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
2168                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
2169                 return -EINVAL;
2170         }
2171
2172         /* Length must align on block boundary */
2173         if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
2174                 MTDDEBUG (MTD_DEBUG_LEVEL0,
2175                           "nand_erase: Length not block aligned\n");
2176                 return -EINVAL;
2177         }
2178
2179         /* Do not allow erase past end of device */
2180         if ((instr->len + instr->addr) > mtd->size) {
2181                 MTDDEBUG (MTD_DEBUG_LEVEL0,
2182                           "nand_erase: Erase past end of device\n");
2183                 return -EINVAL;
2184         }
2185
2186         instr->fail_addr = 0xffffffff;
2187
2188         /* Grab the lock and see if the device is available */
2189         nand_get_device(chip, mtd, FL_ERASING);
2190
2191         /* Shift to get first page */
2192         page = (int)(instr->addr >> chip->page_shift);
2193         chipnr = (int)(instr->addr >> chip->chip_shift);
2194
2195         /* Calculate pages in each block */
2196         pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2197
2198         /* Select the NAND device */
2199         chip->select_chip(mtd, chipnr);
2200
2201         /* Check, if it is write protected */
2202         if (nand_check_wp(mtd)) {
2203                 MTDDEBUG (MTD_DEBUG_LEVEL0,
2204                           "nand_erase: Device is write protected!!!\n");
2205                 instr->state = MTD_ERASE_FAILED;
2206                 goto erase_exit;
2207         }
2208
2209         /*
2210          * If BBT requires refresh, set the BBT page mask to see if the BBT
2211          * should be rewritten. Otherwise the mask is set to 0xffffffff which
2212          * can not be matched. This is also done when the bbt is actually
2213          * erased to avoid recusrsive updates
2214          */
2215         if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2216                 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2217
2218         /* Loop through the pages */
2219         len = instr->len;
2220
2221         instr->state = MTD_ERASING;
2222
2223         while (len) {
2224                 WATCHDOG_RESET();
2225                 /*
2226                  * heck if we have a bad block, we do not erase bad blocks !
2227                  */
2228                 if (!instr->scrub && nand_block_checkbad(mtd, ((loff_t) page) <<
2229                                         chip->page_shift, 0, allowbbt)) {
2230                         printk(KERN_WARNING "nand_erase: attempt to erase a "
2231                                "bad block at page 0x%08x\n", page);
2232                         instr->state = MTD_ERASE_FAILED;
2233                         goto erase_exit;
2234                 }
2235
2236                 /*
2237                  * Invalidate the page cache, if we erase the block which
2238                  * contains the current cached page
2239                  */
2240                 if (page <= chip->pagebuf && chip->pagebuf <
2241                     (page + pages_per_block))
2242                         chip->pagebuf = -1;
2243
2244                 chip->erase_cmd(mtd, page & chip->pagemask);
2245
2246                 status = chip->waitfunc(mtd, chip);
2247
2248                 /*
2249                  * See if operation failed and additional status checks are
2250                  * available
2251                  */
2252                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2253                         status = chip->errstat(mtd, chip, FL_ERASING,
2254                                                status, page);
2255
2256                 /* See if block erase succeeded */
2257                 if (status & NAND_STATUS_FAIL) {
2258                         MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: "
2259                                   "Failed erase, page 0x%08x\n", page);
2260                         instr->state = MTD_ERASE_FAILED;
2261                         instr->fail_addr = ((loff_t)page << chip->page_shift);
2262                         goto erase_exit;
2263                 }
2264
2265                 /*
2266                  * If BBT requires refresh, set the BBT rewrite flag to the
2267                  * page being erased
2268                  */
2269                 if (bbt_masked_page != 0xffffffff &&
2270                     (page & BBT_PAGE_MASK) == bbt_masked_page)
2271                         rewrite_bbt[chipnr] =
2272                                 ((loff_t)page << chip->page_shift);
2273
2274                 /* Increment page address and decrement length */
2275                 len -= (1 << chip->phys_erase_shift);
2276                 page += pages_per_block;
2277
2278                 /* Check, if we cross a chip boundary */
2279                 if (len && !(page & chip->pagemask)) {
2280                         chipnr++;
2281                         chip->select_chip(mtd, -1);
2282                         chip->select_chip(mtd, chipnr);
2283
2284                         /*
2285                          * If BBT requires refresh and BBT-PERCHIP, set the BBT
2286                          * page mask to see if this BBT should be rewritten
2287                          */
2288                         if (bbt_masked_page != 0xffffffff &&
2289                             (chip->bbt_td->options & NAND_BBT_PERCHIP))
2290                                 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2291                                         BBT_PAGE_MASK;
2292                 }
2293         }
2294         instr->state = MTD_ERASE_DONE;
2295
2296  erase_exit:
2297
2298         ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2299
2300         /* Deselect and wake up anyone waiting on the device */
2301         nand_release_device(mtd);
2302
2303         /* Do call back function */
2304         if (!ret)
2305                 mtd_erase_callback(instr);
2306
2307         /*
2308          * If BBT requires refresh and erase was successful, rewrite any
2309          * selected bad block tables
2310          */
2311         if (bbt_masked_page == 0xffffffff || ret)
2312                 return ret;
2313
2314         for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2315                 if (!rewrite_bbt[chipnr])
2316                         continue;
2317                 /* update the BBT for chip */
2318                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
2319                           "(%d:0x%0llx 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
2320                           chip->bbt_td->pages[chipnr]);
2321                 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2322         }
2323
2324         /* Return more or less happy */
2325         return ret;
2326 }
2327
2328 /**
2329  * nand_sync - [MTD Interface] sync
2330  * @mtd:        MTD device structure
2331  *
2332  * Sync is actually a wait for chip ready function
2333  */
2334 static void nand_sync(struct mtd_info *mtd)
2335 {
2336         struct nand_chip *chip = mtd->priv;
2337
2338         MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_sync: called\n");
2339
2340         /* Grab the lock and see if the device is available */
2341         nand_get_device(chip, mtd, FL_SYNCING);
2342         /* Release it and go back */
2343         nand_release_device(mtd);
2344 }
2345
2346 /**
2347  * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2348  * @mtd:        MTD device structure
2349  * @offs:       offset relative to mtd start
2350  */
2351 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2352 {
2353         /* Check for invalid offset */
2354         if (offs > mtd->size)
2355                 return -EINVAL;
2356
2357         return nand_block_checkbad(mtd, offs, 1, 0);
2358 }
2359
2360 /**
2361  * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2362  * @mtd:        MTD device structure
2363  * @ofs:        offset relative to mtd start
2364  */
2365 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2366 {
2367         struct nand_chip *chip = mtd->priv;
2368         int ret;
2369
2370         if ((ret = nand_block_isbad(mtd, ofs))) {
2371                 /* If it was bad already, return success and do nothing. */
2372                 if (ret > 0)
2373                         return 0;
2374                 return ret;
2375         }
2376
2377         return chip->block_markbad(mtd, ofs);
2378 }
2379
2380 /*
2381  * Set default functions
2382  */
2383 static void nand_set_defaults(struct nand_chip *chip, int busw)
2384 {
2385         /* check for proper chip_delay setup, set 20us if not */
2386         if (!chip->chip_delay)
2387                 chip->chip_delay = 20;
2388
2389         /* check, if a user supplied command function given */
2390         if (chip->cmdfunc == NULL)
2391                 chip->cmdfunc = nand_command;
2392
2393         /* check, if a user supplied wait function given */
2394         if (chip->waitfunc == NULL)
2395                 chip->waitfunc = nand_wait;
2396
2397         if (!chip->select_chip)
2398                 chip->select_chip = nand_select_chip;
2399         if (!chip->read_byte)
2400                 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2401         if (!chip->read_word)
2402                 chip->read_word = nand_read_word;
2403         if (!chip->block_bad)
2404                 chip->block_bad = nand_block_bad;
2405         if (!chip->block_markbad)
2406                 chip->block_markbad = nand_default_block_markbad;
2407         if (!chip->write_buf)
2408                 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2409         if (!chip->read_buf)
2410                 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2411         if (!chip->verify_buf)
2412                 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2413         if (!chip->scan_bbt)
2414                 chip->scan_bbt = nand_default_bbt;
2415         if (!chip->controller)
2416                 chip->controller = &chip->hwcontrol;
2417 }
2418
2419 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
2420 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2421 {
2422         int i;
2423
2424         while (len--) {
2425                 crc ^= *p++ << 8;
2426                 for (i = 0; i < 8; i++)
2427                         crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2428         }
2429
2430         return crc;
2431 }
2432
2433 /*
2434  * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise
2435  */
2436 static int nand_flash_detect_onfi(struct mtd_info *mtd,
2437                                         struct nand_chip *chip,
2438                                         int *busw)
2439 {
2440         struct nand_onfi_params *p = &chip->onfi_params;
2441         int i;
2442         int val;
2443
2444         chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2445         if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2446                 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2447                 return 0;
2448
2449         printk(KERN_INFO "ONFI flash detected\n");
2450         chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2451         for (i = 0; i < 3; i++) {
2452                 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2453                 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2454                                                 le16_to_cpu(p->crc)) {
2455                         printk(KERN_INFO "ONFI param page %d valid\n", i);
2456                         break;
2457                 }
2458         }
2459
2460         if (i == 3)
2461                 return 0;
2462
2463         /* check version */
2464         val = le16_to_cpu(p->revision);
2465         if (val & (1 << 5))
2466                 chip->onfi_version = 23;
2467         else if (val & (1 << 4))
2468                 chip->onfi_version = 22;
2469         else if (val & (1 << 3))
2470                 chip->onfi_version = 21;
2471         else if (val & (1 << 2))
2472                 chip->onfi_version = 20;
2473         else if (val & (1 << 1))
2474                 chip->onfi_version = 10;
2475         else
2476                 chip->onfi_version = 0;
2477
2478         if (!chip->onfi_version) {
2479                 printk(KERN_INFO "%s: unsupported ONFI "
2480                                         "version: %d\n", __func__, val);
2481                 return 0;
2482         }
2483
2484         if (!mtd->name)
2485                 mtd->name = p->model;
2486
2487         mtd->writesize = le32_to_cpu(p->byte_per_page);
2488         mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2489         mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
2490         chip->chipsize = (uint64_t)le32_to_cpu(p->blocks_per_lun) * mtd->erasesize;
2491         *busw = 0;
2492         if (le16_to_cpu(p->features) & 1)
2493                 *busw = NAND_BUSWIDTH_16;
2494
2495         return 1;
2496 }
2497 #else
2498 static inline int nand_flash_detect_onfi(struct mtd_info *mtd,
2499                                         struct nand_chip *chip,
2500                                         int *busw)
2501 {
2502         return 0;
2503 }
2504 #endif
2505
2506 static void nand_flash_detect_non_onfi(struct mtd_info *mtd,
2507                                         struct nand_chip *chip,
2508                                         const struct nand_flash_dev *type,
2509                                         int *busw)
2510 {
2511         /* Newer devices have all the information in additional id bytes */
2512         if (!type->pagesize) {
2513                 int extid;
2514                 /* The 3rd id byte holds MLC / multichip data */
2515                 chip->cellinfo = chip->read_byte(mtd);
2516                 /* The 4th id byte is the important one */
2517                 extid = chip->read_byte(mtd);
2518                 /* Calc pagesize */
2519                 mtd->writesize = 1024 << (extid & 0x3);
2520                 extid >>= 2;
2521                 /* Calc oobsize */
2522                 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
2523                 extid >>= 2;
2524                 /* Calc blocksize. Blocksize is multiples of 64KiB */
2525                 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2526                 extid >>= 2;
2527                 /* Get buswidth information */
2528                 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2529
2530         } else {
2531                 /*
2532                  * Old devices have chip data hardcoded in the device id table
2533                  */
2534                 mtd->erasesize = type->erasesize;
2535                 mtd->writesize = type->pagesize;
2536                 mtd->oobsize = mtd->writesize / 32;
2537                 *busw = type->options & NAND_BUSWIDTH_16;
2538         }
2539 }
2540
2541 /*
2542  * Get the flash and manufacturer id and lookup if the type is supported
2543  */
2544 static const struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2545                                                   struct nand_chip *chip,
2546                                                   int busw,
2547                                                   int *maf_id, int *dev_id,
2548                                                   const struct nand_flash_dev *type)
2549 {
2550         int ret, maf_idx;
2551         int tmp_id, tmp_manf;
2552
2553         /* Select the device */
2554         chip->select_chip(mtd, 0);
2555
2556         /*
2557          * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2558          * after power-up
2559          */
2560         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2561
2562         /* Send the command for reading device ID */
2563         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2564
2565         /* Read manufacturer and device IDs */
2566         *maf_id = chip->read_byte(mtd);
2567         *dev_id = chip->read_byte(mtd);
2568
2569         /* Try again to make sure, as some systems the bus-hold or other
2570          * interface concerns can cause random data which looks like a
2571          * possibly credible NAND flash to appear. If the two results do
2572          * not match, ignore the device completely.
2573          */
2574
2575         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2576
2577         /* Read manufacturer and device IDs */
2578
2579         tmp_manf = chip->read_byte(mtd);
2580         tmp_id = chip->read_byte(mtd);
2581
2582         if (tmp_manf != *maf_id || tmp_id != *dev_id) {
2583                 printk(KERN_INFO "%s: second ID read did not match "
2584                        "%02x,%02x against %02x,%02x\n", __func__,
2585                        *maf_id, *dev_id, tmp_manf, tmp_id);
2586                 return ERR_PTR(-ENODEV);
2587         }
2588
2589         if (!type)
2590                 type = nand_flash_ids;
2591
2592         for (; type->name != NULL; type++)
2593                 if (*dev_id == type->id)
2594                         break;
2595
2596         if (!type->name) {
2597                 /* supress warning if there is no nand */
2598                 if (*maf_id != 0x00 && *maf_id != 0xff &&
2599                     *dev_id  != 0x00 && *dev_id  != 0xff)
2600                         printk(KERN_INFO "%s: unknown NAND device: "
2601                                 "Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
2602                                 __func__, *maf_id, *dev_id);
2603                 return ERR_PTR(-ENODEV);
2604         }
2605
2606         if (!mtd->name)
2607                 mtd->name = type->name;
2608
2609         chip->chipsize = (uint64_t)type->chipsize << 20;
2610         chip->onfi_version = 0;
2611
2612         ret = nand_flash_detect_onfi(mtd, chip, &busw);
2613         if (!ret)
2614                 nand_flash_detect_non_onfi(mtd, chip, type, &busw);
2615
2616         /* Get chip options, preserve non chip based options */
2617         chip->options &= ~NAND_CHIPOPTIONS_MSK;
2618         chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
2619
2620         /*
2621          * Set chip as a default. Board drivers can override it, if necessary
2622          */
2623         chip->options |= NAND_NO_AUTOINCR;
2624
2625         /* Try to identify manufacturer */
2626         for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2627                 if (nand_manuf_ids[maf_idx].id == *maf_id)
2628                         break;
2629         }
2630
2631         /*
2632          * Check, if buswidth is correct. Hardware drivers should set
2633          * chip correct !
2634          */
2635         if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2636                 printk(KERN_INFO "NAND device: Manufacturer ID:"
2637                        " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2638                        *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2639                 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2640                        (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2641                        busw ? 16 : 8);
2642                 return ERR_PTR(-EINVAL);
2643         }
2644
2645         /* Calculate the address shift from the page size */
2646         chip->page_shift = ffs(mtd->writesize) - 1;
2647         /* Convert chipsize to number of pages per chip -1. */
2648         chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2649
2650         chip->bbt_erase_shift = chip->phys_erase_shift =
2651                 ffs(mtd->erasesize) - 1;
2652         if (chip->chipsize & 0xffffffff)
2653                 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
2654         else
2655                 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)) + 31;
2656
2657         /* Set the bad block position */
2658         chip->badblockpos = mtd->writesize > 512 ?
2659                 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2660
2661         /* Check if chip is a not a samsung device. Do not clear the
2662          * options for chips which are not having an extended id.
2663          */
2664         if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2665                 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2666
2667         /* Check for AND chips with 4 page planes */
2668         if (chip->options & NAND_4PAGE_ARRAY)
2669                 chip->erase_cmd = multi_erase_cmd;
2670         else
2671                 chip->erase_cmd = single_erase_cmd;
2672
2673         /* Do not replace user supplied command function ! */
2674         if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2675                 chip->cmdfunc = nand_command_lp;
2676
2677         MTDDEBUG (MTD_DEBUG_LEVEL0, "NAND device: Manufacturer ID:"
2678                   " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, *dev_id,
2679                   nand_manuf_ids[maf_idx].name, type->name);
2680
2681         return type;
2682 }
2683
2684 /**
2685  * nand_scan_ident - [NAND Interface] Scan for the NAND device
2686  * @mtd:             MTD device structure
2687  * @maxchips:        Number of chips to scan for
2688  * @table:           Alternative NAND ID table
2689  *
2690  * This is the first phase of the normal nand_scan() function. It
2691  * reads the flash ID and sets up MTD fields accordingly.
2692  *
2693  * The mtd->owner field must be set to the module of the caller.
2694  */
2695 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
2696                     const struct nand_flash_dev *table)
2697 {
2698         int i, busw, nand_maf_id, nand_dev_id;
2699         struct nand_chip *chip = mtd->priv;
2700         const struct nand_flash_dev *type;
2701
2702         /* Get buswidth to select the correct functions */
2703         busw = chip->options & NAND_BUSWIDTH_16;
2704         /* Set the default functions */
2705         nand_set_defaults(chip, busw);
2706
2707         /* Read the flash type */
2708         type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id, &nand_dev_id, table);
2709
2710         if (IS_ERR(type)) {
2711 #ifndef CONFIG_SYS_NAND_QUIET_TEST
2712                 printk(KERN_WARNING "No NAND device found!!!\n");
2713 #endif
2714                 chip->select_chip(mtd, -1);
2715                 return PTR_ERR(type);
2716         }
2717
2718         /* Check for a chip array */
2719         for (i = 1; i < maxchips; i++) {
2720                 chip->select_chip(mtd, i);
2721                 /* See comment in nand_get_flash_type for reset */
2722                 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2723                 /* Send the command for reading device ID */
2724                 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2725                 /* Read manufacturer and device IDs */
2726                 if (nand_maf_id != chip->read_byte(mtd) ||
2727                     nand_dev_id != chip->read_byte(mtd))
2728                         break;
2729         }
2730 #ifdef DEBUG
2731         if (i > 1)
2732                 printk(KERN_INFO "%d NAND chips detected\n", i);
2733 #endif
2734
2735         /* Store the number of chips and calc total size for mtd */
2736         chip->numchips = i;
2737         mtd->size = i * chip->chipsize;
2738
2739         return 0;
2740 }
2741
2742
2743 /**
2744  * nand_scan_tail - [NAND Interface] Scan for the NAND device
2745  * @mtd:            MTD device structure
2746  *
2747  * This is the second phase of the normal nand_scan() function. It
2748  * fills out all the uninitialized function pointers with the defaults
2749  * and scans for a bad block table if appropriate.
2750  */
2751 int nand_scan_tail(struct mtd_info *mtd)
2752 {
2753         int i;
2754         struct nand_chip *chip = mtd->priv;
2755
2756         if (!(chip->options & NAND_OWN_BUFFERS))
2757                 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2758         if (!chip->buffers)
2759                 return -ENOMEM;
2760
2761         /* Set the internal oob buffer location, just after the page data */
2762         chip->oob_poi = chip->buffers->databuf + mtd->writesize;
2763
2764         /*
2765          * If no default placement scheme is given, select an appropriate one
2766          */
2767         if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
2768                 switch (mtd->oobsize) {
2769                 case 8:
2770                         chip->ecc.layout = &nand_oob_8;
2771                         break;
2772                 case 16:
2773                         chip->ecc.layout = &nand_oob_16;
2774                         break;
2775                 case 64:
2776                         chip->ecc.layout = &nand_oob_64;
2777                         break;
2778                 case 128:
2779                         chip->ecc.layout = &nand_oob_128;
2780                         break;
2781                 default:
2782                         printk(KERN_WARNING "No oob scheme defined for "
2783                                "oobsize %d\n", mtd->oobsize);
2784                 }
2785         }
2786
2787         if (!chip->write_page)
2788                 chip->write_page = nand_write_page;
2789
2790         /*
2791          * check ECC mode, default to software if 3byte/512byte hardware ECC is
2792          * selected and we have 256 byte pagesize fallback to software ECC
2793          */
2794
2795         switch (chip->ecc.mode) {
2796         case NAND_ECC_HW_OOB_FIRST:
2797                 /* Similar to NAND_ECC_HW, but a separate read_page handle */
2798                 if (!chip->ecc.calculate || !chip->ecc.correct ||
2799                      !chip->ecc.hwctl) {
2800                         printk(KERN_WARNING "No ECC functions supplied, "
2801                                "Hardware ECC not possible\n");
2802                         BUG();
2803                 }
2804                 if (!chip->ecc.read_page)
2805                         chip->ecc.read_page = nand_read_page_hwecc_oob_first;
2806
2807         case NAND_ECC_HW:
2808                 /* Use standard hwecc read page function ? */
2809                 if (!chip->ecc.read_page)
2810                         chip->ecc.read_page = nand_read_page_hwecc;
2811                 if (!chip->ecc.write_page)
2812                         chip->ecc.write_page = nand_write_page_hwecc;
2813                 if (!chip->ecc.read_page_raw)
2814                         chip->ecc.read_page_raw = nand_read_page_raw;
2815                 if (!chip->ecc.write_page_raw)
2816                         chip->ecc.write_page_raw = nand_write_page_raw;
2817                 if (!chip->ecc.read_oob)
2818                         chip->ecc.read_oob = nand_read_oob_std;
2819                 if (!chip->ecc.write_oob)
2820                         chip->ecc.write_oob = nand_write_oob_std;
2821
2822         case NAND_ECC_HW_SYNDROME:
2823                 if ((!chip->ecc.calculate || !chip->ecc.correct ||
2824                      !chip->ecc.hwctl) &&
2825                     (!chip->ecc.read_page ||
2826                      chip->ecc.read_page == nand_read_page_hwecc ||
2827                      !chip->ecc.write_page ||
2828                      chip->ecc.write_page == nand_write_page_hwecc)) {
2829                         printk(KERN_WARNING "No ECC functions supplied, "
2830                                "Hardware ECC not possible\n");
2831                         BUG();
2832                 }
2833                 /* Use standard syndrome read/write page function ? */
2834                 if (!chip->ecc.read_page)
2835                         chip->ecc.read_page = nand_read_page_syndrome;
2836                 if (!chip->ecc.write_page)
2837                         chip->ecc.write_page = nand_write_page_syndrome;
2838                 if (!chip->ecc.read_page_raw)
2839                         chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
2840                 if (!chip->ecc.write_page_raw)
2841                         chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
2842                 if (!chip->ecc.read_oob)
2843                         chip->ecc.read_oob = nand_read_oob_syndrome;
2844                 if (!chip->ecc.write_oob)
2845                         chip->ecc.write_oob = nand_write_oob_syndrome;
2846
2847                 if (mtd->writesize >= chip->ecc.size)
2848                         break;
2849                 printk(KERN_WARNING "%d byte HW ECC not possible on "
2850                        "%d byte page size, fallback to SW ECC\n",
2851                        chip->ecc.size, mtd->writesize);
2852                 chip->ecc.mode = NAND_ECC_SOFT;
2853
2854         case NAND_ECC_SOFT:
2855                 chip->ecc.calculate = nand_calculate_ecc;
2856                 chip->ecc.correct = nand_correct_data;
2857                 chip->ecc.read_page = nand_read_page_swecc;
2858                 chip->ecc.read_subpage = nand_read_subpage;
2859                 chip->ecc.write_page = nand_write_page_swecc;
2860                 chip->ecc.read_page_raw = nand_read_page_raw;
2861                 chip->ecc.write_page_raw = nand_write_page_raw;
2862                 chip->ecc.read_oob = nand_read_oob_std;
2863                 chip->ecc.write_oob = nand_write_oob_std;
2864                 chip->ecc.size = 256;
2865                 chip->ecc.bytes = 3;
2866                 break;
2867
2868         case NAND_ECC_SOFT_BCH:
2869                 if (!mtd_nand_has_bch()) {
2870                         printk(KERN_WARNING "CONFIG_MTD_ECC_BCH not enabled\n");
2871                         return -EINVAL;
2872                 }
2873                 chip->ecc.calculate = nand_bch_calculate_ecc;
2874                 chip->ecc.correct = nand_bch_correct_data;
2875                 chip->ecc.read_page = nand_read_page_swecc;
2876                 chip->ecc.read_subpage = nand_read_subpage;
2877                 chip->ecc.write_page = nand_write_page_swecc;
2878                 chip->ecc.read_page_raw = nand_read_page_raw;
2879                 chip->ecc.write_page_raw = nand_write_page_raw;
2880                 chip->ecc.read_oob = nand_read_oob_std;
2881                 chip->ecc.write_oob = nand_write_oob_std;
2882                 /*
2883                  * Board driver should supply ecc.size and ecc.bytes values to
2884                  * select how many bits are correctable; see nand_bch_init()
2885                  * for details.
2886                  * Otherwise, default to 4 bits for large page devices
2887                  */
2888                 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
2889                         chip->ecc.size = 512;
2890                         chip->ecc.bytes = 7;
2891                 }
2892                 chip->ecc.priv = nand_bch_init(mtd,
2893                                                chip->ecc.size,
2894                                                chip->ecc.bytes,
2895                                                &chip->ecc.layout);
2896                 if (!chip->ecc.priv)
2897                         printk(KERN_WARNING "BCH ECC initialization failed!\n");
2898
2899                 break;
2900
2901         case NAND_ECC_NONE:
2902                 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2903                        "This is not recommended !!\n");
2904                 chip->ecc.read_page = nand_read_page_raw;
2905                 chip->ecc.write_page = nand_write_page_raw;
2906                 chip->ecc.read_oob = nand_read_oob_std;
2907                 chip->ecc.read_page_raw = nand_read_page_raw;
2908                 chip->ecc.write_page_raw = nand_write_page_raw;
2909                 chip->ecc.write_oob = nand_write_oob_std;
2910                 chip->ecc.size = mtd->writesize;
2911                 chip->ecc.bytes = 0;
2912                 break;
2913
2914         default:
2915                 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
2916                        chip->ecc.mode);
2917                 BUG();
2918         }
2919
2920         /*
2921          * The number of bytes available for a client to place data into
2922          * the out of band area
2923          */
2924         chip->ecc.layout->oobavail = 0;
2925         for (i = 0; chip->ecc.layout->oobfree[i].length
2926                         && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
2927                 chip->ecc.layout->oobavail +=
2928                         chip->ecc.layout->oobfree[i].length;
2929         mtd->oobavail = chip->ecc.layout->oobavail;
2930
2931         /*
2932          * Set the number of read / write steps for one page depending on ECC
2933          * mode
2934          */
2935         chip->ecc.steps = mtd->writesize / chip->ecc.size;
2936         if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
2937                 printk(KERN_WARNING "Invalid ecc parameters\n");
2938                 BUG();
2939         }
2940         chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
2941
2942         /*
2943          * Allow subpage writes up to ecc.steps. Not possible for MLC
2944          * FLASH.
2945          */
2946         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2947             !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
2948                 switch(chip->ecc.steps) {
2949                 case 2:
2950                         mtd->subpage_sft = 1;
2951                         break;
2952                 case 4:
2953                 case 8:
2954                 case 16:
2955                         mtd->subpage_sft = 2;
2956                         break;
2957                 }
2958         }
2959         chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
2960
2961         /* Initialize state */
2962         chip->state = FL_READY;
2963
2964         /* De-select the device */
2965         chip->select_chip(mtd, -1);
2966
2967         /* Invalidate the pagebuffer reference */
2968         chip->pagebuf = -1;
2969
2970         /* Fill in remaining MTD driver data */
2971         mtd->type = MTD_NANDFLASH;
2972         mtd->flags = MTD_CAP_NANDFLASH;
2973         mtd->erase = nand_erase;
2974         mtd->point = NULL;
2975         mtd->unpoint = NULL;
2976         mtd->read = nand_read;
2977         mtd->write = nand_write;
2978         mtd->read_oob = nand_read_oob;
2979         mtd->write_oob = nand_write_oob;
2980         mtd->sync = nand_sync;
2981         mtd->lock = NULL;
2982         mtd->unlock = NULL;
2983         mtd->block_isbad = nand_block_isbad;
2984         mtd->block_markbad = nand_block_markbad;
2985
2986         /* propagate ecc.layout to mtd_info */
2987         mtd->ecclayout = chip->ecc.layout;
2988
2989         /* Check, if we should skip the bad block table scan */
2990         if (chip->options & NAND_SKIP_BBTSCAN)
2991                 chip->options |= NAND_BBT_SCANNED;
2992
2993         return 0;
2994 }
2995
2996 /**
2997  * nand_scan - [NAND Interface] Scan for the NAND device
2998  * @mtd:        MTD device structure
2999  * @maxchips:   Number of chips to scan for
3000  *
3001  * This fills out all the uninitialized function pointers
3002  * with the defaults.
3003  * The flash ID is read and the mtd/chip structures are
3004  * filled with the appropriate values.
3005  * The mtd->owner field must be set to the module of the caller
3006  *
3007  */
3008 int nand_scan(struct mtd_info *mtd, int maxchips)
3009 {
3010         int ret;
3011
3012         ret = nand_scan_ident(mtd, maxchips, NULL);
3013         if (!ret)
3014                 ret = nand_scan_tail(mtd);
3015         return ret;
3016 }
3017
3018 /**
3019  * nand_release - [NAND Interface] Free resources held by the NAND device
3020  * @mtd:        MTD device structure
3021 */
3022 void nand_release(struct mtd_info *mtd)
3023 {
3024         struct nand_chip *chip = mtd->priv;
3025
3026         if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3027                 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3028
3029 #ifdef CONFIG_MTD_PARTITIONS
3030         /* Deregister partitions */
3031         del_mtd_partitions(mtd);
3032 #endif
3033
3034         /* Free bad block table memory */
3035         kfree(chip->bbt);
3036         if (!(chip->options & NAND_OWN_BUFFERS))
3037                 kfree(chip->buffers);
3038 }