drivers/mtd/nand/nand_base.c

   1 /*
   2  *  drivers/mtd/nand.c
   3  *
   4  *  Overview:
   5  *   This is the generic MTD driver for NAND flash devices. It should be
   6  *   capable of working with almost all NAND chips currently available.
   7  *   Basic support for AG-AND chips is provided.
   8  *
   9  *      Additional technical information is available on
  10  *      http://www.linux-mtd.infradead.org/tech/nand.html
  11  *
  12  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  13  *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
  14  *
  15  *  Credits:
  16  *      David Woodhouse for adding multichip support
  17  *
  18  *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  19  *      rework for 2K page size chips
  20  *
  21  *  TODO:
  22  *      Enable cached programming for 2k page size chips
  23  *      Check, if mtd->ecctype should be set to MTD_ECC_HW
  24  *      if we have HW ecc support.
  25  *      The AG-AND chips have nice features for speed improvement,
  26  *      which are not supported yet. Read / program 4 pages in one go.
  27  *
  28  * This program is free software; you can redistribute it and/or modify
  29  * it under the terms of the GNU General Public License version 2 as
  30  * published by the Free Software Foundation.
  31  *
  32  */
  33
  34 /* XXX U-BOOT XXX */
  35 #if 0
  36 #include <linux/module.h>
  37 #include <linux/delay.h>
  38 #include <linux/errno.h>
  39 #include <linux/err.h>
  40 #include <linux/sched.h>
  41 #include <linux/slab.h>
  42 #include <linux/types.h>
  43 #include <linux/mtd/mtd.h>
  44 #include <linux/mtd/nand.h>
  45 #include <linux/mtd/nand_ecc.h>
  46 #include <linux/mtd/compatmac.h>
  47 #include <linux/interrupt.h>
  48 #include <linux/bitops.h>
  49 #include <linux/leds.h>
  50 #include <asm/io.h>
  51
  52 #ifdef CONFIG_MTD_PARTITIONS
  53 #include <linux/mtd/partitions.h>
  54 #endif
  55
  56 #endif
  57
  58 #include <common.h>
  59
  60 #define ENOTSUPP        524     /* Operation is not supported */
  61
  62 #if defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY)
  63
  64 #include <malloc.h>
  65 #include <watchdog.h>
  66 #include <linux/err.h>
  67 #include <linux/mtd/compat.h>
  68 #include <linux/mtd/mtd.h>
  69 #include <linux/mtd/nand.h>
  70 #include <linux/mtd/nand_ecc.h>
  71
  72 #include <asm/io.h>
  73 #include <asm/errno.h>
  74
  75 #ifdef CONFIG_JFFS2_NAND
  76 #include <jffs2/jffs2.h>
  77 #endif
  78
  79 /* Define default oob placement schemes for large and small page devices */
  80 static struct nand_ecclayout nand_oob_8 = {
  81         .eccbytes = 3,
  82         .eccpos = {0, 1, 2},
  83         .oobfree = {
  84                 {.offset = 3,
  85                  .length = 2},
  86                 {.offset = 6,
  87                  .length = 2}}
  88 };
  89
  90 static struct nand_ecclayout nand_oob_16 = {
  91         .eccbytes = 6,
  92         .eccpos = {0, 1, 2, 3, 6, 7},
  93         .oobfree = {
  94                 {.offset = 8,
  95                  . length = 8}}
  96 };
  97
  98 static struct nand_ecclayout nand_oob_64 = {
  99         .eccbytes = 24,
 100         .eccpos = {
 101                    40, 41, 42, 43, 44, 45, 46, 47,
 102                    48, 49, 50, 51, 52, 53, 54, 55,
 103                    56, 57, 58, 59, 60, 61, 62, 63},
 104         .oobfree = {
 105                 {.offset = 2,
 106                  .length = 38}}
 107 };
 108
 109 static struct nand_ecclayout nand_oob_128 = {
 110         .eccbytes = 48,
 111         .eccpos = {
 112                     80,  81,  82,  83,  84,  85,  86,  87,
 113                     88,  89,  90,  91,  92,  93,  94,  95,
 114                     96,  97,  98,  99, 100, 101, 102, 103,
 115                    104, 105, 106, 107, 108, 109, 110, 111,
 116                    112, 113, 114, 115, 116, 117, 118, 119,
 117                    120, 121, 122, 123, 124, 125, 126, 127},
 118         .oobfree = {
 119                 {.offset = 2,
 120                  .length = 78}}
 121 };
 122
 123
 124 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
 125                            int new_state);
 126
 127 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
 128                              struct mtd_oob_ops *ops);
 129
 130 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this);
 131
 132 /*
 133  * For devices which display every fart in the system on a seperate LED. Is
 134  * compiled away when LED support is disabled.
 135  */
 136 /* XXX U-BOOT XXX */
 137 #if 0
 138 DEFINE_LED_TRIGGER(nand_led_trigger);
 139 #endif
 140
 141 /**
 142  * nand_release_device - [GENERIC] release chip
 143  * @mtd:        MTD device structure
 144  *
 145  * Deselect, release chip lock and wake up anyone waiting on the device
 146  */
 147 /* XXX U-BOOT XXX */
 148 #if 0
 149 static void nand_release_device(struct mtd_info *mtd)
 150 {
 151         struct nand_chip *chip = mtd->priv;
 152
 153         /* De-select the NAND device */
 154         chip->select_chip(mtd, -1);
 155
 156         /* Release the controller and the chip */
 157         spin_lock(&chip->controller->lock);
 158         chip->controller->active = NULL;
 159         chip->state = FL_READY;
 160         wake_up(&chip->controller->wq);
 161         spin_unlock(&chip->controller->lock);
 162 }
 163 #else
 164 static void nand_release_device (struct mtd_info *mtd)
 165 {
 166         struct nand_chip *this = mtd->priv;
 167         this->select_chip(mtd, -1);     /* De-select the NAND device */
 168 }
 169 #endif
 170
 171 /**
 172  * nand_read_byte - [DEFAULT] read one byte from the chip
 173  * @mtd:        MTD device structure
 174  *
 175  * Default read function for 8bit buswith
 176  */
 177 static uint8_t nand_read_byte(struct mtd_info *mtd)
 178 {
 179         struct nand_chip *chip = mtd->priv;
 180         return readb(chip->IO_ADDR_R);
 181 }
 182
 183 /**
 184  * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
 185  * @mtd:        MTD device structure
 186  *
 187  * Default read function for 16bit buswith with
 188  * endianess conversion
 189  */
 190 static uint8_t nand_read_byte16(struct mtd_info *mtd)
 191 {
 192         struct nand_chip *chip = mtd->priv;
 193         return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
 194 }
 195
 196 /**
 197  * nand_read_word - [DEFAULT] read one word from the chip
 198  * @mtd:        MTD device structure
 199  *
 200  * Default read function for 16bit buswith without
 201  * endianess conversion
 202  */
 203 static u16 nand_read_word(struct mtd_info *mtd)
 204 {
 205         struct nand_chip *chip = mtd->priv;
 206         return readw(chip->IO_ADDR_R);
 207 }
 208
 209 /**
 210  * nand_select_chip - [DEFAULT] control CE line
 211  * @mtd:        MTD device structure
 212  * @chipnr:     chipnumber to select, -1 for deselect
 213  *
 214  * Default select function for 1 chip devices.
 215  */
 216 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 217 {
 218         struct nand_chip *chip = mtd->priv;
 219
 220         switch (chipnr) {
 221         case -1:
 222                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
 223                 break;
 224         case 0:
 225                 break;
 226
 227         default:
 228                 BUG();
 229         }
 230 }
 231
 232 /**
 233  * nand_write_buf - [DEFAULT] write buffer to chip
 234  * @mtd:        MTD device structure
 235  * @buf:        data buffer
 236  * @len:        number of bytes to write
 237  *
 238  * Default write function for 8bit buswith
 239  */
 240 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 241 {
 242         int i;
 243         struct nand_chip *chip = mtd->priv;
 244
 245         for (i = 0; i < len; i++)
 246                 writeb(buf[i], chip->IO_ADDR_W);
 247 }
 248
 249 /**
 250  * nand_read_buf - [DEFAULT] read chip data into buffer
 251  * @mtd:        MTD device structure
 252  * @buf:        buffer to store date
 253  * @len:        number of bytes to read
 254  *
 255  * Default read function for 8bit buswith
 256  */
 257 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 258 {
 259         int i;
 260         struct nand_chip *chip = mtd->priv;
 261
 262         for (i = 0; i < len; i++)
 263                 buf[i] = readb(chip->IO_ADDR_R);
 264 }
 265
 266 /**
 267  * nand_verify_buf - [DEFAULT] Verify chip data against buffer
 268  * @mtd:        MTD device structure
 269  * @buf:        buffer containing the data to compare
 270  * @len:        number of bytes to compare
 271  *
 272  * Default verify function for 8bit buswith
 273  */
 274 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 275 {
 276         int i;
 277         struct nand_chip *chip = mtd->priv;
 278
 279         for (i = 0; i < len; i++)
 280                 if (buf[i] != readb(chip->IO_ADDR_R))
 281                         return -EFAULT;
 282         return 0;
 283 }
 284
 285 /**
 286  * nand_write_buf16 - [DEFAULT] write buffer to chip
 287  * @mtd:        MTD device structure
 288  * @buf:        data buffer
 289  * @len:        number of bytes to write
 290  *
 291  * Default write function for 16bit buswith
 292  */
 293 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 294 {
 295         int i;
 296         struct nand_chip *chip = mtd->priv;
 297         u16 *p = (u16 *) buf;
 298         len >>= 1;
 299
 300         for (i = 0; i < len; i++)
 301                 writew(p[i], chip->IO_ADDR_W);
 302
 303 }
 304
 305 /**
 306  * nand_read_buf16 - [DEFAULT] read chip data into buffer
 307  * @mtd:        MTD device structure
 308  * @buf:        buffer to store date
 309  * @len:        number of bytes to read
 310  *
 311  * Default read function for 16bit buswith
 312  */
 313 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 314 {
 315         int i;
 316         struct nand_chip *chip = mtd->priv;
 317         u16 *p = (u16 *) buf;
 318         len >>= 1;
 319
 320         for (i = 0; i < len; i++)
 321                 p[i] = readw(chip->IO_ADDR_R);
 322 }
 323
 324 /**
 325  * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
 326  * @mtd:        MTD device structure
 327  * @buf:        buffer containing the data to compare
 328  * @len:        number of bytes to compare
 329  *
 330  * Default verify function for 16bit buswith
 331  */
 332 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 333 {
 334         int i;
 335         struct nand_chip *chip = mtd->priv;
 336         u16 *p = (u16 *) buf;
 337         len >>= 1;
 338
 339         for (i = 0; i < len; i++)
 340                 if (p[i] != readw(chip->IO_ADDR_R))
 341                         return -EFAULT;
 342
 343         return 0;
 344 }
 345
 346 /**
 347  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
 348  * @mtd:        MTD device structure
 349  * @ofs:        offset from device start
 350  * @getchip:    0, if the chip is already selected
 351  *
 352  * Check, if the block is bad.
 353  */
 354 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 355 {
 356         int page, chipnr, res = 0;
 357         struct nand_chip *chip = mtd->priv;
 358         u16 bad;
 359
 360         page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 361
 362         if (getchip) {
 363                 chipnr = (int)(ofs >> chip->chip_shift);
 364
 365                 nand_get_device(chip, mtd, FL_READING);
 366
 367                 /* Select the NAND device */
 368                 chip->select_chip(mtd, chipnr);
 369         }
 370
 371         if (chip->options & NAND_BUSWIDTH_16) {
 372                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
 373                               page);
 374                 bad = cpu_to_le16(chip->read_word(mtd));
 375                 if (chip->badblockpos & 0x1)
 376                         bad >>= 8;
 377                 if ((bad & 0xFF) != 0xff)
 378                         res = 1;
 379         } else {
 380                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
 381                 if (chip->read_byte(mtd) != 0xff)
 382                         res = 1;
 383         }
 384
 385         if (getchip)
 386                 nand_release_device(mtd);
 387
 388         return res;
 389 }
 390
 391 /**
 392  * nand_default_block_markbad - [DEFAULT] mark a block bad
 393  * @mtd:        MTD device structure
 394  * @ofs:        offset from device start
 395  *
 396  * This is the default implementation, which can be overridden by
 397  * a hardware specific driver.
 398 */
 399 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 400 {
 401         struct nand_chip *chip = mtd->priv;
 402         uint8_t buf[2] = { 0, 0 };
 403         int block, ret;
 404
 405         /* Get block number */
 406         block = (int)(ofs >> chip->bbt_erase_shift);
 407         if (chip->bbt)
 408                 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
 409
 410         /* Do we have a flash based bad block table ? */
 411         if (chip->options & NAND_USE_FLASH_BBT)
 412                 ret = nand_update_bbt(mtd, ofs);
 413         else {
 414                 /* We write two bytes, so we dont have to mess with 16 bit
 415                  * access
 416                  */
 417                 ofs += mtd->oobsize;
 418                 chip->ops.len = chip->ops.ooblen = 2;
 419                 chip->ops.datbuf = NULL;
 420                 chip->ops.oobbuf = buf;
 421                 chip->ops.ooboffs = chip->badblockpos & ~0x01;
 422
 423                 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
 424         }
 425         if (!ret)
 426                 mtd->ecc_stats.badblocks++;
 427         return ret;
 428 }
 429
 430 /**
 431  * nand_check_wp - [GENERIC] check if the chip is write protected
 432  * @mtd:        MTD device structure
 433  * Check, if the device is write protected
 434  *
 435  * The function expects, that the device is already selected
 436  */
 437 static int nand_check_wp(struct mtd_info *mtd)
 438 {
 439         struct nand_chip *chip = mtd->priv;
 440         /* Check the WP bit */
 441         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 442         return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
 443 }
 444
 445 /**
 446  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
 447  * @mtd:        MTD device structure
 448  * @ofs:        offset from device start
 449  * @getchip:    0, if the chip is already selected
 450  * @allowbbt:   1, if its allowed to access the bbt area
 451  *
 452  * Check, if the block is bad. Either by reading the bad block table or
 453  * calling of the scan function.
 454  */
 455 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
 456                                int allowbbt)
 457 {
 458         struct nand_chip *chip = mtd->priv;
 459
 460         if (!(chip->options & NAND_BBT_SCANNED)) {
 461                 chip->scan_bbt(mtd);
 462                 chip->options |= NAND_BBT_SCANNED;
 463         }
 464
 465         if (!chip->bbt)
 466                 return chip->block_bad(mtd, ofs, getchip);
 467
 468         /* Return info from the table */
 469         return nand_isbad_bbt(mtd, ofs, allowbbt);
 470 }
 471
 472 /*
 473  * Wait for the ready pin, after a command
 474  * The timeout is catched later.
 475  */
 476 /* XXX U-BOOT XXX */
 477 #if 0
 478 void nand_wait_ready(struct mtd_info *mtd)
 479 {
 480         struct nand_chip *chip = mtd->priv;
 481         unsigned long timeo = jiffies + 2;
 482
 483         led_trigger_event(nand_led_trigger, LED_FULL);
 484         /* wait until command is processed or timeout occures */
 485         do {
 486                 if (chip->dev_ready(mtd))
 487                         break;
 488                 touch_softlockup_watchdog();
 489         } while (time_before(jiffies, timeo));
 490         led_trigger_event(nand_led_trigger, LED_OFF);
 491 }
 492 EXPORT_SYMBOL_GPL(nand_wait_ready);
 493 #else
 494 void nand_wait_ready(struct mtd_info *mtd)
 495 {
 496         struct nand_chip *chip = mtd->priv;
 497         u32 timeo = (CFG_HZ * 20) / 1000;
 498
 499         reset_timer();
 500
 501         /* wait until command is processed or timeout occures */
 502         while (get_timer(0) < timeo) {
 503                 if (chip->dev_ready)
 504                         if (chip->dev_ready(mtd))
 505                                 break;
 506         }
 507 }
 508 #endif
 509
 510 /**
 511  * nand_command - [DEFAULT] Send command to NAND device
 512  * @mtd:        MTD device structure
 513  * @command:    the command to be sent
 514  * @column:     the column address for this command, -1 if none
 515  * @page_addr:  the page address for this command, -1 if none
 516  *
 517  * Send command to NAND device. This function is used for small page
 518  * devices (256/512 Bytes per page)
 519  */
 520 static void nand_command(struct mtd_info *mtd, unsigned int command,
 521                          int column, int page_addr)
 522 {
 523         register struct nand_chip *chip = mtd->priv;
 524         int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
 525
 526         /*
 527          * Write out the command to the device.
 528          */
 529         if (command == NAND_CMD_SEQIN) {
 530                 int readcmd;
 531
 532                 if (column >= mtd->writesize) {
 533                         /* OOB area */
 534                         column -= mtd->writesize;
 535                         readcmd = NAND_CMD_READOOB;
 536                 } else if (column < 256) {
 537                         /* First 256 bytes --> READ0 */
 538                         readcmd = NAND_CMD_READ0;
 539                 } else {
 540                         column -= 256;
 541                         readcmd = NAND_CMD_READ1;
 542                 }
 543                 chip->cmd_ctrl(mtd, readcmd, ctrl);
 544                 ctrl &= ~NAND_CTRL_CHANGE;
 545         }
 546         chip->cmd_ctrl(mtd, command, ctrl);
 547
 548         /*
 549          * Address cycle, when necessary
 550          */
 551         ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
 552         /* Serially input address */
 553         if (column != -1) {
 554                 /* Adjust columns for 16 bit buswidth */
 555                 if (chip->options & NAND_BUSWIDTH_16)
 556                         column >>= 1;
 557                 chip->cmd_ctrl(mtd, column, ctrl);
 558                 ctrl &= ~NAND_CTRL_CHANGE;
 559         }
 560         if (page_addr != -1) {
 561                 chip->cmd_ctrl(mtd, page_addr, ctrl);
 562                 ctrl &= ~NAND_CTRL_CHANGE;
 563                 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
 564                 /* One more address cycle for devices > 32MiB */
 565                 if (chip->chipsize > (32 << 20))
 566                         chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
 567         }
 568         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 569
 570         /*
 571          * program and erase have their own busy handlers
 572          * status and sequential in needs no delay
 573          */
 574         switch (command) {
 575
 576         case NAND_CMD_PAGEPROG:
 577         case NAND_CMD_ERASE1:
 578         case NAND_CMD_ERASE2:
 579         case NAND_CMD_SEQIN:
 580         case NAND_CMD_STATUS:
 581                 return;
 582
 583         case NAND_CMD_RESET:
 584                 if (chip->dev_ready)
 585                         break;
 586                 udelay(chip->chip_delay);
 587                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 588                                NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 589                 chip->cmd_ctrl(mtd,
 590                                NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 591                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
 592                 return;
 593
 594                 /* This applies to read commands */
 595         default:
 596                 /*
 597                  * If we don't have access to the busy pin, we apply the given
 598                  * command delay
 599                  */
 600                 if (!chip->dev_ready) {
 601                         udelay(chip->chip_delay);
 602                         return;
 603                 }
 604         }
 605         /* Apply this short delay always to ensure that we do wait tWB in
 606          * any case on any machine. */
 607         ndelay(100);
 608
 609         nand_wait_ready(mtd);
 610 }
 611
 612 /**
 613  * nand_command_lp - [DEFAULT] Send command to NAND large page device
 614  * @mtd:        MTD device structure
 615  * @command:    the command to be sent
 616  * @column:     the column address for this command, -1 if none
 617  * @page_addr:  the page address for this command, -1 if none
 618  *
 619  * Send command to NAND device. This is the version for the new large page
 620  * devices We dont have the separate regions as we have in the small page
 621  * devices.  We must emulate NAND_CMD_READOOB to keep the code compatible.
 622  */
 623 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
 624                             int column, int page_addr)
 625 {
 626         register struct nand_chip *chip = mtd->priv;
 627
 628         /* Emulate NAND_CMD_READOOB */
 629         if (command == NAND_CMD_READOOB) {
 630                 column += mtd->writesize;
 631                 command = NAND_CMD_READ0;
 632         }
 633
 634         /* Command latch cycle */
 635         chip->cmd_ctrl(mtd, command & 0xff,
 636                        NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 637
 638         if (column != -1 || page_addr != -1) {
 639                 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
 640
 641                 /* Serially input address */
 642                 if (column != -1) {
 643                         /* Adjust columns for 16 bit buswidth */
 644                         if (chip->options & NAND_BUSWIDTH_16)
 645                                 column >>= 1;
 646                         chip->cmd_ctrl(mtd, column, ctrl);
 647                         ctrl &= ~NAND_CTRL_CHANGE;
 648                         chip->cmd_ctrl(mtd, column >> 8, ctrl);
 649                 }
 650                 if (page_addr != -1) {
 651                         chip->cmd_ctrl(mtd, page_addr, ctrl);
 652                         chip->cmd_ctrl(mtd, page_addr >> 8,
 653                                        NAND_NCE | NAND_ALE);
 654                         /* One more address cycle for devices > 128MiB */
 655                         if (chip->chipsize > (128 << 20))
 656                                 chip->cmd_ctrl(mtd, page_addr >> 16,
 657                                                NAND_NCE | NAND_ALE);
 658                 }
 659         }
 660         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 661
 662         /*
 663          * program and erase have their own busy handlers
 664          * status, sequential in, and deplete1 need no delay
 665          */
 666         switch (command) {
 667
 668         case NAND_CMD_CACHEDPROG:
 669         case NAND_CMD_PAGEPROG:
 670         case NAND_CMD_ERASE1:
 671         case NAND_CMD_ERASE2:
 672         case NAND_CMD_SEQIN:
 673         case NAND_CMD_RNDIN:
 674         case NAND_CMD_STATUS:
 675         case NAND_CMD_DEPLETE1:
 676                 return;
 677
 678                 /*
 679                  * read error status commands require only a short delay
 680                  */
 681         case NAND_CMD_STATUS_ERROR:
 682         case NAND_CMD_STATUS_ERROR0:
 683         case NAND_CMD_STATUS_ERROR1:
 684         case NAND_CMD_STATUS_ERROR2:
 685         case NAND_CMD_STATUS_ERROR3:
 686                 udelay(chip->chip_delay);
 687                 return;
 688
 689         case NAND_CMD_RESET:
 690                 if (chip->dev_ready)
 691                         break;
 692                 udelay(chip->chip_delay);
 693                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 694                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 695                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 696                                NAND_NCE | NAND_CTRL_CHANGE);
 697                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
 698                 return;
 699
 700         case NAND_CMD_RNDOUT:
 701                 /* No ready / busy check necessary */
 702                 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
 703                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 704                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 705                                NAND_NCE | NAND_CTRL_CHANGE);
 706                 return;
 707
 708         case NAND_CMD_READ0:
 709                 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
 710                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 711                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 712                                NAND_NCE | NAND_CTRL_CHANGE);
 713
 714                 /* This applies to read commands */
 715         default:
 716                 /*
 717                  * If we don't have access to the busy pin, we apply the given
 718                  * command delay
 719                  */
 720                 if (!chip->dev_ready) {
 721                         udelay(chip->chip_delay);
 722                         return;
 723                 }
 724         }
 725
 726         /* Apply this short delay always to ensure that we do wait tWB in
 727          * any case on any machine. */
 728         ndelay(100);
 729
 730         nand_wait_ready(mtd);
 731 }
 732
 733 /**
 734  * nand_get_device - [GENERIC] Get chip for selected access
 735  * @chip:       the nand chip descriptor
 736  * @mtd:        MTD device structure
 737  * @new_state:  the state which is requested
 738  *
 739  * Get the device and lock it for exclusive access
 740  */
 741 /* XXX U-BOOT XXX */
 742 #if 0
 743 static int
 744 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
 745 {
 746         spinlock_t *lock = &chip->controller->lock;
 747         wait_queue_head_t *wq = &chip->controller->wq;
 748         DECLARE_WAITQUEUE(wait, current);
 749  retry:
 750         spin_lock(lock);
 751
 752         /* Hardware controller shared among independend devices */
 753         /* Hardware controller shared among independend devices */
 754         if (!chip->controller->active)
 755                 chip->controller->active = chip;
 756
 757         if (chip->controller->active == chip && chip->state == FL_READY) {
 758                 chip->state = new_state;
 759                 spin_unlock(lock);
 760                 return 0;
 761         }
 762         if (new_state == FL_PM_SUSPENDED) {
 763                 spin_unlock(lock);
 764                 return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN;
 765         }
 766         set_current_state(TASK_UNINTERRUPTIBLE);
 767         add_wait_queue(wq, &wait);
 768         spin_unlock(lock);
 769         schedule();
 770         remove_wait_queue(wq, &wait);
 771         goto retry;
 772 }
 773 #else
 774 static int nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state)
 775 {
 776         this->state = new_state;
 777         return 0;
 778 }
 779 #endif
 780
 781 /**
 782  * nand_wait - [DEFAULT]  wait until the command is done
 783  * @mtd:        MTD device structure
 784  * @chip:       NAND chip structure
 785  *
 786  * Wait for command done. This applies to erase and program only
 787  * Erase can take up to 400ms and program up to 20ms according to
 788  * general NAND and SmartMedia specs
 789  */
 790 /* XXX U-BOOT XXX */
 791 #if 0
 792 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
 793 {
 794
 795         unsigned long timeo = jiffies;
 796         int status, state = chip->state;
 797
 798         if (state == FL_ERASING)
 799                 timeo += (HZ * 400) / 1000;
 800         else
 801                 timeo += (HZ * 20) / 1000;
 802
 803         led_trigger_event(nand_led_trigger, LED_FULL);
 804
 805         /* Apply this short delay always to ensure that we do wait tWB in
 806          * any case on any machine. */
 807         ndelay(100);
 808
 809         if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
 810                 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
 811         else
 812                 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 813
 814         while (time_before(jiffies, timeo)) {
 815                 if (chip->dev_ready) {
 816                         if (chip->dev_ready(mtd))
 817                                 break;
 818                 } else {
 819                         if (chip->read_byte(mtd) & NAND_STATUS_READY)
 820                                 break;
 821                 }
 822                 cond_resched();
 823         }
 824         led_trigger_event(nand_led_trigger, LED_OFF);
 825
 826         status = (int)chip->read_byte(mtd);
 827         return status;
 828 }
 829 #else
 830 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this)
 831 {
 832         unsigned long   timeo;
 833         int state = this->state;
 834
 835         if (state == FL_ERASING)
 836                 timeo = (CFG_HZ * 400) / 1000;
 837         else
 838                 timeo = (CFG_HZ * 20) / 1000;
 839
 840         if ((state == FL_ERASING) && (this->options & NAND_IS_AND))
 841                 this->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
 842         else
 843                 this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 844
 845         reset_timer();
 846
 847         while (1) {
 848                 if (get_timer(0) > timeo) {
 849                         printf("Timeout!");
 850                         return 0x01;
 851                 }
 852
 853                 if (this->dev_ready) {
 854                         if (this->dev_ready(mtd))
 855                                 break;
 856                 } else {
 857                         if (this->read_byte(mtd) & NAND_STATUS_READY)
 858                                 break;
 859                 }
 860         }
 861 #ifdef PPCHAMELON_NAND_TIMER_HACK
 862         reset_timer();
 863         while (get_timer(0) < 10);
 864 #endif /*  PPCHAMELON_NAND_TIMER_HACK */
 865
 866         return this->read_byte(mtd);
 867 }
 868 #endif
 869
 870 /**
 871  * nand_read_page_raw - [Intern] read raw page data without ecc
 872  * @mtd:        mtd info structure
 873  * @chip:       nand chip info structure
 874  * @buf:        buffer to store read data
 875  */
 876 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
 877                               uint8_t *buf)
 878 {
 879         chip->read_buf(mtd, buf, mtd->writesize);
 880         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 881         return 0;
 882 }
 883
 884 /**
 885  * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
 886  * @mtd:        mtd info structure
 887  * @chip:       nand chip info structure
 888  * @buf:        buffer to store read data
 889  */
 890 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
 891                                 uint8_t *buf)
 892 {
 893         int i, eccsize = chip->ecc.size;
 894         int eccbytes = chip->ecc.bytes;
 895         int eccsteps = chip->ecc.steps;
 896         uint8_t *p = buf;
 897         uint8_t *ecc_calc = chip->buffers->ecccalc;
 898         uint8_t *ecc_code = chip->buffers->ecccode;
 899         uint32_t *eccpos = chip->ecc.layout->eccpos;
 900
 901         chip->ecc.read_page_raw(mtd, chip, buf);
 902
 903         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
 904                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 905
 906         for (i = 0; i < chip->ecc.total; i++)
 907                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 908
 909         eccsteps = chip->ecc.steps;
 910         p = buf;
 911
 912         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 913                 int stat;
 914
 915                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 916                 if (stat == -1)
 917                         mtd->ecc_stats.failed++;
 918                 else
 919                         mtd->ecc_stats.corrected += stat;
 920         }
 921         return 0;
 922 }
 923
 924 /**
 925  * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
 926  * @mtd:        mtd info structure
 927  * @chip:       nand chip info structure
 928  * @buf:        buffer to store read data
 929  *
 930  * Not for syndrome calculating ecc controllers which need a special oob layout
 931  */
 932 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
 933                                 uint8_t *buf)
 934 {
 935         int i, eccsize = chip->ecc.size;
 936         int eccbytes = chip->ecc.bytes;
 937         int eccsteps = chip->ecc.steps;
 938         uint8_t *p = buf;
 939         uint8_t *ecc_calc = chip->buffers->ecccalc;
 940         uint8_t *ecc_code = chip->buffers->ecccode;
 941         uint32_t *eccpos = chip->ecc.layout->eccpos;
 942
 943         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 944                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 945                 chip->read_buf(mtd, p, eccsize);
 946                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 947         }
 948         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 949
 950         for (i = 0; i < chip->ecc.total; i++)
 951                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 952
 953         eccsteps = chip->ecc.steps;
 954         p = buf;
 955
 956         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 957                 int stat;
 958
 959                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 960                 if (stat == -1)
 961                         mtd->ecc_stats.failed++;
 962                 else
 963                         mtd->ecc_stats.corrected += stat;
 964         }
 965         return 0;
 966 }
 967
 968 /**
 969  * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
 970  * @mtd:        mtd info structure
 971  * @chip:       nand chip info structure
 972  * @buf:        buffer to store read data
 973  *
 974  * The hw generator calculates the error syndrome automatically. Therefor
 975  * we need a special oob layout and handling.
 976  */
 977 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
 978                                    uint8_t *buf)
 979 {
 980         int i, eccsize = chip->ecc.size;
 981         int eccbytes = chip->ecc.bytes;
 982         int eccsteps = chip->ecc.steps;
 983         uint8_t *p = buf;
 984         uint8_t *oob = chip->oob_poi;
 985
 986         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 987                 int stat;
 988
 989                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 990                 chip->read_buf(mtd, p, eccsize);
 991
 992                 if (chip->ecc.prepad) {
 993                         chip->read_buf(mtd, oob, chip->ecc.prepad);
 994                         oob += chip->ecc.prepad;
 995                 }
 996
 997                 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
 998                 chip->read_buf(mtd, oob, eccbytes);
 999                 stat = chip->ecc.correct(mtd, p, oob, NULL);
1000
1001                 if (stat == -1)
1002                         mtd->ecc_stats.failed++;
1003                 else
1004                         mtd->ecc_stats.corrected += stat;
1005
1006                 oob += eccbytes;
1007
1008                 if (chip->ecc.postpad) {
1009                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1010                         oob += chip->ecc.postpad;
1011                 }
1012         }
1013
1014         /* Calculate remaining oob bytes */
1015         i = mtd->oobsize - (oob - chip->oob_poi);
1016         if (i)
1017                 chip->read_buf(mtd, oob, i);
1018
1019         return 0;
1020 }
1021
1022 /**
1023  * nand_transfer_oob - [Internal] Transfer oob to client buffer
1024  * @chip:       nand chip structure
1025  * @oob:        oob destination address
1026  * @ops:        oob ops structure
1027  * @len:        size of oob to transfer
1028  */
1029 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1030                                   struct mtd_oob_ops *ops, size_t len)
1031 {
1032         switch(ops->mode) {
1033
1034         case MTD_OOB_PLACE:
1035         case MTD_OOB_RAW:
1036                 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1037                 return oob + len;
1038
1039         case MTD_OOB_AUTO: {
1040                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1041                 uint32_t boffs = 0, roffs = ops->ooboffs;
1042                 size_t bytes = 0;
1043
1044                 for(; free->length && len; free++, len -= bytes) {
1045                         /* Read request not from offset 0 ? */
1046                         if (unlikely(roffs)) {
1047                                 if (roffs >= free->length) {
1048                                         roffs -= free->length;
1049                                         continue;
1050                                 }
1051                                 boffs = free->offset + roffs;
1052                                 bytes = min_t(size_t, len,
1053                                               (free->length - roffs));
1054                                 roffs = 0;
1055                         } else {
1056                                 bytes = min_t(size_t, len, free->length);
1057                                 boffs = free->offset;
1058                         }
1059                         memcpy(oob, chip->oob_poi + boffs, bytes);
1060                         oob += bytes;
1061                 }
1062                 return oob;
1063         }
1064         default:
1065                 BUG();
1066         }
1067         return NULL;
1068 }
1069
1070 /**
1071  * nand_do_read_ops - [Internal] Read data with ECC
1072  *
1073  * @mtd:        MTD device structure
1074  * @from:       offset to read from
1075  * @ops:        oob ops structure
1076  *
1077  * Internal function. Called with chip held.
1078  */
1079 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1080                             struct mtd_oob_ops *ops)
1081 {
1082         int chipnr, page, realpage, col, bytes, aligned;
1083         struct nand_chip *chip = mtd->priv;
1084         struct mtd_ecc_stats stats;
1085         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1086         int sndcmd = 1;
1087         int ret = 0;
1088         uint32_t readlen = ops->len;
1089         uint32_t oobreadlen = ops->ooblen;
1090         uint8_t *bufpoi, *oob, *buf;
1091
1092         stats = mtd->ecc_stats;
1093
1094         chipnr = (int)(from >> chip->chip_shift);
1095         chip->select_chip(mtd, chipnr);
1096
1097         realpage = (int)(from >> chip->page_shift);
1098         page = realpage & chip->pagemask;
1099
1100         col = (int)(from & (mtd->writesize - 1));
1101
1102         buf = ops->datbuf;
1103         oob = ops->oobbuf;
1104
1105         while(1) {
1106                 bytes = min(mtd->writesize - col, readlen);
1107                 aligned = (bytes == mtd->writesize);
1108
1109                 /* Is the current page in the buffer ? */
1110                 if (realpage != chip->pagebuf || oob) {
1111                         bufpoi = aligned ? buf : chip->buffers->databuf;
1112
1113                         if (likely(sndcmd)) {
1114                                 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1115                                 sndcmd = 0;
1116                         }
1117
1118                         /* Now read the page into the buffer */
1119                         if (unlikely(ops->mode == MTD_OOB_RAW))
1120                                 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi);
1121                         else
1122                                 ret = chip->ecc.read_page(mtd, chip, bufpoi);
1123                         if (ret < 0)
1124                                 break;
1125
1126                         /* Transfer not aligned data */
1127                         if (!aligned) {
1128                                 chip->pagebuf = realpage;
1129                                 memcpy(buf, chip->buffers->databuf + col, bytes);
1130                         }
1131
1132                         buf += bytes;
1133
1134                         if (unlikely(oob)) {
1135                                 /* Raw mode does data:oob:data:oob */
1136                                 if (ops->mode != MTD_OOB_RAW) {
1137                                         int toread = min(oobreadlen,
1138                                                 chip->ecc.layout->oobavail);
1139                                         if (toread) {
1140                                                 oob = nand_transfer_oob(chip,
1141                                                         oob, ops, toread);
1142                                                 oobreadlen -= toread;
1143                                         }
1144                                 } else
1145                                         buf = nand_transfer_oob(chip,
1146                                                 buf, ops, mtd->oobsize);
1147                         }
1148
1149                         if (!(chip->options & NAND_NO_READRDY)) {
1150                                 /*
1151                                  * Apply delay or wait for ready/busy pin. Do
1152                                  * this before the AUTOINCR check, so no
1153                                  * problems arise if a chip which does auto
1154                                  * increment is marked as NOAUTOINCR by the
1155                                  * board driver.
1156                                  */
1157                                 if (!chip->dev_ready)
1158                                         udelay(chip->chip_delay);
1159                                 else
1160                                         nand_wait_ready(mtd);
1161                         }
1162                 } else {
1163                         memcpy(buf, chip->buffers->databuf + col, bytes);
1164                         buf += bytes;
1165                 }
1166
1167                 readlen -= bytes;
1168
1169                 if (!readlen)
1170                         break;
1171
1172                 /* For subsequent reads align to page boundary. */
1173                 col = 0;
1174                 /* Increment page address */
1175                 realpage++;
1176
1177                 page = realpage & chip->pagemask;
1178                 /* Check, if we cross a chip boundary */
1179                 if (!page) {
1180                         chipnr++;
1181                         chip->select_chip(mtd, -1);
1182                         chip->select_chip(mtd, chipnr);
1183                 }
1184
1185                 /* Check, if the chip supports auto page increment
1186                  * or if we have hit a block boundary.
1187                  */
1188                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1189                         sndcmd = 1;
1190         }
1191
1192         ops->retlen = ops->len - (size_t) readlen;
1193         if (oob)
1194                 ops->oobretlen = ops->ooblen - oobreadlen;
1195
1196         if (ret)
1197                 return ret;
1198
1199         if (mtd->ecc_stats.failed - stats.failed)
1200                 return -EBADMSG;
1201
1202         return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1203 }
1204
1205 /**
1206  * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1207  * @mtd:        MTD device structure
1208  * @from:       offset to read from
1209  * @len:        number of bytes to read
1210  * @retlen:     pointer to variable to store the number of read bytes
1211  * @buf:        the databuffer to put data
1212  *
1213  * Get hold of the chip and call nand_do_read
1214  */
1215 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1216                      size_t *retlen, uint8_t *buf)
1217 {
1218         struct nand_chip *chip = mtd->priv;
1219         int ret;
1220
1221         /* Do not allow reads past end of device */
1222         if ((from + len) > mtd->size)
1223                 return -EINVAL;
1224         if (!len)
1225                 return 0;
1226
1227         nand_get_device(chip, mtd, FL_READING);
1228
1229         chip->ops.len = len;
1230         chip->ops.datbuf = buf;
1231         chip->ops.oobbuf = NULL;
1232
1233         ret = nand_do_read_ops(mtd, from, &chip->ops);
1234
1235         *retlen = chip->ops.retlen;
1236
1237         nand_release_device(mtd);
1238
1239         return ret;
1240 }
1241
1242 /**
1243  * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1244  * @mtd:        mtd info structure
1245  * @chip:       nand chip info structure
1246  * @page:       page number to read
1247  * @sndcmd:     flag whether to issue read command or not
1248  */
1249 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1250                              int page, int sndcmd)
1251 {
1252         if (sndcmd) {
1253                 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1254                 sndcmd = 0;
1255         }
1256         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1257         return sndcmd;
1258 }
1259
1260 /**
1261  * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1262  *                          with syndromes
1263  * @mtd:        mtd info structure
1264  * @chip:       nand chip info structure
1265  * @page:       page number to read
1266  * @sndcmd:     flag whether to issue read command or not
1267  */
1268 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1269                                   int page, int sndcmd)
1270 {
1271         uint8_t *buf = chip->oob_poi;
1272         int length = mtd->oobsize;
1273         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1274         int eccsize = chip->ecc.size;
1275         uint8_t *bufpoi = buf;
1276         int i, toread, sndrnd = 0, pos;
1277
1278         chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1279         for (i = 0; i < chip->ecc.steps; i++) {
1280                 if (sndrnd) {
1281                         pos = eccsize + i * (eccsize + chunk);
1282                         if (mtd->writesize > 512)
1283                                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1284                         else
1285                                 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1286                 } else
1287                         sndrnd = 1;
1288                 toread = min_t(int, length, chunk);
1289                 chip->read_buf(mtd, bufpoi, toread);
1290                 bufpoi += toread;
1291                 length -= toread;
1292         }
1293         if (length > 0)
1294                 chip->read_buf(mtd, bufpoi, length);
1295
1296         return 1;
1297 }
1298
1299 /**
1300  * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1301  * @mtd:        mtd info structure
1302  * @chip:       nand chip info structure
1303  * @page:       page number to write
1304  */
1305 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1306                               int page)
1307 {
1308         int status = 0;
1309         const uint8_t *buf = chip->oob_poi;
1310         int length = mtd->oobsize;
1311
1312         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1313         chip->write_buf(mtd, buf, length);
1314         /* Send command to program the OOB data */
1315         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1316
1317         status = chip->waitfunc(mtd, chip);
1318
1319         return status & NAND_STATUS_FAIL ? -EIO : 0;
1320 }
1321
1322 /**
1323  * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1324  *                           with syndrome - only for large page flash !
1325  * @mtd:        mtd info structure
1326  * @chip:       nand chip info structure
1327  * @page:       page number to write
1328  */
1329 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1330                                    struct nand_chip *chip, int page)
1331 {
1332         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1333         int eccsize = chip->ecc.size, length = mtd->oobsize;
1334         int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1335         const uint8_t *bufpoi = chip->oob_poi;
1336
1337         /*
1338          * data-ecc-data-ecc ... ecc-oob
1339          * or
1340          * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1341          */
1342         if (!chip->ecc.prepad && !chip->ecc.postpad) {
1343                 pos = steps * (eccsize + chunk);
1344                 steps = 0;
1345         } else
1346                 pos = eccsize;
1347
1348         chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1349         for (i = 0; i < steps; i++) {
1350                 if (sndcmd) {
1351                         if (mtd->writesize <= 512) {
1352                                 uint32_t fill = 0xFFFFFFFF;
1353
1354                                 len = eccsize;
1355                                 while (len > 0) {
1356                                         int num = min_t(int, len, 4);
1357                                         chip->write_buf(mtd, (uint8_t *)&fill,
1358                                                         num);
1359                                         len -= num;
1360                                 }
1361                         } else {
1362                                 pos = eccsize + i * (eccsize + chunk);
1363                                 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1364                         }
1365                 } else
1366                         sndcmd = 1;
1367                 len = min_t(int, length, chunk);
1368                 chip->write_buf(mtd, bufpoi, len);
1369                 bufpoi += len;
1370                 length -= len;
1371         }
1372         if (length > 0)
1373                 chip->write_buf(mtd, bufpoi, length);
1374
1375         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1376         status = chip->waitfunc(mtd, chip);
1377
1378         return status & NAND_STATUS_FAIL ? -EIO : 0;
1379 }
1380
1381 /**
1382  * nand_do_read_oob - [Intern] NAND read out-of-band
1383  * @mtd:        MTD device structure
1384  * @from:       offset to read from
1385  * @ops:        oob operations description structure
1386  *
1387  * NAND read out-of-band data from the spare area
1388  */
1389 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1390                             struct mtd_oob_ops *ops)
1391 {
1392         int page, realpage, chipnr, sndcmd = 1;
1393         struct nand_chip *chip = mtd->priv;
1394         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1395         int readlen = ops->ooblen;
1396         int len;
1397         uint8_t *buf = ops->oobbuf;
1398
1399         MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n",
1400                   (unsigned long long)from, readlen);
1401
1402         if (ops->mode == MTD_OOB_AUTO)
1403                 len = chip->ecc.layout->oobavail;
1404         else
1405                 len = mtd->oobsize;
1406
1407         if (unlikely(ops->ooboffs >= len)) {
1408                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1409                           "Attempt to start read outside oob\n");
1410                 return -EINVAL;
1411         }
1412
1413         /* Do not allow reads past end of device */
1414         if (unlikely(from >= mtd->size ||
1415                      ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1416                                         (from >> chip->page_shift)) * len)) {
1417                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1418                           "Attempt read beyond end of device\n");
1419                 return -EINVAL;
1420         }
1421
1422         chipnr = (int)(from >> chip->chip_shift);
1423         chip->select_chip(mtd, chipnr);
1424
1425         /* Shift to get page */
1426         realpage = (int)(from >> chip->page_shift);
1427         page = realpage & chip->pagemask;
1428
1429         while(1) {
1430                 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1431
1432                 len = min(len, readlen);
1433                 buf = nand_transfer_oob(chip, buf, ops, len);
1434
1435                 if (!(chip->options & NAND_NO_READRDY)) {
1436                         /*
1437                          * Apply delay or wait for ready/busy pin. Do this
1438                          * before the AUTOINCR check, so no problems arise if a
1439                          * chip which does auto increment is marked as
1440                          * NOAUTOINCR by the board driver.
1441                          */
1442                         if (!chip->dev_ready)
1443                                 udelay(chip->chip_delay);
1444                         else
1445                                 nand_wait_ready(mtd);
1446                 }
1447
1448                 readlen -= len;
1449                 if (!readlen)
1450                         break;
1451
1452                 /* Increment page address */
1453                 realpage++;
1454
1455                 page = realpage & chip->pagemask;
1456                 /* Check, if we cross a chip boundary */
1457                 if (!page) {
1458                         chipnr++;
1459                         chip->select_chip(mtd, -1);
1460                         chip->select_chip(mtd, chipnr);
1461                 }
1462
1463                 /* Check, if the chip supports auto page increment
1464                  * or if we have hit a block boundary.
1465                  */
1466                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1467                         sndcmd = 1;
1468         }
1469
1470         ops->oobretlen = ops->ooblen;
1471         return 0;
1472 }
1473
1474 /**
1475  * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1476  * @mtd:        MTD device structure
1477  * @from:       offset to read from
1478  * @ops:        oob operation description structure
1479  *
1480  * NAND read data and/or out-of-band data
1481  */
1482 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1483                          struct mtd_oob_ops *ops)
1484 {
1485         struct nand_chip *chip = mtd->priv;
1486         int ret = -ENOTSUPP;
1487
1488         ops->retlen = 0;
1489
1490         /* Do not allow reads past end of device */
1491         if (ops->datbuf && (from + ops->len) > mtd->size) {
1492                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1493                           "Attempt read beyond end of device\n");
1494                 return -EINVAL;
1495         }
1496
1497         nand_get_device(chip, mtd, FL_READING);
1498
1499         switch(ops->mode) {
1500         case MTD_OOB_PLACE:
1501         case MTD_OOB_AUTO:
1502         case MTD_OOB_RAW:
1503                 break;
1504
1505         default:
1506                 goto out;
1507         }
1508
1509         if (!ops->datbuf)
1510                 ret = nand_do_read_oob(mtd, from, ops);
1511         else
1512                 ret = nand_do_read_ops(mtd, from, ops);
1513
1514  out:
1515         nand_release_device(mtd);
1516         return ret;
1517 }
1518
1519
1520 /**
1521  * nand_write_page_raw - [Intern] raw page write function
1522  * @mtd:        mtd info structure
1523  * @chip:       nand chip info structure
1524  * @buf:        data buffer
1525  */
1526 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1527                                 const uint8_t *buf)
1528 {
1529         chip->write_buf(mtd, buf, mtd->writesize);
1530         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1531 }
1532
1533 /**
1534  * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1535  * @mtd:        mtd info structure
1536  * @chip:       nand chip info structure
1537  * @buf:        data buffer
1538  */
1539 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1540                                   const uint8_t *buf)
1541 {
1542         int i, eccsize = chip->ecc.size;
1543         int eccbytes = chip->ecc.bytes;
1544         int eccsteps = chip->ecc.steps;
1545         uint8_t *ecc_calc = chip->buffers->ecccalc;
1546         const uint8_t *p = buf;
1547         uint32_t *eccpos = chip->ecc.layout->eccpos;
1548
1549         /* Software ecc calculation */
1550         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1551                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1552
1553         for (i = 0; i < chip->ecc.total; i++)
1554                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1555
1556         chip->ecc.write_page_raw(mtd, chip, buf);
1557 }
1558
1559 /**
1560  * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1561  * @mtd:        mtd info structure
1562  * @chip:       nand chip info structure
1563  * @buf:        data buffer
1564  */
1565 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1566                                   const uint8_t *buf)
1567 {
1568         int i, eccsize = chip->ecc.size;
1569         int eccbytes = chip->ecc.bytes;
1570         int eccsteps = chip->ecc.steps;
1571         uint8_t *ecc_calc = chip->buffers->ecccalc;
1572         const uint8_t *p = buf;
1573         uint32_t *eccpos = chip->ecc.layout->eccpos;
1574
1575         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1576                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1577                 chip->write_buf(mtd, p, eccsize);
1578                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1579         }
1580
1581         for (i = 0; i < chip->ecc.total; i++)
1582                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1583
1584         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1585 }
1586
1587 /**
1588  * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1589  * @mtd:        mtd info structure
1590  * @chip:       nand chip info structure
1591  * @buf:        data buffer
1592  *
1593  * The hw generator calculates the error syndrome automatically. Therefor
1594  * we need a special oob layout and handling.
1595  */
1596 static void nand_write_page_syndrome(struct mtd_info *mtd,
1597                                     struct nand_chip *chip, const uint8_t *buf)
1598 {
1599         int i, eccsize = chip->ecc.size;
1600         int eccbytes = chip->ecc.bytes;
1601         int eccsteps = chip->ecc.steps;
1602         const uint8_t *p = buf;
1603         uint8_t *oob = chip->oob_poi;
1604
1605         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1606
1607                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1608                 chip->write_buf(mtd, p, eccsize);
1609
1610                 if (chip->ecc.prepad) {
1611                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1612                         oob += chip->ecc.prepad;
1613                 }
1614
1615                 chip->ecc.calculate(mtd, p, oob);
1616                 chip->write_buf(mtd, oob, eccbytes);
1617                 oob += eccbytes;
1618
1619                 if (chip->ecc.postpad) {
1620                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1621                         oob += chip->ecc.postpad;
1622                 }
1623         }
1624
1625         /* Calculate remaining oob bytes */
1626         i = mtd->oobsize - (oob - chip->oob_poi);
1627         if (i)
1628                 chip->write_buf(mtd, oob, i);
1629 }
1630
1631 /**
1632  * nand_write_page - [REPLACEABLE] write one page
1633  * @mtd:        MTD device structure
1634  * @chip:       NAND chip descriptor
1635  * @buf:        the data to write
1636  * @page:       page number to write
1637  * @cached:     cached programming
1638  * @raw:        use _raw version of write_page
1639  */
1640 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1641                            const uint8_t *buf, int page, int cached, int raw)
1642 {
1643         int status;
1644
1645         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1646
1647         if (unlikely(raw))
1648                 chip->ecc.write_page_raw(mtd, chip, buf);
1649         else
1650                 chip->ecc.write_page(mtd, chip, buf);
1651
1652         /*
1653          * Cached progamming disabled for now, Not sure if its worth the
1654          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1655          */
1656         cached = 0;
1657
1658         if (!cached || !(chip->options & NAND_CACHEPRG)) {
1659
1660                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1661                 status = chip->waitfunc(mtd, chip);
1662                 /*
1663                  * See if operation failed and additional status checks are
1664                  * available
1665                  */
1666                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1667                         status = chip->errstat(mtd, chip, FL_WRITING, status,
1668                                                page);
1669
1670                 if (status & NAND_STATUS_FAIL)
1671                         return -EIO;
1672         } else {
1673                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1674                 status = chip->waitfunc(mtd, chip);
1675         }
1676
1677 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1678         /* Send command to read back the data */
1679         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1680
1681         if (chip->verify_buf(mtd, buf, mtd->writesize))
1682                 return -EIO;
1683 #endif
1684         return 0;
1685 }
1686
1687 /**
1688  * nand_fill_oob - [Internal] Transfer client buffer to oob
1689  * @chip:       nand chip structure
1690  * @oob:        oob data buffer
1691  * @ops:        oob ops structure
1692  */
1693 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
1694                                   struct mtd_oob_ops *ops)
1695 {
1696         size_t len = ops->ooblen;
1697
1698         switch(ops->mode) {
1699
1700         case MTD_OOB_PLACE:
1701         case MTD_OOB_RAW:
1702                 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1703                 return oob + len;
1704
1705         case MTD_OOB_AUTO: {
1706                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1707                 uint32_t boffs = 0, woffs = ops->ooboffs;
1708                 size_t bytes = 0;
1709
1710                 for(; free->length && len; free++, len -= bytes) {
1711                         /* Write request not from offset 0 ? */
1712                         if (unlikely(woffs)) {
1713                                 if (woffs >= free->length) {
1714                                         woffs -= free->length;
1715                                         continue;
1716                                 }
1717                                 boffs = free->offset + woffs;
1718                                 bytes = min_t(size_t, len,
1719                                               (free->length - woffs));
1720                                 woffs = 0;
1721                         } else {
1722                                 bytes = min_t(size_t, len, free->length);
1723                                 boffs = free->offset;
1724                         }
1725                         memcpy(chip->oob_poi + boffs, oob, bytes);
1726                         oob += bytes;
1727                 }
1728                 return oob;
1729         }
1730         default:
1731                 BUG();
1732         }
1733         return NULL;
1734 }
1735
1736 #define NOTALIGNED(x)   (x & (chip->subpagesize - 1)) != 0
1737
1738 /**
1739  * nand_do_write_ops - [Internal] NAND write with ECC
1740  * @mtd:        MTD device structure
1741  * @to:         offset to write to
1742  * @ops:        oob operations description structure
1743  *
1744  * NAND write with ECC
1745  */
1746 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1747                              struct mtd_oob_ops *ops)
1748 {
1749         int chipnr, realpage, page, blockmask, column;
1750         struct nand_chip *chip = mtd->priv;
1751         uint32_t writelen = ops->len;
1752         uint8_t *oob = ops->oobbuf;
1753         uint8_t *buf = ops->datbuf;
1754         int ret, subpage;
1755
1756         ops->retlen = 0;
1757         if (!writelen)
1758                 return 0;
1759
1760         /* reject writes, which are not page aligned */
1761         if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
1762                 printk(KERN_NOTICE "nand_write: "
1763                        "Attempt to write not page aligned data\n");
1764                 return -EINVAL;
1765         }
1766
1767         column = to & (mtd->writesize - 1);
1768         subpage = column || (writelen & (mtd->writesize - 1));
1769
1770         if (subpage && oob)
1771                 return -EINVAL;
1772
1773         chipnr = (int)(to >> chip->chip_shift);
1774         chip->select_chip(mtd, chipnr);
1775
1776         /* Check, if it is write protected */
1777         if (nand_check_wp(mtd)) {
1778                 printk (KERN_NOTICE "nand_do_write_ops: Device is write protected\n");
1779                 return -EIO;
1780         }
1781
1782         realpage = (int)(to >> chip->page_shift);
1783         page = realpage & chip->pagemask;
1784         blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1785
1786         /* Invalidate the page cache, when we write to the cached page */
1787         if (to <= (chip->pagebuf << chip->page_shift) &&
1788             (chip->pagebuf << chip->page_shift) < (to + ops->len))
1789                 chip->pagebuf = -1;
1790
1791         /* If we're not given explicit OOB data, let it be 0xFF */
1792         if (likely(!oob))
1793                 memset(chip->oob_poi, 0xff, mtd->oobsize);
1794
1795         while(1) {
1796                 int bytes = mtd->writesize;
1797                 int cached = writelen > bytes && page != blockmask;
1798                 uint8_t *wbuf = buf;
1799
1800                 /* Partial page write ? */
1801                 if (unlikely(column || writelen < (mtd->writesize - 1))) {
1802                         cached = 0;
1803                         bytes = min_t(int, bytes - column, (int) writelen);
1804                         chip->pagebuf = -1;
1805                         memset(chip->buffers->databuf, 0xff, mtd->writesize);
1806                         memcpy(&chip->buffers->databuf[column], buf, bytes);
1807                         wbuf = chip->buffers->databuf;
1808                 }
1809
1810                 if (unlikely(oob))
1811                         oob = nand_fill_oob(chip, oob, ops);
1812
1813                 ret = chip->write_page(mtd, chip, wbuf, page, cached,
1814                                        (ops->mode == MTD_OOB_RAW));
1815                 if (ret)
1816                         break;
1817
1818                 writelen -= bytes;
1819                 if (!writelen)
1820                         break;
1821
1822                 column = 0;
1823                 buf += bytes;
1824                 realpage++;
1825
1826                 page = realpage & chip->pagemask;
1827                 /* Check, if we cross a chip boundary */
1828                 if (!page) {
1829                         chipnr++;
1830                         chip->select_chip(mtd, -1);
1831                         chip->select_chip(mtd, chipnr);
1832                 }
1833         }
1834
1835         ops->retlen = ops->len - writelen;
1836         if (unlikely(oob))
1837                 ops->oobretlen = ops->ooblen;
1838         return ret;
1839 }
1840
1841 /**
1842  * nand_write - [MTD Interface] NAND write with ECC
1843  * @mtd:        MTD device structure
1844  * @to:         offset to write to
1845  * @len:        number of bytes to write
1846  * @retlen:     pointer to variable to store the number of written bytes
1847  * @buf:        the data to write
1848  *
1849  * NAND write with ECC
1850  */
1851 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
1852                           size_t *retlen, const uint8_t *buf)
1853 {
1854         struct nand_chip *chip = mtd->priv;
1855         int ret;
1856
1857         /* Do not allow reads past end of device */
1858         if ((to + len) > mtd->size)
1859                 return -EINVAL;
1860         if (!len)
1861                 return 0;
1862
1863         nand_get_device(chip, mtd, FL_WRITING);
1864
1865         chip->ops.len = len;
1866         chip->ops.datbuf = (uint8_t *)buf;
1867         chip->ops.oobbuf = NULL;
1868
1869         ret = nand_do_write_ops(mtd, to, &chip->ops);
1870
1871         *retlen = chip->ops.retlen;
1872
1873         nand_release_device(mtd);
1874
1875         return ret;
1876 }
1877
1878 /**
1879  * nand_do_write_oob - [MTD Interface] NAND write out-of-band
1880  * @mtd:        MTD device structure
1881  * @to:         offset to write to
1882  * @ops:        oob operation description structure
1883  *
1884  * NAND write out-of-band
1885  */
1886 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
1887                              struct mtd_oob_ops *ops)
1888 {
1889         int chipnr, page, status, len;
1890         struct nand_chip *chip = mtd->priv;
1891
1892         MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n",
1893                   (unsigned int)to, (int)ops->ooblen);
1894
1895         if (ops->mode == MTD_OOB_AUTO)
1896                 len = chip->ecc.layout->oobavail;
1897         else
1898                 len = mtd->oobsize;
1899
1900         /* Do not allow write past end of page */
1901         if ((ops->ooboffs + ops->ooblen) > len) {
1902                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: "
1903                           "Attempt to write past end of page\n");
1904                 return -EINVAL;
1905         }
1906
1907         if (unlikely(ops->ooboffs >= len)) {
1908                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1909                           "Attempt to start write outside oob\n");
1910                 return -EINVAL;
1911         }
1912
1913         /* Do not allow reads past end of device */
1914         if (unlikely(to >= mtd->size ||
1915                      ops->ooboffs + ops->ooblen >
1916                         ((mtd->size >> chip->page_shift) -
1917                          (to >> chip->page_shift)) * len)) {
1918                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1919                           "Attempt write beyond end of device\n");
1920                 return -EINVAL;
1921         }
1922
1923         chipnr = (int)(to >> chip->chip_shift);
1924         chip->select_chip(mtd, chipnr);
1925
1926         /* Shift to get page */
1927         page = (int)(to >> chip->page_shift);
1928
1929         /*
1930          * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
1931          * of my DiskOnChip 2000 test units) will clear the whole data page too
1932          * if we don't do this. I have no clue why, but I seem to have 'fixed'
1933          * it in the doc2000 driver in August 1999.  dwmw2.
1934          */
1935         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1936
1937         /* Check, if it is write protected */
1938         if (nand_check_wp(mtd))
1939                 return -EROFS;
1940
1941         /* Invalidate the page cache, if we write to the cached page */
1942         if (page == chip->pagebuf)
1943                 chip->pagebuf = -1;
1944
1945         memset(chip->oob_poi, 0xff, mtd->oobsize);
1946         nand_fill_oob(chip, ops->oobbuf, ops);
1947         status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
1948         memset(chip->oob_poi, 0xff, mtd->oobsize);
1949
1950         if (status)
1951                 return status;
1952
1953         ops->oobretlen = ops->ooblen;
1954
1955         return 0;
1956 }
1957
1958 /**
1959  * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
1960  * @mtd:        MTD device structure
1961  * @to:         offset to write to
1962  * @ops:        oob operation description structure
1963  */
1964 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
1965                           struct mtd_oob_ops *ops)
1966 {
1967         struct nand_chip *chip = mtd->priv;
1968         int ret = -ENOTSUPP;
1969
1970         ops->retlen = 0;
1971
1972         /* Do not allow writes past end of device */
1973         if (ops->datbuf && (to + ops->len) > mtd->size) {
1974                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1975                           "Attempt read beyond end of device\n");
1976                 return -EINVAL;
1977         }
1978
1979         nand_get_device(chip, mtd, FL_WRITING);
1980
1981         switch(ops->mode) {
1982         case MTD_OOB_PLACE:
1983         case MTD_OOB_AUTO:
1984         case MTD_OOB_RAW:
1985                 break;
1986
1987         default:
1988                 goto out;
1989         }
1990
1991         if (!ops->datbuf)
1992                 ret = nand_do_write_oob(mtd, to, ops);
1993         else
1994                 ret = nand_do_write_ops(mtd, to, ops);
1995
1996  out:
1997         nand_release_device(mtd);
1998         return ret;
1999 }
2000
2001 /**
2002  * single_erease_cmd - [GENERIC] NAND standard block erase command function
2003  * @mtd:        MTD device structure
2004  * @page:       the page address of the block which will be erased
2005  *
2006  * Standard erase command for NAND chips
2007  */
2008 static void single_erase_cmd(struct mtd_info *mtd, int page)
2009 {
2010         struct nand_chip *chip = mtd->priv;
2011         /* Send commands to erase a block */
2012         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2013         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2014 }
2015
2016 /**
2017  * multi_erease_cmd - [GENERIC] AND specific block erase command function
2018  * @mtd:        MTD device structure
2019  * @page:       the page address of the block which will be erased
2020  *
2021  * AND multi block erase command function
2022  * Erase 4 consecutive blocks
2023  */
2024 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2025 {
2026         struct nand_chip *chip = mtd->priv;
2027         /* Send commands to erase a block */
2028         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2029         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2030         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2031         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2032         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2033 }
2034
2035 /**
2036  * nand_erase - [MTD Interface] erase block(s)
2037  * @mtd:        MTD device structure
2038  * @instr:      erase instruction
2039  *
2040  * Erase one ore more blocks
2041  */
2042 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2043 {
2044         return nand_erase_nand(mtd, instr, 0);
2045 }
2046
2047 #define BBT_PAGE_MASK   0xffffff3f
2048 /**
2049  * nand_erase_nand - [Internal] erase block(s)
2050  * @mtd:        MTD device structure
2051  * @instr:      erase instruction
2052  * @allowbbt:   allow erasing the bbt area
2053  *
2054  * Erase one ore more blocks
2055  */
2056 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2057                     int allowbbt)
2058 {
2059         int page, len, status, pages_per_block, ret, chipnr;
2060         struct nand_chip *chip = mtd->priv;
2061         int rewrite_bbt[NAND_MAX_CHIPS]={0};
2062         unsigned int bbt_masked_page = 0xffffffff;
2063
2064         MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n",
2065                   (unsigned int) instr->addr, (unsigned int) instr->len);
2066
2067         /* Start address must align on block boundary */
2068         if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
2069                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
2070                 return -EINVAL;
2071         }
2072
2073         /* Length must align on block boundary */
2074         if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
2075                 MTDDEBUG (MTD_DEBUG_LEVEL0,
2076                           "nand_erase: Length not block aligned\n");
2077                 return -EINVAL;
2078         }
2079
2080         /* Do not allow erase past end of device */
2081         if ((instr->len + instr->addr) > mtd->size) {
2082                 MTDDEBUG (MTD_DEBUG_LEVEL0,
2083                           "nand_erase: Erase past end of device\n");
2084                 return -EINVAL;
2085         }
2086
2087         instr->fail_addr = 0xffffffff;
2088
2089         /* Grab the lock and see if the device is available */
2090         nand_get_device(chip, mtd, FL_ERASING);
2091
2092         /* Shift to get first page */
2093         page = (int)(instr->addr >> chip->page_shift);
2094         chipnr = (int)(instr->addr >> chip->chip_shift);
2095
2096         /* Calculate pages in each block */
2097         pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2098
2099         /* Select the NAND device */
2100         chip->select_chip(mtd, chipnr);
2101
2102         /* Check, if it is write protected */
2103         if (nand_check_wp(mtd)) {
2104                 MTDDEBUG (MTD_DEBUG_LEVEL0,
2105                           "nand_erase: Device is write protected!!!\n");
2106                 instr->state = MTD_ERASE_FAILED;
2107                 goto erase_exit;
2108         }
2109
2110         /*
2111          * If BBT requires refresh, set the BBT page mask to see if the BBT
2112          * should be rewritten. Otherwise the mask is set to 0xffffffff which
2113          * can not be matched. This is also done when the bbt is actually
2114          * erased to avoid recusrsive updates
2115          */
2116         if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2117                 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2118
2119         /* Loop through the pages */
2120         len = instr->len;
2121
2122         instr->state = MTD_ERASING;
2123
2124         while (len) {
2125                 /*
2126                  * heck if we have a bad block, we do not erase bad blocks !
2127                  */
2128                 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2129                                         chip->page_shift, 0, allowbbt)) {
2130                         printk(KERN_WARNING "nand_erase: attempt to erase a "
2131                                "bad block at page 0x%08x\n", page);
2132                         instr->state = MTD_ERASE_FAILED;
2133                         goto erase_exit;
2134                 }
2135
2136                 /*
2137                  * Invalidate the page cache, if we erase the block which
2138                  * contains the current cached page
2139                  */
2140                 if (page <= chip->pagebuf && chip->pagebuf <
2141                     (page + pages_per_block))
2142                         chip->pagebuf = -1;
2143
2144                 chip->erase_cmd(mtd, page & chip->pagemask);
2145
2146                 status = chip->waitfunc(mtd, chip);
2147
2148                 /*
2149                  * See if operation failed and additional status checks are
2150                  * available
2151                  */
2152                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2153                         status = chip->errstat(mtd, chip, FL_ERASING,
2154                                                status, page);
2155
2156                 /* See if block erase succeeded */
2157                 if (status & NAND_STATUS_FAIL) {
2158                         MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: "
2159                                   "Failed erase, page 0x%08x\n", page);
2160                         instr->state = MTD_ERASE_FAILED;
2161                         instr->fail_addr = (page << chip->page_shift);
2162                         goto erase_exit;
2163                 }
2164
2165                 /*
2166                  * If BBT requires refresh, set the BBT rewrite flag to the
2167                  * page being erased
2168                  */
2169                 if (bbt_masked_page != 0xffffffff &&
2170                     (page & BBT_PAGE_MASK) == bbt_masked_page)
2171                             rewrite_bbt[chipnr] = (page << chip->page_shift);
2172
2173                 /* Increment page address and decrement length */
2174                 len -= (1 << chip->phys_erase_shift);
2175                 page += pages_per_block;
2176
2177                 /* Check, if we cross a chip boundary */
2178                 if (len && !(page & chip->pagemask)) {
2179                         chipnr++;
2180                         chip->select_chip(mtd, -1);
2181                         chip->select_chip(mtd, chipnr);
2182
2183                         /*
2184                          * If BBT requires refresh and BBT-PERCHIP, set the BBT
2185                          * page mask to see if this BBT should be rewritten
2186                          */
2187                         if (bbt_masked_page != 0xffffffff &&
2188                             (chip->bbt_td->options & NAND_BBT_PERCHIP))
2189                                 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2190                                         BBT_PAGE_MASK;
2191                 }
2192         }
2193         instr->state = MTD_ERASE_DONE;
2194
2195  erase_exit:
2196
2197         ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2198         /* Do call back function */
2199         if (!ret)
2200                 mtd_erase_callback(instr);
2201
2202         /* Deselect and wake up anyone waiting on the device */
2203         nand_release_device(mtd);
2204
2205         /*
2206          * If BBT requires refresh and erase was successful, rewrite any
2207          * selected bad block tables
2208          */
2209         if (bbt_masked_page == 0xffffffff || ret)
2210                 return ret;
2211
2212         for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2213                 if (!rewrite_bbt[chipnr])
2214                         continue;
2215                 /* update the BBT for chip */
2216                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
2217                           "(%d:0x%0x 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
2218                           chip->bbt_td->pages[chipnr]);
2219                 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2220         }
2221
2222         /* Return more or less happy */
2223         return ret;
2224 }
2225
2226 /**
2227  * nand_sync - [MTD Interface] sync
2228  * @mtd:        MTD device structure
2229  *
2230  * Sync is actually a wait for chip ready function
2231  */
2232 static void nand_sync(struct mtd_info *mtd)
2233 {
2234         struct nand_chip *chip = mtd->priv;
2235
2236         MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_sync: called\n");
2237
2238         /* Grab the lock and see if the device is available */
2239         nand_get_device(chip, mtd, FL_SYNCING);
2240         /* Release it and go back */
2241         nand_release_device(mtd);
2242 }
2243
2244 /**
2245  * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2246  * @mtd:        MTD device structure
2247  * @offs:       offset relative to mtd start
2248  */
2249 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2250 {
2251         /* Check for invalid offset */
2252         if (offs > mtd->size)
2253                 return -EINVAL;
2254
2255         return nand_block_checkbad(mtd, offs, 1, 0);
2256 }
2257
2258 /**
2259  * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2260  * @mtd:        MTD device structure
2261  * @ofs:        offset relative to mtd start
2262  */
2263 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2264 {
2265         struct nand_chip *chip = mtd->priv;
2266         int ret;
2267
2268         if ((ret = nand_block_isbad(mtd, ofs))) {
2269                 /* If it was bad already, return success and do nothing. */
2270                 if (ret > 0)
2271                         return 0;
2272                 return ret;
2273         }
2274
2275         return chip->block_markbad(mtd, ofs);
2276 }
2277
2278 /**
2279  * nand_suspend - [MTD Interface] Suspend the NAND flash
2280  * @mtd:        MTD device structure
2281  */
2282 static int nand_suspend(struct mtd_info *mtd)
2283 {
2284         struct nand_chip *chip = mtd->priv;
2285
2286         return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2287 }
2288
2289 /**
2290  * nand_resume - [MTD Interface] Resume the NAND flash
2291  * @mtd:        MTD device structure
2292  */
2293 static void nand_resume(struct mtd_info *mtd)
2294 {
2295         struct nand_chip *chip = mtd->priv;
2296
2297         if (chip->state == FL_PM_SUSPENDED)
2298                 nand_release_device(mtd);
2299         else
2300                 printk(KERN_ERR "nand_resume() called for a chip which is not "
2301                        "in suspended state\n");
2302 }
2303
2304 /*
2305  * Set default functions
2306  */
2307 static void nand_set_defaults(struct nand_chip *chip, int busw)
2308 {
2309         /* check for proper chip_delay setup, set 20us if not */
2310         if (!chip->chip_delay)
2311                 chip->chip_delay = 20;
2312
2313         /* check, if a user supplied command function given */
2314         if (chip->cmdfunc == NULL)
2315                 chip->cmdfunc = nand_command;
2316
2317         /* check, if a user supplied wait function given */
2318         if (chip->waitfunc == NULL)
2319                 chip->waitfunc = nand_wait;
2320
2321         if (!chip->select_chip)
2322                 chip->select_chip = nand_select_chip;
2323         if (!chip->read_byte)
2324                 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2325         if (!chip->read_word)
2326                 chip->read_word = nand_read_word;
2327         if (!chip->block_bad)
2328                 chip->block_bad = nand_block_bad;
2329         if (!chip->block_markbad)
2330                 chip->block_markbad = nand_default_block_markbad;
2331         if (!chip->write_buf)
2332                 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2333         if (!chip->read_buf)
2334                 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2335         if (!chip->verify_buf)
2336                 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2337         if (!chip->scan_bbt)
2338                 chip->scan_bbt = nand_default_bbt;
2339
2340         if (!chip->controller) {
2341                 chip->controller = &chip->hwcontrol;
2342
2343                 /* XXX U-BOOT XXX */
2344 #if 0
2345                 spin_lock_init(&chip->controller->lock);
2346                 init_waitqueue_head(&chip->controller->wq);
2347 #endif
2348         }
2349
2350 }
2351
2352 /*
2353  * Get the flash and manufacturer id and lookup if the type is supported
2354  */
2355 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2356                                                   struct nand_chip *chip,
2357                                                   int busw, int *maf_id)
2358 {
2359         struct nand_flash_dev *type = NULL;
2360         int i, dev_id, maf_idx;
2361
2362         /* Select the device */
2363         chip->select_chip(mtd, 0);
2364
2365         /* Send the command for reading device ID */
2366         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2367
2368         /* Read manufacturer and device IDs */
2369         *maf_id = chip->read_byte(mtd);
2370         dev_id = chip->read_byte(mtd);
2371
2372         /* Lookup the flash id */
2373         for (i = 0; nand_flash_ids[i].name != NULL; i++) {
2374                 if (dev_id == nand_flash_ids[i].id) {
2375                         type =  &nand_flash_ids[i];
2376                         break;
2377                 }
2378         }
2379
2380         if (!type)
2381                 return ERR_PTR(-ENODEV);
2382
2383         if (!mtd->name)
2384                 mtd->name = type->name;
2385
2386         chip->chipsize = type->chipsize << 20;
2387
2388         /* Newer devices have all the information in additional id bytes */
2389         if (!type->pagesize) {
2390                 int extid;
2391                 /* The 3rd id byte holds MLC / multichip data */
2392                 chip->cellinfo = chip->read_byte(mtd);
2393                 /* The 4th id byte is the important one */
2394                 extid = chip->read_byte(mtd);
2395                 /* Calc pagesize */
2396                 mtd->writesize = 1024 << (extid & 0x3);
2397                 extid >>= 2;
2398                 /* Calc oobsize */
2399                 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
2400                 extid >>= 2;
2401                 /* Calc blocksize. Blocksize is multiples of 64KiB */
2402                 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2403                 extid >>= 2;
2404                 /* Get buswidth information */
2405                 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2406
2407         } else {
2408                 /*
2409                  * Old devices have chip data hardcoded in the device id table
2410                  */
2411                 mtd->erasesize = type->erasesize;
2412                 mtd->writesize = type->pagesize;
2413                 mtd->oobsize = mtd->writesize / 32;
2414                 busw = type->options & NAND_BUSWIDTH_16;
2415         }
2416
2417         /* Try to identify manufacturer */
2418         for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2419                 if (nand_manuf_ids[maf_idx].id == *maf_id)
2420                         break;
2421         }
2422
2423         /*
2424          * Check, if buswidth is correct. Hardware drivers should set
2425          * chip correct !
2426          */
2427         if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2428                 printk(KERN_INFO "NAND device: Manufacturer ID:"
2429                        " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2430                        dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2431                 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2432                        (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2433                        busw ? 16 : 8);
2434                 return ERR_PTR(-EINVAL);
2435         }
2436
2437         /* Calculate the address shift from the page size */
2438         chip->page_shift = ffs(mtd->writesize) - 1;
2439         /* Convert chipsize to number of pages per chip -1. */
2440         chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2441
2442         chip->bbt_erase_shift = chip->phys_erase_shift =
2443                 ffs(mtd->erasesize) - 1;
2444         chip->chip_shift = ffs(chip->chipsize) - 1;
2445
2446         /* Set the bad block position */
2447         chip->badblockpos = mtd->writesize > 512 ?
2448                 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2449
2450         /* Get chip options, preserve non chip based options */
2451         chip->options &= ~NAND_CHIPOPTIONS_MSK;
2452         chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
2453
2454         /*
2455          * Set chip as a default. Board drivers can override it, if necessary
2456          */
2457         chip->options |= NAND_NO_AUTOINCR;
2458
2459         /* Check if chip is a not a samsung device. Do not clear the
2460          * options for chips which are not having an extended id.
2461          */
2462         if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2463                 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2464
2465         /* Check for AND chips with 4 page planes */
2466         if (chip->options & NAND_4PAGE_ARRAY)
2467                 chip->erase_cmd = multi_erase_cmd;
2468         else
2469                 chip->erase_cmd = single_erase_cmd;
2470
2471         /* Do not replace user supplied command function ! */
2472         if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2473                 chip->cmdfunc = nand_command_lp;
2474
2475         MTDDEBUG (MTD_DEBUG_LEVEL0, "NAND device: Manufacturer ID:"
2476                   " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2477                   nand_manuf_ids[maf_idx].name, type->name);
2478
2479         return type;
2480 }
2481
2482 /**
2483  * nand_scan_ident - [NAND Interface] Scan for the NAND device
2484  * @mtd:             MTD device structure
2485  * @maxchips:        Number of chips to scan for
2486  *
2487  * This is the first phase of the normal nand_scan() function. It
2488  * reads the flash ID and sets up MTD fields accordingly.
2489  *
2490  * The mtd->owner field must be set to the module of the caller.
2491  */
2492 int nand_scan_ident(struct mtd_info *mtd, int maxchips)
2493 {
2494         int i, busw, nand_maf_id;
2495         struct nand_chip *chip = mtd->priv;
2496         struct nand_flash_dev *type;
2497
2498         /* Get buswidth to select the correct functions */
2499         busw = chip->options & NAND_BUSWIDTH_16;
2500         /* Set the default functions */
2501         nand_set_defaults(chip, busw);
2502
2503         /* Read the flash type */
2504         type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
2505
2506         if (IS_ERR(type)) {
2507                 printk(KERN_WARNING "No NAND device found!!!\n");
2508                 chip->select_chip(mtd, -1);
2509                 return PTR_ERR(type);
2510         }
2511
2512         /* Check for a chip array */
2513         for (i = 1; i < maxchips; i++) {
2514                 chip->select_chip(mtd, i);
2515                 /* Send the command for reading device ID */
2516                 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2517                 /* Read manufacturer and device IDs */
2518                 if (nand_maf_id != chip->read_byte(mtd) ||
2519                     type->id != chip->read_byte(mtd))
2520                         break;
2521         }
2522         if (i > 1)
2523                 printk(KERN_INFO "%d NAND chips detected\n", i);
2524
2525         /* Store the number of chips and calc total size for mtd */
2526         chip->numchips = i;
2527         mtd->size = i * chip->chipsize;
2528
2529         return 0;
2530 }
2531
2532
2533 /**
2534  * nand_scan_tail - [NAND Interface] Scan for the NAND device
2535  * @mtd:            MTD device structure
2536  * @maxchips:       Number of chips to scan for
2537  *
2538  * This is the second phase of the normal nand_scan() function. It
2539  * fills out all the uninitialized function pointers with the defaults
2540  * and scans for a bad block table if appropriate.
2541  */
2542 int nand_scan_tail(struct mtd_info *mtd)
2543 {
2544         int i;
2545         struct nand_chip *chip = mtd->priv;
2546
2547         if (!(chip->options & NAND_OWN_BUFFERS))
2548                 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2549         if (!chip->buffers)
2550                 return -ENOMEM;
2551
2552         /* Set the internal oob buffer location, just after the page data */
2553         chip->oob_poi = chip->buffers->databuf + mtd->writesize;
2554
2555         /*
2556          * If no default placement scheme is given, select an appropriate one
2557          */
2558         if (!chip->ecc.layout) {
2559                 switch (mtd->oobsize) {
2560                 case 8:
2561                         chip->ecc.layout = &nand_oob_8;
2562                         break;
2563                 case 16:
2564                         chip->ecc.layout = &nand_oob_16;
2565                         break;
2566                 case 64:
2567                         chip->ecc.layout = &nand_oob_64;
2568                         break;
2569                 case 128:
2570                         chip->ecc.layout = &nand_oob_128;
2571                         break;
2572                 default:
2573                         printk(KERN_WARNING "No oob scheme defined for "
2574                                "oobsize %d\n", mtd->oobsize);
2575 /*                      BUG(); */
2576                 }
2577         }
2578
2579         if (!chip->write_page)
2580                 chip->write_page = nand_write_page;
2581
2582         /*
2583          * check ECC mode, default to software if 3byte/512byte hardware ECC is
2584          * selected and we have 256 byte pagesize fallback to software ECC
2585          */
2586         if (!chip->ecc.read_page_raw)
2587                 chip->ecc.read_page_raw = nand_read_page_raw;
2588         if (!chip->ecc.write_page_raw)
2589                 chip->ecc.write_page_raw = nand_write_page_raw;
2590
2591         switch (chip->ecc.mode) {
2592         case NAND_ECC_HW:
2593                 /* Use standard hwecc read page function ? */
2594                 if (!chip->ecc.read_page)
2595                         chip->ecc.read_page = nand_read_page_hwecc;
2596                 if (!chip->ecc.write_page)
2597                         chip->ecc.write_page = nand_write_page_hwecc;
2598                 if (!chip->ecc.read_oob)
2599                         chip->ecc.read_oob = nand_read_oob_std;
2600                 if (!chip->ecc.write_oob)
2601                         chip->ecc.write_oob = nand_write_oob_std;
2602
2603         case NAND_ECC_HW_SYNDROME:
2604                 if ((!chip->ecc.calculate || !chip->ecc.correct ||
2605                      !chip->ecc.hwctl) &&
2606                     (!chip->ecc.read_page ||
2607                      chip->ecc.read_page == nand_read_page_hwecc ||
2608                      !chip->ecc.write_page ||
2609                      chip->ecc.write_page == nand_write_page_hwecc)) {
2610                         printk(KERN_WARNING "No ECC functions supplied, "
2611                                "Hardware ECC not possible\n");
2612                         BUG();
2613                 }
2614                 /* Use standard syndrome read/write page function ? */
2615                 if (!chip->ecc.read_page)
2616                         chip->ecc.read_page = nand_read_page_syndrome;
2617                 if (!chip->ecc.write_page)
2618                         chip->ecc.write_page = nand_write_page_syndrome;
2619                 if (!chip->ecc.read_oob)
2620                         chip->ecc.read_oob = nand_read_oob_syndrome;
2621                 if (!chip->ecc.write_oob)
2622                         chip->ecc.write_oob = nand_write_oob_syndrome;
2623
2624                 if (mtd->writesize >= chip->ecc.size)
2625                         break;
2626                 printk(KERN_WARNING "%d byte HW ECC not possible on "
2627                        "%d byte page size, fallback to SW ECC\n",
2628                        chip->ecc.size, mtd->writesize);
2629                 chip->ecc.mode = NAND_ECC_SOFT;
2630
2631         case NAND_ECC_SOFT:
2632                 chip->ecc.calculate = nand_calculate_ecc;
2633                 chip->ecc.correct = nand_correct_data;
2634                 chip->ecc.read_page = nand_read_page_swecc;
2635                 chip->ecc.write_page = nand_write_page_swecc;
2636                 chip->ecc.read_oob = nand_read_oob_std;
2637                 chip->ecc.write_oob = nand_write_oob_std;
2638                 chip->ecc.size = 256;
2639                 chip->ecc.bytes = 3;
2640                 break;
2641
2642         case NAND_ECC_NONE:
2643                 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2644                        "This is not recommended !!\n");
2645                 chip->ecc.read_page = nand_read_page_raw;
2646                 chip->ecc.write_page = nand_write_page_raw;
2647                 chip->ecc.read_oob = nand_read_oob_std;
2648                 chip->ecc.write_oob = nand_write_oob_std;
2649                 chip->ecc.size = mtd->writesize;
2650                 chip->ecc.bytes = 0;
2651                 break;
2652
2653         default:
2654                 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
2655                        chip->ecc.mode);
2656                 BUG();
2657         }
2658
2659         /*
2660          * The number of bytes available for a client to place data into
2661          * the out of band area
2662          */
2663         chip->ecc.layout->oobavail = 0;
2664         for (i = 0; chip->ecc.layout->oobfree[i].length; i++)
2665                 chip->ecc.layout->oobavail +=
2666                         chip->ecc.layout->oobfree[i].length;
2667         mtd->oobavail = chip->ecc.layout->oobavail;
2668
2669         /*
2670          * Set the number of read / write steps for one page depending on ECC
2671          * mode
2672          */
2673         chip->ecc.steps = mtd->writesize / chip->ecc.size;
2674         if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
2675                 printk(KERN_WARNING "Invalid ecc parameters\n");
2676                 BUG();
2677         }
2678         chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
2679
2680         /*
2681          * Allow subpage writes up to ecc.steps. Not possible for MLC
2682          * FLASH.
2683          */
2684         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2685             !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
2686                 switch(chip->ecc.steps) {
2687                 case 2:
2688                         mtd->subpage_sft = 1;
2689                         break;
2690                 case 4:
2691                 case 8:
2692                         mtd->subpage_sft = 2;
2693                         break;
2694                 }
2695         }
2696         chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
2697
2698         /* Initialize state */
2699         chip->state = FL_READY;
2700
2701         /* De-select the device */
2702         chip->select_chip(mtd, -1);
2703
2704         /* Invalidate the pagebuffer reference */
2705         chip->pagebuf = -1;
2706
2707         /* Fill in remaining MTD driver data */
2708         mtd->type = MTD_NANDFLASH;
2709         mtd->flags = MTD_CAP_NANDFLASH;
2710         mtd->erase = nand_erase;
2711         mtd->point = NULL;
2712         mtd->unpoint = NULL;
2713         mtd->read = nand_read;
2714         mtd->write = nand_write;
2715         mtd->read_oob = nand_read_oob;
2716         mtd->write_oob = nand_write_oob;
2717         mtd->sync = nand_sync;
2718         mtd->lock = NULL;
2719         mtd->unlock = NULL;
2720         mtd->suspend = nand_suspend;
2721         mtd->resume = nand_resume;
2722         mtd->block_isbad = nand_block_isbad;
2723         mtd->block_markbad = nand_block_markbad;
2724
2725         /* propagate ecc.layout to mtd_info */
2726         mtd->ecclayout = chip->ecc.layout;
2727
2728         /* Check, if we should skip the bad block table scan */
2729         if (chip->options & NAND_SKIP_BBTSCAN)
2730                 chip->options |= NAND_BBT_SCANNED;
2731
2732         return 0;
2733 }
2734
2735 /* module_text_address() isn't exported, and it's mostly a pointless
2736    test if this is a module _anyway_ -- they'd have to try _really_ hard
2737    to call us from in-kernel code if the core NAND support is modular. */
2738 #ifdef MODULE
2739 #define caller_is_module() (1)
2740 #else
2741 #define caller_is_module() \
2742         module_text_address((unsigned long)__builtin_return_address(0))
2743 #endif
2744
2745 /**
2746  * nand_scan - [NAND Interface] Scan for the NAND device
2747  * @mtd:        MTD device structure
2748  * @maxchips:   Number of chips to scan for
2749  *
2750  * This fills out all the uninitialized function pointers
2751  * with the defaults.
2752  * The flash ID is read and the mtd/chip structures are
2753  * filled with the appropriate values.
2754  * The mtd->owner field must be set to the module of the caller
2755  *
2756  */
2757 int nand_scan(struct mtd_info *mtd, int maxchips)
2758 {
2759         int ret;
2760
2761         /* Many callers got this wrong, so check for it for a while... */
2762         /* XXX U-BOOT XXX */
2763 #if 0
2764         if (!mtd->owner && caller_is_module()) {
2765                 printk(KERN_CRIT "nand_scan() called with NULL mtd->owner!\n");
2766                 BUG();
2767         }
2768 #endif
2769
2770         ret = nand_scan_ident(mtd, maxchips);
2771         if (!ret)
2772                 ret = nand_scan_tail(mtd);
2773         return ret;
2774 }
2775
2776 /**
2777  * nand_release - [NAND Interface] Free resources held by the NAND device
2778  * @mtd:        MTD device structure
2779 */
2780 void nand_release(struct mtd_info *mtd)
2781 {
2782         struct nand_chip *chip = mtd->priv;
2783
2784 #ifdef CONFIG_MTD_PARTITIONS
2785         /* Deregister partitions */
2786         del_mtd_partitions(mtd);
2787 #endif
2788         /* Deregister the device */
2789         /* XXX U-BOOT XXX */
2790 #if 0
2791         del_mtd_device(mtd);
2792 #endif
2793
2794         /* Free bad block table memory */
2795         kfree(chip->bbt);
2796         if (!(chip->options & NAND_OWN_BUFFERS))
2797                 kfree(chip->buffers);
2798 }
2799
2800 /* XXX U-BOOT XXX */
2801 #if 0
2802 EXPORT_SYMBOL_GPL(nand_scan);
2803 EXPORT_SYMBOL_GPL(nand_scan_ident);
2804 EXPORT_SYMBOL_GPL(nand_scan_tail);
2805 EXPORT_SYMBOL_GPL(nand_release);
2806
2807 static int __init nand_base_init(void)
2808 {
2809         led_trigger_register_simple("nand-disk", &nand_led_trigger);
2810         return 0;
2811 }
2812
2813 static void __exit nand_base_exit(void)
2814 {
2815         led_trigger_unregister_simple(nand_led_trigger);
2816 }
2817
2818 module_init(nand_base_init);
2819 module_exit(nand_base_exit);
2820
2821 MODULE_LICENSE("GPL");
2822 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
2823 MODULE_DESCRIPTION("Generic NAND flash driver code");
2824 #endif
2825
2826 #endif
2827