5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
9 * Additional technical information is available on
10 * http://www.linux-mtd.infradead.org/doc/nand.html
12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
16 * David Woodhouse for adding multichip support
18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ecc support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
27 * BBT table is not serialized, has to be fixed
29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
37 #define ENOTSUPP 524 /* Operation is not supported */
41 #include <linux/err.h>
42 #include <linux/mtd/compat.h>
43 #include <linux/mtd/mtd.h>
44 #include <linux/mtd/nand.h>
45 #include <linux/mtd/nand_ecc.h>
47 #ifdef CONFIG_MTD_PARTITIONS
48 #include <linux/mtd/partitions.h>
52 #include <asm/errno.h>
55 * CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting
56 * a flash. NAND flash is initialized prior to interrupts so standard timers
57 * can't be used. CONFIG_SYS_NAND_RESET_CNT should be set to a value
58 * which is greater than (max NAND reset time / NAND status read time).
59 * A conservative default of 200000 (500 us / 25 ns) is used as a default.
61 #ifndef CONFIG_SYS_NAND_RESET_CNT
62 #define CONFIG_SYS_NAND_RESET_CNT 200000
65 /* Define default oob placement schemes for large and small page devices */
66 static struct nand_ecclayout nand_oob_8 = {
76 static struct nand_ecclayout nand_oob_16 = {
78 .eccpos = {0, 1, 2, 3, 6, 7},
84 static struct nand_ecclayout nand_oob_64 = {
87 40, 41, 42, 43, 44, 45, 46, 47,
88 48, 49, 50, 51, 52, 53, 54, 55,
89 56, 57, 58, 59, 60, 61, 62, 63},
95 static struct nand_ecclayout nand_oob_128 = {
98 80, 81, 82, 83, 84, 85, 86, 87,
99 88, 89, 90, 91, 92, 93, 94, 95,
100 96, 97, 98, 99, 100, 101, 102, 103,
101 104, 105, 106, 107, 108, 109, 110, 111,
102 112, 113, 114, 115, 116, 117, 118, 119,
103 120, 121, 122, 123, 124, 125, 126, 127},
110 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
113 int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
114 struct mtd_oob_ops *ops);
116 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this);
119 * nand_release_device - [GENERIC] release chip
120 * @mtd: MTD device structure
122 * Deselect, release chip lock and wake up anyone waiting on the device
124 static void nand_release_device (struct mtd_info *mtd)
126 struct nand_chip *this = mtd->priv;
127 this->select_chip(mtd, -1); /* De-select the NAND device */
131 * nand_read_byte - [DEFAULT] read one byte from the chip
132 * @mtd: MTD device structure
134 * Default read function for 8bit buswith
136 static uint8_t nand_read_byte(struct mtd_info *mtd)
138 struct nand_chip *chip = mtd->priv;
139 return readb(chip->IO_ADDR_R);
143 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
144 * @mtd: MTD device structure
146 * Default read function for 16bit buswith with
147 * endianess conversion
149 static uint8_t nand_read_byte16(struct mtd_info *mtd)
151 struct nand_chip *chip = mtd->priv;
153 #ifdef CONFIG_MTD_NAND_SPRD
154 return (uint8_t)readl(chip->IO_ADDR_R);
156 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
161 * nand_read_word - [DEFAULT] read one word from the chip
162 * @mtd: MTD device structure
164 * Default read function for 16bit buswith without
165 * endianess conversion
167 static u16 nand_read_word(struct mtd_info *mtd)
169 struct nand_chip *chip = mtd->priv;
170 return readw(chip->IO_ADDR_R);
174 * nand_select_chip - [DEFAULT] control CE line
175 * @mtd: MTD device structure
176 * @chipnr: chipnumber to select, -1 for deselect
178 * Default select function for 1 chip devices.
180 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
182 struct nand_chip *chip = mtd->priv;
186 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
197 * nand_write_buf - [DEFAULT] write buffer to chip
198 * @mtd: MTD device structure
200 * @len: number of bytes to write
202 * Default write function for 8bit buswith
204 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
207 struct nand_chip *chip = mtd->priv;
209 #ifdef CONFIG_MTD_NAND_SPRD
210 memcpy(chip->IO_ADDR_W, buf, len);
212 for (i = 0; i < len; i++)
213 writeb(buf[i], chip->IO_ADDR_W);
218 * nand_read_buf - [DEFAULT] read chip data into buffer
219 * @mtd: MTD device structure
220 * @buf: buffer to store date
221 * @len: number of bytes to read
223 * Default read function for 8bit buswith
225 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
228 struct nand_chip *chip = mtd->priv;
230 #ifdef CONFIG_MTD_NAND_SPRD
231 memcpy(buf, chip->IO_ADDR_R, len);
233 for (i = 0; i < len; i++)
234 buf[i] = readb(chip->IO_ADDR_R);
239 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
240 * @mtd: MTD device structure
241 * @buf: buffer containing the data to compare
242 * @len: number of bytes to compare
244 * Default verify function for 8bit buswith
246 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
249 struct nand_chip *chip = mtd->priv;
251 for (i = 0; i < len; i++)
252 if (buf[i] != readb(chip->IO_ADDR_R))
258 * nand_write_buf16 - [DEFAULT] write buffer to chip
259 * @mtd: MTD device structure
261 * @len: number of bytes to write
263 * Default write function for 16bit buswith
265 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
268 struct nand_chip *chip = mtd->priv;
270 #ifdef CONFIG_MTD_NAND_SPRD
271 memcpy(chip->IO_ADDR_W, buf, len);
273 u16 *p = (u16 *) buf;
276 for (i = 0; i < len; i++)
277 writew(p[i], chip->IO_ADDR_W);
282 * nand_read_buf16 - [DEFAULT] read chip data into buffer
283 * @mtd: MTD device structure
284 * @buf: buffer to store date
285 * @len: number of bytes to read
287 * Default read function for 16bit buswith
289 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
292 struct nand_chip *chip = mtd->priv;
294 #ifdef CONFIG_MTD_NAND_SPRD
295 memcpy(buf, chip->IO_ADDR_R, len);
297 u16 *p = (u16 *) buf;
300 for (i = 0; i < len; i++)
301 p[i] = readw(chip->IO_ADDR_R);
306 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
307 * @mtd: MTD device structure
308 * @buf: buffer containing the data to compare
309 * @len: number of bytes to compare
311 * Default verify function for 16bit buswith
313 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
316 struct nand_chip *chip = mtd->priv;
317 u16 *p = (u16 *) buf;
320 for (i = 0; i < len; i++)
321 if (p[i] != readw((uint16_t *)chip->IO_ADDR_R + i))
328 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
329 * @mtd: MTD device structure
330 * @ofs: offset from device start
331 * @getchip: 0, if the chip is already selected
333 * Check, if the block is bad.
335 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
337 int page, chipnr, res = 0;
338 struct nand_chip *chip = mtd->priv;
341 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
344 chipnr = (int)(ofs >> chip->chip_shift);
346 nand_get_device(chip, mtd, FL_READING);
348 /* Select the NAND device */
349 chip->select_chip(mtd, chipnr);
352 if (chip->options & NAND_BUSWIDTH_16) {
353 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
355 bad = cpu_to_le16(chip->read_word(mtd));
356 if (chip->badblockpos & 0x1)
358 if ((bad & 0xFF) != 0xff)
361 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
362 if (chip->read_byte(mtd) != 0xff)
367 nand_release_device(mtd);
373 * nand_default_block_markbad - [DEFAULT] mark a block bad
374 * @mtd: MTD device structure
375 * @ofs: offset from device start
377 * This is the default implementation, which can be overridden by
378 * a hardware specific driver.
380 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
382 struct nand_chip *chip = mtd->priv;
383 uint8_t buf[2] = { 0x55, 0xaa };
385 #ifndef CONFIG_MTD_NAND_SC8810
386 mtd_oob_mode_t sprd_mode;
388 /* Get block number */
389 block = (int)(ofs >> chip->bbt_erase_shift);
391 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
393 /* Do we have a flash based bad block table ? */
394 if (chip->options & NAND_USE_FLASH_BBT)
395 ret = nand_update_bbt(mtd, ofs);
397 /* We write two bytes, so we dont have to mess with 16 bit
400 nand_get_device(chip, mtd, FL_WRITING);
402 chip->ops.len = chip->ops.ooblen = 2;
403 chip->ops.datbuf = NULL;
404 chip->ops.oobbuf = buf;
405 chip->ops.ooboffs = chip->badblockpos & ~0x01;
407 #ifndef CONFIG_MTD_NAND_SC8810
408 sprd_mode = chip->ops.mode;
409 if (chip->ops.mode == MTD_OOB_AUTO)
410 chip->ops.mode = MTD_OOB_RAW;
412 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
414 #ifndef CONFIG_MTD_NAND_SC8810
415 chip->ops.mode = sprd_mode;
417 nand_release_device(mtd);
420 mtd->ecc_stats.badblocks++;
426 * nand_check_wp - [GENERIC] check if the chip is write protected
427 * @mtd: MTD device structure
428 * Check, if the device is write protected
430 * The function expects, that the device is already selected
432 static int nand_check_wp(struct mtd_info *mtd)
434 struct nand_chip *chip = mtd->priv;
435 /* Check the WP bit */
436 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
437 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
441 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
442 * @mtd: MTD device structure
443 * @ofs: offset from device start
444 * @getchip: 0, if the chip is already selected
445 * @allowbbt: 1, if its allowed to access the bbt area
447 * Check, if the block is bad. Either by reading the bad block table or
448 * calling of the scan function.
450 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
453 struct nand_chip *chip = mtd->priv;
455 if (!(chip->options & NAND_BBT_SCANNED)) {
456 chip->options |= NAND_BBT_SCANNED;
457 #ifdef SPRD_EVM_TAG_ON
461 #ifdef SPRD_EVM_TAG_ON
467 return chip->block_bad(mtd, ofs, getchip);
469 /* Return info from the table */
470 return nand_isbad_bbt(mtd, ofs, allowbbt);
474 * Wait for the ready pin, after a command
475 * The timeout is catched later.
477 void nand_wait_ready(struct mtd_info *mtd)
479 struct nand_chip *chip = mtd->priv;
480 u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
484 /* wait until command is processed or timeout occures */
485 while (get_timer(0) < timeo) {
487 if (chip->dev_ready(mtd))
493 * nand_command - [DEFAULT] Send command to NAND device
494 * @mtd: MTD device structure
495 * @command: the command to be sent
496 * @column: the column address for this command, -1 if none
497 * @page_addr: the page address for this command, -1 if none
499 * Send command to NAND device. This function is used for small page
500 * devices (256/512 Bytes per page)
502 static void nand_command(struct mtd_info *mtd, unsigned int command,
503 int column, int page_addr)
505 register struct nand_chip *chip = mtd->priv;
506 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
507 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
510 * Write out the command to the device.
512 if (command == NAND_CMD_SEQIN) {
515 if (column >= mtd->writesize) {
517 column -= mtd->writesize;
518 readcmd = NAND_CMD_READOOB;
519 } else if (column < 256) {
520 /* First 256 bytes --> READ0 */
521 readcmd = NAND_CMD_READ0;
524 readcmd = NAND_CMD_READ1;
526 chip->cmd_ctrl(mtd, readcmd, ctrl);
527 ctrl &= ~NAND_CTRL_CHANGE;
529 chip->cmd_ctrl(mtd, command, ctrl);
532 * Address cycle, when necessary
534 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
535 /* Serially input address */
537 /* Adjust columns for 16 bit buswidth */
538 if (chip->options & NAND_BUSWIDTH_16)
540 chip->cmd_ctrl(mtd, column, ctrl);
541 ctrl &= ~NAND_CTRL_CHANGE;
543 if (page_addr != -1) {
544 chip->cmd_ctrl(mtd, page_addr, ctrl);
545 ctrl &= ~NAND_CTRL_CHANGE;
546 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
547 /* One more address cycle for devices > 32MiB */
548 if (chip->chipsize > (32 << 20))
549 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
551 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
554 * program and erase have their own busy handlers
555 * status and sequential in needs no delay
559 case NAND_CMD_PAGEPROG:
560 case NAND_CMD_ERASE1:
561 case NAND_CMD_ERASE2:
563 case NAND_CMD_STATUS:
569 udelay(chip->chip_delay);
570 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
571 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
573 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
574 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
578 /* This applies to read commands */
581 * If we don't have access to the busy pin, we apply the given
584 if (!chip->dev_ready) {
585 udelay(chip->chip_delay);
589 /* Apply this short delay always to ensure that we do wait tWB in
590 * any case on any machine. */
593 //nand_wait_ready(mtd);
597 * nand_command_lp - [DEFAULT] Send command to NAND large page device
598 * @mtd: MTD device structure
599 * @command: the command to be sent
600 * @column: the column address for this command, -1 if none
601 * @page_addr: the page address for this command, -1 if none
603 * Send command to NAND device. This is the version for the new large page
604 * devices We dont have the separate regions as we have in the small page
605 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
607 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
608 int column, int page_addr)
610 register struct nand_chip *chip = mtd->priv;
611 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
613 /* Emulate NAND_CMD_READOOB */
614 if (command == NAND_CMD_READOOB) {
615 column += mtd->writesize;
616 command = NAND_CMD_READ0;
619 /* Command latch cycle */
620 chip->cmd_ctrl(mtd, command & 0xff,
621 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
623 if (column != -1 || page_addr != -1) {
624 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
626 /* Serially input address */
628 /* Adjust columns for 16 bit buswidth */
629 if (chip->options & NAND_BUSWIDTH_16)
631 #ifdef CONFIG_MTD_NAND_SPRD
632 chip->cmd_ctrl(mtd, column, ctrl);
634 chip->cmd_ctrl(mtd, column, ctrl);
635 ctrl &= ~NAND_CTRL_CHANGE;
636 chip->cmd_ctrl(mtd, column >> 8, ctrl);
639 if (page_addr != -1) {
640 #ifdef CONFIG_MTD_NAND_SPRD
641 chip->cmd_ctrl(mtd, page_addr, ctrl);
643 chip->cmd_ctrl(mtd, page_addr, ctrl);
644 chip->cmd_ctrl(mtd, page_addr >> 8,
645 NAND_NCE | NAND_ALE);
646 /* One more address cycle for devices > 128MiB */
647 if (chip->chipsize > (128 << 20))
648 chip->cmd_ctrl(mtd, page_addr >> 16,
649 NAND_NCE | NAND_ALE);
653 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
656 * program and erase have their own busy handlers
657 * status, sequential in, and deplete1 need no delay
661 case NAND_CMD_CACHEDPROG:
662 case NAND_CMD_PAGEPROG:
663 case NAND_CMD_ERASE1:
664 case NAND_CMD_ERASE2:
667 case NAND_CMD_STATUS:
668 case NAND_CMD_DEPLETE1:
672 * read error status commands require only a short delay
674 case NAND_CMD_STATUS_ERROR:
675 case NAND_CMD_STATUS_ERROR0:
676 case NAND_CMD_STATUS_ERROR1:
677 case NAND_CMD_STATUS_ERROR2:
678 case NAND_CMD_STATUS_ERROR3:
679 udelay(chip->chip_delay);
685 udelay(chip->chip_delay);
686 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
687 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
688 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
689 NAND_NCE | NAND_CTRL_CHANGE);
690 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
694 case NAND_CMD_RNDOUT:
695 /* No ready / busy check necessary */
696 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
697 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
698 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
699 NAND_NCE | NAND_CTRL_CHANGE);
703 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
704 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
705 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
706 NAND_NCE | NAND_CTRL_CHANGE);
708 /* This applies to read commands */
711 * If we don't have access to the busy pin, we apply the given
714 if (!chip->dev_ready) {
715 udelay(chip->chip_delay);
720 /* Apply this short delay always to ensure that we do wait tWB in
721 * any case on any machine. */
724 nand_wait_ready(mtd);
728 * nand_get_device - [GENERIC] Get chip for selected access
729 * @chip: the nand chip descriptor
730 * @mtd: MTD device structure
731 * @new_state: the state which is requested
733 * Get the device and lock it for exclusive access
735 static int nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state)
737 this->state = new_state;
742 * nand_wait - [DEFAULT] wait until the command is done
743 * @mtd: MTD device structure
744 * @chip: NAND chip structure
746 * Wait for command done. This applies to erase and program only
747 * Erase can take up to 400ms and program up to 20ms according to
748 * general NAND and SmartMedia specs
750 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this)
753 int state = this->state;
755 if (state == FL_ERASING)
756 timeo = (CONFIG_SYS_HZ * 400) / 1000;
758 timeo = (CONFIG_SYS_HZ * 20) / 1000;
760 if ((state == FL_ERASING) && (this->options & NAND_IS_AND))
761 this->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
763 this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
768 if (get_timer(0) > timeo) {
773 if (this->dev_ready) {
774 if (this->dev_ready(mtd))
777 if (this->read_byte(mtd) & NAND_STATUS_READY)
781 #ifdef PPCHAMELON_NAND_TIMER_HACK
783 while (get_timer(0) < 10);
784 #endif /* PPCHAMELON_NAND_TIMER_HACK */
786 return this->read_byte(mtd);
790 * nand_read_page_raw - [Intern] read raw page data without ecc
791 * @mtd: mtd info structure
792 * @chip: nand chip info structure
793 * @buf: buffer to store read data
794 * @page: page number to read
796 * Not for syndrome calculating ecc controllers, which use a special oob layout
798 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
799 uint8_t *buf, int page)
801 uint8_t ecc_calc[128];
802 chip->ecc.hwctl(mtd, NAND_ECC_READ);
803 chip->read_buf(mtd, buf, mtd->writesize);
804 chip->ecc.calculate(mtd, NULL, ecc_calc);
805 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
810 * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
811 * @mtd: mtd info structure
812 * @chip: nand chip info structure
813 * @buf: buffer to store read data
814 * @page: page number to read
816 * We need a special oob layout and handling even when OOB isn't used.
818 static int nand_read_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
819 uint8_t *buf, int page)
821 int eccsize = chip->ecc.size;
822 int eccbytes = chip->ecc.bytes;
823 uint8_t *oob = chip->oob_poi;
826 for (steps = chip->ecc.steps; steps > 0; steps--) {
827 chip->read_buf(mtd, buf, eccsize);
830 if (chip->ecc.prepad) {
831 chip->read_buf(mtd, oob, chip->ecc.prepad);
832 oob += chip->ecc.prepad;
835 chip->read_buf(mtd, oob, eccbytes);
838 if (chip->ecc.postpad) {
839 chip->read_buf(mtd, oob, chip->ecc.postpad);
840 oob += chip->ecc.postpad;
844 size = mtd->oobsize - (oob - chip->oob_poi);
846 chip->read_buf(mtd, oob, size);
852 * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
853 * @mtd: mtd info structure
854 * @chip: nand chip info structure
855 * @buf: buffer to store read data
856 * @page: page number to read
858 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
859 uint8_t *buf, int page)
861 int i, eccsize = chip->ecc.size;
862 int eccbytes = chip->ecc.bytes;
863 int eccsteps = chip->ecc.steps;
865 uint8_t *ecc_calc = chip->buffers->ecccalc;
866 uint8_t *ecc_code = chip->buffers->ecccode;
867 uint32_t *eccpos = chip->ecc.layout->eccpos;
869 chip->ecc.read_page_raw(mtd, chip, buf, page);
871 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
872 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
874 for (i = 0; i < chip->ecc.total; i++)
875 ecc_code[i] = chip->oob_poi[eccpos[i]];
877 eccsteps = chip->ecc.steps;
880 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
883 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
885 mtd->ecc_stats.failed++;
887 mtd->ecc_stats.corrected += stat;
893 * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
894 * @mtd: mtd info structure
895 * @chip: nand chip info structure
896 * @data_offs: offset of requested data within the page
897 * @readlen: data length
898 * @bufpoi: buffer to store read data
900 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
902 int start_step, end_step, num_steps;
903 uint32_t *eccpos = chip->ecc.layout->eccpos;
905 int data_col_addr, i, gaps = 0;
906 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
907 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
909 /* Column address wihin the page aligned to ECC size (256bytes). */
910 start_step = data_offs / chip->ecc.size;
911 end_step = (data_offs + readlen - 1) / chip->ecc.size;
912 num_steps = end_step - start_step + 1;
914 /* Data size aligned to ECC ecc.size*/
915 datafrag_len = num_steps * chip->ecc.size;
916 eccfrag_len = num_steps * chip->ecc.bytes;
918 data_col_addr = start_step * chip->ecc.size;
919 /* If we read not a page aligned data */
920 if (data_col_addr != 0)
921 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
923 p = bufpoi + data_col_addr;
924 chip->read_buf(mtd, p, datafrag_len);
927 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
928 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
930 /* The performance is faster if to position offsets
931 according to ecc.pos. Let make sure here that
932 there are no gaps in ecc positions */
933 for (i = 0; i < eccfrag_len - 1; i++) {
934 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
935 eccpos[i + start_step * chip->ecc.bytes + 1]) {
941 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
942 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
944 /* send the command to read the particular ecc bytes */
945 /* take care about buswidth alignment in read_buf */
946 aligned_pos = eccpos[start_step * chip->ecc.bytes] & ~(busw - 1);
947 aligned_len = eccfrag_len;
948 if (eccpos[start_step * chip->ecc.bytes] & (busw - 1))
950 if (eccpos[(start_step + num_steps) * chip->ecc.bytes] & (busw - 1))
953 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize + aligned_pos, -1);
954 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
957 for (i = 0; i < eccfrag_len; i++)
958 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + start_step * chip->ecc.bytes]];
960 p = bufpoi + data_col_addr;
961 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
964 stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
966 mtd->ecc_stats.failed++;
968 mtd->ecc_stats.corrected += stat;
974 * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
975 * @mtd: mtd info structure
976 * @chip: nand chip info structure
977 * @buf: buffer to store read data
978 * @page: page number to read
980 * Not for syndrome calculating ecc controllers which need a special oob layout
982 static int is_nand_spl_read = 0;
983 #define CONFIG_SYS_SPL_ECC_POS 8
984 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
985 uint8_t *buf, int page)
987 int i, eccsize = chip->ecc.size;
988 int eccbytes = chip->ecc.bytes;
989 int eccsteps = chip->ecc.steps;
991 uint8_t *ecc_calc = chip->buffers->ecccalc;
992 uint8_t *ecc_code = chip->buffers->ecccode;
993 uint32_t *eccpos = chip->ecc.layout->eccpos;
994 uint8_t tmplayout[64];
996 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
997 chip->ecc.hwctl(mtd, NAND_ECC_READ);
998 chip->read_buf(mtd, p, eccsize);
999 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1001 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1004 printf("nand_read_page_hwecc next\n");
1006 printf("%x ", chip->oob_poi[i]);
1012 if (is_nand_spl_read){
1013 int eccbytes = chip->ecc.bytes;
1014 int spare_per_sct = mtd->oobsize / chip->ecc.steps;
1015 for (i = 0; i < chip->ecc.steps; i ++){
1016 memcpy(&(ecc_code[i*eccbytes]), &(chip->oob_poi[i * spare_per_sct + CONFIG_SYS_SPL_ECC_POS]), eccbytes);
1019 for (i = 0; i < chip->ecc.total; i++)
1020 ecc_code[i] = chip->oob_poi[eccpos[i]];
1023 eccsteps = chip->ecc.steps;
1026 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1029 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1031 mtd->ecc_stats.failed++;
1032 printk("%s: ecc correct error %d times\n",__FUNCTION__, mtd->ecc_stats.failed);
1034 printk("\nthe all data page = %d\n", page);
1035 for(i = 0; i < 2048; i++) {
1036 printk("%02x ", *(p + i));
1041 printk("\nthe read ecc\n");
1042 for(i = 0; i < 16; i ++) {
1043 printk("%02x ", ecc_code[i]/**(read_ecc + i)*/);
1048 printk("\nthe calc ecc\n");
1049 for(i = 0; i < 16; i ++) {
1050 printk("%02x ", ecc_calc[i]/**(calc_ecc + i)*/);
1057 mtd->ecc_stats.corrected += stat;
1063 * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
1064 * @mtd: mtd info structure
1065 * @chip: nand chip info structure
1066 * @buf: buffer to store read data
1067 * @page: page number to read
1069 * Hardware ECC for large page chips, require OOB to be read first.
1070 * For this ECC mode, the write_page method is re-used from ECC_HW.
1071 * These methods read/write ECC from the OOB area, unlike the
1072 * ECC_HW_SYNDROME support with multiple ECC steps, follows the
1073 * "infix ECC" scheme and reads/writes ECC from the data area, by
1074 * overwriting the NAND manufacturer bad block markings.
1076 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1077 struct nand_chip *chip, uint8_t *buf, int page)
1079 int i, eccsize = chip->ecc.size;
1080 int eccbytes = chip->ecc.bytes;
1081 int eccsteps = chip->ecc.steps;
1083 uint8_t *ecc_code = chip->buffers->ecccode;
1084 uint32_t *eccpos = chip->ecc.layout->eccpos;
1085 uint8_t *ecc_calc = chip->buffers->ecccalc;
1087 /* Read the OOB area first */
1088 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1089 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1090 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1092 for (i = 0; i < chip->ecc.total; i++)
1093 ecc_code[i] = chip->oob_poi[eccpos[i]];
1095 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1098 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1099 chip->read_buf(mtd, p, eccsize);
1100 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1102 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1104 mtd->ecc_stats.failed++;
1106 mtd->ecc_stats.corrected += stat;
1112 * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
1113 * @mtd: mtd info structure
1114 * @chip: nand chip info structure
1115 * @buf: buffer to store read data
1116 * @page: page number to read
1118 * The hw generator calculates the error syndrome automatically. Therefor
1119 * we need a special oob layout and handling.
1121 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1122 uint8_t *buf, int page)
1124 int i, eccsize = chip->ecc.size;
1125 int eccbytes = chip->ecc.bytes;
1126 int eccsteps = chip->ecc.steps;
1128 uint8_t *oob = chip->oob_poi;
1130 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1133 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1134 chip->read_buf(mtd, p, eccsize);
1136 if (chip->ecc.prepad) {
1137 chip->read_buf(mtd, oob, chip->ecc.prepad);
1138 oob += chip->ecc.prepad;
1141 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1142 chip->read_buf(mtd, oob, eccbytes);
1143 stat = chip->ecc.correct(mtd, p, oob, NULL);
1146 mtd->ecc_stats.failed++;
1148 mtd->ecc_stats.corrected += stat;
1152 if (chip->ecc.postpad) {
1153 chip->read_buf(mtd, oob, chip->ecc.postpad);
1154 oob += chip->ecc.postpad;
1158 /* Calculate remaining oob bytes */
1159 i = mtd->oobsize - (oob - chip->oob_poi);
1161 chip->read_buf(mtd, oob, i);
1167 * nand_transfer_oob - [Internal] Transfer oob to client buffer
1168 * @chip: nand chip structure
1169 * @oob: oob destination address
1170 * @ops: oob ops structure
1171 * @len: size of oob to transfer
1173 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1174 struct mtd_oob_ops *ops, size_t len)
1180 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1183 case MTD_OOB_AUTO: {
1184 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1185 uint32_t boffs = 0, roffs = ops->ooboffs;
1188 for(; free->length && len; free++, len -= bytes) {
1189 /* Read request not from offset 0 ? */
1190 if (unlikely(roffs)) {
1191 if (roffs >= free->length) {
1192 roffs -= free->length;
1195 boffs = free->offset + roffs;
1196 bytes = min_t(size_t, len,
1197 (free->length - roffs));
1200 bytes = min_t(size_t, len, free->length);
1201 boffs = free->offset;
1203 memcpy(oob, chip->oob_poi + boffs, bytes);
1215 * nand_do_read_ops - [Internal] Read data with ECC
1217 * @mtd: MTD device structure
1218 * @from: offset to read from
1219 * @ops: oob ops structure
1221 * Internal function. Called with chip held.
1223 int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1224 struct mtd_oob_ops *ops)
1226 int chipnr, page, realpage, col, bytes, aligned;
1227 struct nand_chip *chip = mtd->priv;
1228 struct mtd_ecc_stats stats;
1229 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1232 uint32_t readlen = ops->len;
1233 uint32_t oobreadlen = ops->ooblen;
1234 uint8_t *bufpoi, *oob, *buf;
1236 stats = mtd->ecc_stats;
1238 chipnr = (int)(from >> chip->chip_shift);
1239 chip->select_chip(mtd, chipnr);
1241 realpage = (int)(from >> chip->page_shift);
1242 page = realpage & chip->pagemask;
1244 col = (int)(from & (mtd->writesize - 1));
1250 bytes = min(mtd->writesize - col, readlen);
1251 aligned = (bytes == mtd->writesize);
1253 /* Is the current page in the buffer ? */
1254 if (realpage != chip->pagebuf || oob) {
1255 bufpoi = aligned ? buf : chip->buffers->databuf;
1257 if (likely(sndcmd)) {
1258 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1262 if(page <= (0xc000 >> chip->page_shift)) {
1263 is_nand_spl_read = 1;
1265 is_nand_spl_read = 0;
1267 /* Now read the page into the buffer */
1268 if (unlikely(ops->mode == MTD_OOB_RAW))
1269 ret = chip->ecc.read_page_raw(mtd, chip,
1271 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1272 ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi);
1274 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1279 /* Transfer not aligned data */
1281 if (!NAND_SUBPAGE_READ(chip) && !oob)
1282 chip->pagebuf = realpage;
1283 memcpy(buf, chip->buffers->databuf + col, bytes);
1288 if (unlikely(oob)) {
1289 /* Raw mode does data:oob:data:oob */
1290 if (ops->mode != MTD_OOB_RAW) {
1291 int toread = min(oobreadlen,
1292 chip->ecc.layout->oobavail);
1294 oob = nand_transfer_oob(chip,
1296 oobreadlen -= toread;
1299 buf = nand_transfer_oob(chip,
1300 buf, ops, mtd->oobsize);
1303 if (!(chip->options & NAND_NO_READRDY)) {
1305 * Apply delay or wait for ready/busy pin. Do
1306 * this before the AUTOINCR check, so no
1307 * problems arise if a chip which does auto
1308 * increment is marked as NOAUTOINCR by the
1311 if (!chip->dev_ready)
1312 udelay(chip->chip_delay);
1314 nand_wait_ready(mtd);
1317 memcpy(buf, chip->buffers->databuf + col, bytes);
1326 /* For subsequent reads align to page boundary. */
1328 /* Increment page address */
1331 page = realpage & chip->pagemask;
1332 /* Check, if we cross a chip boundary */
1335 chip->select_chip(mtd, -1);
1336 chip->select_chip(mtd, chipnr);
1339 /* Check, if the chip supports auto page increment
1340 * or if we have hit a block boundary.
1342 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1346 ops->retlen = ops->len - (size_t) readlen;
1348 ops->oobretlen = ops->ooblen - oobreadlen;
1353 if (mtd->ecc_stats.failed - stats.failed)
1356 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1360 * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1361 * @mtd: MTD device structure
1362 * @from: offset to read from
1363 * @len: number of bytes to read
1364 * @retlen: pointer to variable to store the number of read bytes
1365 * @buf: the databuffer to put data
1367 * Get hold of the chip and call nand_do_read
1369 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1370 size_t *retlen, uint8_t *buf)
1372 struct nand_chip *chip = mtd->priv;
1375 /* Do not allow reads past end of device */
1376 if ((from + len) > mtd->size)
1381 nand_get_device(chip, mtd, FL_READING);
1383 chip->ops.len = len;
1384 chip->ops.datbuf = buf;
1385 chip->ops.oobbuf = NULL;
1387 ret = nand_do_read_ops(mtd, from, &chip->ops);
1389 *retlen = chip->ops.retlen;
1391 nand_release_device(mtd);
1397 * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1398 * @mtd: mtd info structure
1399 * @chip: nand chip info structure
1400 * @page: page number to read
1401 * @sndcmd: flag whether to issue read command or not
1403 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1404 int page, int sndcmd)
1407 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1410 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1415 * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1417 * @mtd: mtd info structure
1418 * @chip: nand chip info structure
1419 * @page: page number to read
1420 * @sndcmd: flag whether to issue read command or not
1422 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1423 int page, int sndcmd)
1425 uint8_t *buf = chip->oob_poi;
1426 int length = mtd->oobsize;
1427 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1428 int eccsize = chip->ecc.size;
1429 uint8_t *bufpoi = buf;
1430 int i, toread, sndrnd = 0, pos;
1432 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1433 for (i = 0; i < chip->ecc.steps; i++) {
1435 pos = eccsize + i * (eccsize + chunk);
1436 if (mtd->writesize > 512)
1437 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1439 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1442 toread = min_t(int, length, chunk);
1443 chip->read_buf(mtd, bufpoi, toread);
1448 chip->read_buf(mtd, bufpoi, length);
1454 * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1455 * @mtd: mtd info structure
1456 * @chip: nand chip info structure
1457 * @page: page number to write
1459 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1463 const uint8_t *buf = chip->oob_poi;
1464 int length = mtd->oobsize;
1466 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1467 chip->write_buf(mtd, buf, length);
1468 /* Send command to program the OOB data */
1469 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1471 status = chip->waitfunc(mtd, chip);
1473 return status & NAND_STATUS_FAIL ? -EIO : 0;
1477 * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1478 * with syndrome - only for large page flash !
1479 * @mtd: mtd info structure
1480 * @chip: nand chip info structure
1481 * @page: page number to write
1483 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1484 struct nand_chip *chip, int page)
1486 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1487 int eccsize = chip->ecc.size, length = mtd->oobsize;
1488 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1489 const uint8_t *bufpoi = chip->oob_poi;
1492 * data-ecc-data-ecc ... ecc-oob
1494 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1496 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1497 pos = steps * (eccsize + chunk);
1502 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1503 for (i = 0; i < steps; i++) {
1505 if (mtd->writesize <= 512) {
1506 uint32_t fill = 0xFFFFFFFF;
1510 int num = min_t(int, len, 4);
1511 chip->write_buf(mtd, (uint8_t *)&fill,
1516 pos = eccsize + i * (eccsize + chunk);
1517 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1521 len = min_t(int, length, chunk);
1522 chip->write_buf(mtd, bufpoi, len);
1527 chip->write_buf(mtd, bufpoi, length);
1529 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1530 status = chip->waitfunc(mtd, chip);
1532 return status & NAND_STATUS_FAIL ? -EIO : 0;
1536 * nand_do_read_oob - [Intern] NAND read out-of-band
1537 * @mtd: MTD device structure
1538 * @from: offset to read from
1539 * @ops: oob operations description structure
1541 * NAND read out-of-band data from the spare area
1543 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1544 struct mtd_oob_ops *ops)
1546 int page, realpage, chipnr, sndcmd = 1;
1547 struct nand_chip *chip = mtd->priv;
1548 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1549 int readlen = ops->ooblen;
1551 uint8_t *buf = ops->oobbuf;
1553 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n",
1554 (unsigned long long)from, readlen);
1556 if (ops->mode == MTD_OOB_AUTO)
1557 len = chip->ecc.layout->oobavail;
1561 if (unlikely(ops->ooboffs >= len)) {
1562 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1563 "Attempt to start read outside oob\n");
1567 /* Do not allow reads past end of device */
1568 if (unlikely(from >= mtd->size ||
1569 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1570 (from >> chip->page_shift)) * len)) {
1571 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1572 "Attempt read beyond end of device\n");
1576 chipnr = (int)(from >> chip->chip_shift);
1577 chip->select_chip(mtd, chipnr);
1579 /* Shift to get page */
1580 realpage = (int)(from >> chip->page_shift);
1581 page = realpage & chip->pagemask;
1584 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1586 len = min(len, readlen);
1587 buf = nand_transfer_oob(chip, buf, ops, len);
1589 if (!(chip->options & NAND_NO_READRDY)) {
1591 * Apply delay or wait for ready/busy pin. Do this
1592 * before the AUTOINCR check, so no problems arise if a
1593 * chip which does auto increment is marked as
1594 * NOAUTOINCR by the board driver.
1596 if (!chip->dev_ready)
1597 udelay(chip->chip_delay);
1599 nand_wait_ready(mtd);
1606 /* Increment page address */
1609 page = realpage & chip->pagemask;
1610 /* Check, if we cross a chip boundary */
1613 chip->select_chip(mtd, -1);
1614 chip->select_chip(mtd, chipnr);
1617 /* Check, if the chip supports auto page increment
1618 * or if we have hit a block boundary.
1620 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1624 ops->oobretlen = ops->ooblen;
1629 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1630 * @mtd: MTD device structure
1631 * @from: offset to read from
1632 * @ops: oob operation description structure
1634 * NAND read data and/or out-of-band data
1636 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1637 struct mtd_oob_ops *ops)
1639 struct nand_chip *chip = mtd->priv;
1640 int ret = -ENOTSUPP;
1644 /* Do not allow reads past end of device */
1645 if (ops->datbuf && (from + ops->len) > mtd->size) {
1646 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1647 "Attempt read beyond end of device\n");
1651 nand_get_device(chip, mtd, FL_READING);
1664 ret = nand_do_read_oob(mtd, from, ops);
1666 ret = nand_do_read_ops(mtd, from, ops);
1669 nand_release_device(mtd);
1675 * nand_write_page_raw - [Intern] raw page write function
1676 * @mtd: mtd info structure
1677 * @chip: nand chip info structure
1680 * Not for syndrome calculating ecc controllers, which use a special oob layout
1682 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1685 chip->write_buf(mtd, buf, mtd->writesize);
1686 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1690 * nand_write_page_raw_syndrome - [Intern] raw page write function
1691 * @mtd: mtd info structure
1692 * @chip: nand chip info structure
1695 * We need a special oob layout and handling even when ECC isn't checked.
1697 static void nand_write_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1700 int eccsize = chip->ecc.size;
1701 int eccbytes = chip->ecc.bytes;
1702 uint8_t *oob = chip->oob_poi;
1705 for (steps = chip->ecc.steps; steps > 0; steps--) {
1706 chip->write_buf(mtd, buf, eccsize);
1709 if (chip->ecc.prepad) {
1710 chip->write_buf(mtd, oob, chip->ecc.prepad);
1711 oob += chip->ecc.prepad;
1714 chip->read_buf(mtd, oob, eccbytes);
1717 if (chip->ecc.postpad) {
1718 chip->write_buf(mtd, oob, chip->ecc.postpad);
1719 oob += chip->ecc.postpad;
1723 size = mtd->oobsize - (oob - chip->oob_poi);
1725 chip->write_buf(mtd, oob, size);
1728 * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1729 * @mtd: mtd info structure
1730 * @chip: nand chip info structure
1733 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1736 int i, eccsize = chip->ecc.size;
1737 int eccbytes = chip->ecc.bytes;
1738 int eccsteps = chip->ecc.steps;
1739 uint8_t *ecc_calc = chip->buffers->ecccalc;
1740 const uint8_t *p = buf;
1741 uint32_t *eccpos = chip->ecc.layout->eccpos;
1743 /* Software ecc calculation */
1744 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1745 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1747 for (i = 0; i < chip->ecc.total; i++)
1748 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1750 chip->ecc.write_page_raw(mtd, chip, buf);
1754 * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1755 * @mtd: mtd info structure
1756 * @chip: nand chip info structure
1759 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1762 int i, eccsize = chip->ecc.size;
1763 int eccbytes = chip->ecc.bytes;
1764 int eccsteps = chip->ecc.steps;
1765 uint8_t *ecc_calc = chip->buffers->ecccalc;
1766 const uint8_t *p = buf;
1767 uint32_t *eccpos = chip->ecc.layout->eccpos;
1768 uint8_t ecclayouttemp;
1770 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1771 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1772 chip->write_buf(mtd, p, eccsize);
1773 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1776 for (i = 0; i < chip->ecc.total; i++)
1777 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1779 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1780 #ifdef CONFIG_MTD_NAND_SPRD
1781 chip->nfc_wr_oob(mtd);
1786 * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1787 * @mtd: mtd info structure
1788 * @chip: nand chip info structure
1791 * The hw generator calculates the error syndrome automatically. Therefor
1792 * we need a special oob layout and handling.
1794 static void nand_write_page_syndrome(struct mtd_info *mtd,
1795 struct nand_chip *chip, const uint8_t *buf)
1797 int i, eccsize = chip->ecc.size;
1798 int eccbytes = chip->ecc.bytes;
1799 int eccsteps = chip->ecc.steps;
1800 const uint8_t *p = buf;
1801 uint8_t *oob = chip->oob_poi;
1803 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1805 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1806 chip->write_buf(mtd, p, eccsize);
1808 if (chip->ecc.prepad) {
1809 chip->write_buf(mtd, oob, chip->ecc.prepad);
1810 oob += chip->ecc.prepad;
1813 chip->ecc.calculate(mtd, p, oob);
1814 chip->write_buf(mtd, oob, eccbytes);
1817 if (chip->ecc.postpad) {
1818 chip->write_buf(mtd, oob, chip->ecc.postpad);
1819 oob += chip->ecc.postpad;
1823 /* Calculate remaining oob bytes */
1824 i = mtd->oobsize - (oob - chip->oob_poi);
1826 chip->write_buf(mtd, oob, i);
1830 * nand_write_page - [REPLACEABLE] write one page
1831 * @mtd: MTD device structure
1832 * @chip: NAND chip descriptor
1833 * @buf: the data to write
1834 * @page: page number to write
1835 * @cached: cached programming
1836 * @raw: use _raw version of write_page
1838 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1839 const uint8_t *buf, int page, int cached, int raw)
1843 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1845 chip->ecc.write_page_raw(mtd, chip, buf);
1847 chip->ecc.write_page(mtd, chip, buf);
1849 * Cached progamming disabled for now, Not sure if its worth the
1850 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1854 if (!cached || !(chip->options & NAND_CACHEPRG)) {
1856 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1857 status = chip->waitfunc(mtd, chip);
1859 * See if operation failed and additional status checks are
1862 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1863 status = chip->errstat(mtd, chip, FL_WRITING, status,
1866 if (status & NAND_STATUS_FAIL)
1869 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1870 status = chip->waitfunc(mtd, chip);
1873 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1874 /* Send command to read back the data */
1875 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1877 if (chip->verify_buf(mtd, buf, mtd->writesize))
1884 * nand_fill_oob - [Internal] Transfer client buffer to oob
1885 * @chip: nand chip structure
1886 * @oob: oob data buffer
1887 * @ops: oob ops structure
1889 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
1890 struct mtd_oob_ops *ops)
1892 size_t len = ops->ooblen;
1898 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1901 case MTD_OOB_AUTO: {
1902 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1903 uint32_t boffs = 0, woffs = ops->ooboffs;
1906 for(; free->length && len; free++, len -= bytes) {
1907 /* Write request not from offset 0 ? */
1908 if (unlikely(woffs)) {
1909 if (woffs >= free->length) {
1910 woffs -= free->length;
1913 boffs = free->offset + woffs;
1914 bytes = min_t(size_t, len,
1915 (free->length - woffs));
1918 bytes = min_t(size_t, len, free->length);
1919 boffs = free->offset;
1921 memcpy(chip->oob_poi + boffs, oob, bytes);
1932 #define NOTALIGNED(x) (x & (chip->subpagesize - 1)) != 0
1935 * nand_do_write_ops - [Internal] NAND write with ECC
1936 * @mtd: MTD device structure
1937 * @to: offset to write to
1938 * @ops: oob operations description structure
1940 * NAND write with ECC
1942 int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1943 struct mtd_oob_ops *ops)
1945 int chipnr, realpage, page, blockmask, column;
1946 struct nand_chip *chip = mtd->priv;
1947 uint32_t writelen = ops->len;
1948 uint8_t *oob = ops->oobbuf;
1949 uint8_t *buf = ops->datbuf;
1956 column = to & (mtd->writesize - 1);
1957 subpage = column || (writelen & (mtd->writesize - 1));
1962 chipnr = (int)(to >> chip->chip_shift);
1963 chip->select_chip(mtd, chipnr);
1965 /* Check, if it is write protected */
1966 if (nand_check_wp(mtd)) {
1967 printk (KERN_NOTICE "nand_do_write_ops: Device is write protected\n");
1971 realpage = (int)(to >> chip->page_shift);
1972 page = realpage & chip->pagemask;
1973 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1975 /* Invalidate the page cache, when we write to the cached page */
1976 if (to <= (chip->pagebuf << chip->page_shift) &&
1977 (chip->pagebuf << chip->page_shift) < (to + ops->len))
1980 /* If we're not given explicit OOB data, let it be 0xFF */
1982 memset(chip->oob_poi, 0xff, mtd->oobsize);
1985 int bytes = mtd->writesize;
1986 int cached = writelen > bytes && page != blockmask;
1987 uint8_t *wbuf = buf;
1989 /* Partial page write ? */
1990 if (unlikely(column || writelen < (mtd->writesize - 1))) {
1992 bytes = min_t(int, bytes - column, (int) writelen);
1994 memset(chip->buffers->databuf, 0xff, mtd->writesize);
1995 memcpy(&chip->buffers->databuf[column], buf, bytes);
1996 wbuf = chip->buffers->databuf;
2000 memset(chip->oob_poi, 0xff, mtd->oobsize);
2001 oob = nand_fill_oob(chip, oob, ops);
2004 ret = chip->write_page(mtd, chip, wbuf, page, cached,
2005 (ops->mode == MTD_OOB_RAW));
2017 page = realpage & chip->pagemask;
2018 /* Check, if we cross a chip boundary */
2021 chip->select_chip(mtd, -1);
2022 chip->select_chip(mtd, chipnr);
2026 ops->retlen = ops->len - writelen;
2028 ops->oobretlen = ops->ooblen;
2033 * nand_write - [MTD Interface] NAND write with ECC
2034 * @mtd: MTD device structure
2035 * @to: offset to write to
2036 * @len: number of bytes to write
2037 * @retlen: pointer to variable to store the number of written bytes
2038 * @buf: the data to write
2040 * NAND write with ECC
2042 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2043 size_t *retlen, const uint8_t *buf)
2045 struct nand_chip *chip = mtd->priv;
2048 /* Do not allow reads past end of device */
2049 if ((to + len) > mtd->size)
2054 nand_get_device(chip, mtd, FL_WRITING);
2056 chip->ops.len = len;
2057 chip->ops.datbuf = (uint8_t *)buf;
2058 chip->ops.oobbuf = NULL;
2060 ret = nand_do_write_ops(mtd, to, &chip->ops);
2062 *retlen = chip->ops.retlen;
2064 nand_release_device(mtd);
2070 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2071 * @mtd: MTD device structure
2072 * @to: offset to write to
2073 * @ops: oob operation description structure
2075 * NAND write out-of-band
2077 int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2078 struct mtd_oob_ops *ops)
2080 int chipnr, page, status, len;
2081 struct nand_chip *chip = mtd->priv;
2083 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n",
2084 (unsigned int)to, (int)ops->ooblen);
2086 if (ops->mode == MTD_OOB_AUTO)
2087 len = chip->ecc.layout->oobavail;
2091 /* Do not allow write past end of page */
2092 if ((ops->ooboffs + ops->ooblen) > len) {
2093 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: "
2094 "Attempt to write past end of page\n");
2098 if (unlikely(ops->ooboffs >= len)) {
2099 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2100 "Attempt to start write outside oob\n");
2104 /* Do not allow reads past end of device */
2105 if (unlikely(to >= mtd->size ||
2106 ops->ooboffs + ops->ooblen >
2107 ((mtd->size >> chip->page_shift) -
2108 (to >> chip->page_shift)) * len)) {
2109 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2110 "Attempt write beyond end of device\n");
2114 chipnr = (int)(to >> chip->chip_shift);
2115 chip->select_chip(mtd, chipnr);
2117 /* Shift to get page */
2118 page = (int)(to >> chip->page_shift);
2121 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2122 * of my DiskOnChip 2000 test units) will clear the whole data page too
2123 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2124 * it in the doc2000 driver in August 1999. dwmw2.
2126 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2128 /* Check, if it is write protected */
2129 if (nand_check_wp(mtd))
2132 /* Invalidate the page cache, if we write to the cached page */
2133 if (page == chip->pagebuf)
2136 memset(chip->oob_poi, 0xff, mtd->oobsize);
2137 nand_fill_oob(chip, ops->oobbuf, ops);
2138 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2139 memset(chip->oob_poi, 0xff, mtd->oobsize);
2144 ops->oobretlen = ops->ooblen;
2150 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2151 * @mtd: MTD device structure
2152 * @to: offset to write to
2153 * @ops: oob operation description structure
2155 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2156 struct mtd_oob_ops *ops)
2158 struct nand_chip *chip = mtd->priv;
2159 int ret = -ENOTSUPP;
2163 /* Do not allow writes past end of device */
2164 if (ops->datbuf && (to + ops->len) > mtd->size) {
2165 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2166 "Attempt read beyond end of device\n");
2170 nand_get_device(chip, mtd, FL_WRITING);
2183 ret = nand_do_write_oob(mtd, to, ops);
2185 ret = nand_do_write_ops(mtd, to, ops);
2188 nand_release_device(mtd);
2193 * single_erease_cmd - [GENERIC] NAND standard block erase command function
2194 * @mtd: MTD device structure
2195 * @page: the page address of the block which will be erased
2197 * Standard erase command for NAND chips
2199 static void single_erase_cmd(struct mtd_info *mtd, int page)
2201 struct nand_chip *chip = mtd->priv;
2202 /* Send commands to erase a block */
2203 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2204 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2208 * multi_erease_cmd - [GENERIC] AND specific block erase command function
2209 * @mtd: MTD device structure
2210 * @page: the page address of the block which will be erased
2212 * AND multi block erase command function
2213 * Erase 4 consecutive blocks
2215 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2217 struct nand_chip *chip = mtd->priv;
2218 /* Send commands to erase a block */
2219 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2220 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2221 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2222 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2223 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2227 * nand_erase - [MTD Interface] erase block(s)
2228 * @mtd: MTD device structure
2229 * @instr: erase instruction
2231 * Erase one ore more blocks
2233 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2235 return nand_erase_nand(mtd, instr, 0);
2238 #define BBT_PAGE_MASK 0xffffff3f
2240 * nand_erase_nand - [Internal] erase block(s)
2241 * @mtd: MTD device structure
2242 * @instr: erase instruction
2243 * @allowbbt: allow erasing the bbt area
2245 * Erase one ore more blocks
2247 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2250 int page, status, pages_per_block, ret, chipnr;
2251 struct nand_chip *chip = mtd->priv;
2252 loff_t rewrite_bbt[CONFIG_SYS_NAND_MAX_CHIPS] = {0};
2253 unsigned int bbt_masked_page = 0xffffffff;
2256 MTDDEBUG(MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%012llx, "
2257 "len = %llu\n", (unsigned long long) instr->addr,
2258 (unsigned long long) instr->len);
2260 /* Start address must align on block boundary */
2261 if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
2262 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
2266 /* Length must align on block boundary */
2267 if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
2268 MTDDEBUG (MTD_DEBUG_LEVEL0,
2269 "nand_erase: Length not block aligned\n");
2273 /* Do not allow erase past end of device */
2274 if ((instr->len + instr->addr) > mtd->size) {
2275 MTDDEBUG (MTD_DEBUG_LEVEL0,
2276 "nand_erase: Erase past end of device\n");
2280 instr->fail_addr = 0xffffffff;
2282 /* Grab the lock and see if the device is available */
2283 nand_get_device(chip, mtd, FL_ERASING);
2285 /* Shift to get first page */
2286 page = (int)(instr->addr >> chip->page_shift);
2287 chipnr = (int)(instr->addr >> chip->chip_shift);
2289 /* Calculate pages in each block */
2290 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2292 /* Select the NAND device */
2293 chip->select_chip(mtd, chipnr);
2295 /* Check, if it is write protected */
2296 if (nand_check_wp(mtd)) {
2297 MTDDEBUG (MTD_DEBUG_LEVEL0,
2298 "nand_erase: Device is write protected!!!\n");
2299 instr->state = MTD_ERASE_FAILED;
2304 * If BBT requires refresh, set the BBT page mask to see if the BBT
2305 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2306 * can not be matched. This is also done when the bbt is actually
2307 * erased to avoid recusrsive updates
2309 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2310 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2312 /* Loop through the pages */
2315 instr->state = MTD_ERASING;
2319 * heck if we have a bad block, we do not erase bad blocks !
2321 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2322 chip->page_shift, 0, allowbbt)) {
2323 printk(KERN_WARNING "nand_erase: attempt to erase a "
2324 "bad block at page 0x%08x\n", page);
2325 instr->state = MTD_ERASE_FAILED;
2330 * Invalidate the page cache, if we erase the block which
2331 * contains the current cached page
2333 if (page <= chip->pagebuf && chip->pagebuf <
2334 (page + pages_per_block))
2337 chip->erase_cmd(mtd, page & chip->pagemask);
2339 status = chip->waitfunc(mtd, chip);
2342 * See if operation failed and additional status checks are
2345 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2346 status = chip->errstat(mtd, chip, FL_ERASING,
2349 /* See if block erase succeeded */
2350 if (status & NAND_STATUS_FAIL) {
2351 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: "
2352 "Failed erase, page 0x%08x\n", page);
2353 instr->state = MTD_ERASE_FAILED;
2354 instr->fail_addr = ((loff_t)page << chip->page_shift);
2359 * If BBT requires refresh, set the BBT rewrite flag to the
2362 if (bbt_masked_page != 0xffffffff &&
2363 (page & BBT_PAGE_MASK) == bbt_masked_page)
2364 rewrite_bbt[chipnr] =
2365 ((loff_t)page << chip->page_shift);
2367 /* Increment page address and decrement length */
2368 len -= (1 << chip->phys_erase_shift);
2369 page += pages_per_block;
2371 /* Check, if we cross a chip boundary */
2372 if (len && !(page & chip->pagemask)) {
2374 chip->select_chip(mtd, -1);
2375 chip->select_chip(mtd, chipnr);
2378 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2379 * page mask to see if this BBT should be rewritten
2381 if (bbt_masked_page != 0xffffffff &&
2382 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2383 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2387 instr->state = MTD_ERASE_DONE;
2391 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2393 /* Deselect and wake up anyone waiting on the device */
2394 nand_release_device(mtd);
2396 /* Do call back function */
2398 mtd_erase_callback(instr);
2401 * If BBT requires refresh and erase was successful, rewrite any
2402 * selected bad block tables
2404 if (bbt_masked_page == 0xffffffff || ret)
2407 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2408 if (!rewrite_bbt[chipnr])
2410 /* update the BBT for chip */
2411 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
2412 "(%d:0x%0llx 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
2413 chip->bbt_td->pages[chipnr]);
2414 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2417 /* Return more or less happy */
2422 * nand_sync - [MTD Interface] sync
2423 * @mtd: MTD device structure
2425 * Sync is actually a wait for chip ready function
2427 static void nand_sync(struct mtd_info *mtd)
2429 struct nand_chip *chip = mtd->priv;
2431 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_sync: called\n");
2433 /* Grab the lock and see if the device is available */
2434 nand_get_device(chip, mtd, FL_SYNCING);
2435 /* Release it and go back */
2436 nand_release_device(mtd);
2440 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2441 * @mtd: MTD device structure
2442 * @offs: offset relative to mtd start
2444 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2446 /* Check for invalid offset */
2447 if (offs > mtd->size)
2450 return nand_block_checkbad(mtd, offs, 1, 0);
2454 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2455 * @mtd: MTD device structure
2456 * @ofs: offset relative to mtd start
2458 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2460 struct nand_chip *chip = mtd->priv;
2463 if ((ret = nand_block_isbad(mtd, ofs))) {
2464 /* If it was bad already, return success and do nothing. */
2470 return chip->block_markbad(mtd, ofs);
2474 * Set default functions
2476 static void nand_set_defaults(struct nand_chip *chip, int busw)
2478 /* check for proper chip_delay setup, set 20us if not */
2479 if (!chip->chip_delay)
2480 chip->chip_delay = 20;
2482 /* check, if a user supplied command function given */
2483 if (chip->cmdfunc == NULL)
2484 chip->cmdfunc = nand_command;
2486 /* check, if a user supplied wait function given */
2487 if (chip->waitfunc == NULL)
2488 chip->waitfunc = nand_wait;
2490 if (!chip->select_chip)
2491 chip->select_chip = nand_select_chip;
2492 if (!chip->read_byte)
2493 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2494 if (!chip->read_word)
2495 chip->read_word = nand_read_word;
2496 if (!chip->block_bad)
2497 chip->block_bad = nand_block_bad;
2498 if (!chip->block_markbad)
2499 chip->block_markbad = nand_default_block_markbad;
2500 if (!chip->write_buf)
2501 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2502 if (!chip->read_buf)
2503 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2504 if (!chip->verify_buf)
2505 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2506 if (!chip->scan_bbt)
2507 chip->scan_bbt = nand_default_bbt;
2508 if (!chip->controller)
2509 chip->controller = &chip->hwcontrol;
2513 * Get the flash and manufacturer id and lookup if the type is supported
2515 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2516 struct nand_chip *chip,
2517 int busw, int *maf_id)
2519 struct nand_flash_dev *type = NULL;
2520 int i, dev_id, maf_idx;
2521 int tmp_id, tmp_manf;
2522 #if defined(CONFIG_NAND_SC8810) || defined(CONFIG_TIGER)|| defined(CONFIG_SC8830) || defined(CONFIG_SC9630)
2526 #ifdef CONFIG_MTD_NAND_SPRD
2527 unsigned long flash_id = 0;
2529 /* Select the device */
2530 chip->select_chip(mtd, 0);
2534 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2537 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2540 /* Send the command for reading device ID */
2541 #ifdef CONFIG_MTD_NAND_SPRD
2542 chip->cmdfunc(mtd, NAND_CMD_READID, -1, -1);
2543 flash_id = chip->nfc_readid(mtd);
2545 /*Read manufacturer and device IDs */
2546 *maf_id = flash_id & 0xff;
2547 dev_id = (flash_id >> 8)&0xff;
2549 chip->cmdfunc(mtd, NAND_CMD_READID, 0x0, -1);
2550 #if defined(CONFIG_NAND_SC8810) || defined(CONFIG_TIGER) || defined(CONFIG_SC8830) || defined(CONFIG_SC9630)
2551 for (i = 0; i < 5; i++)
2552 id_data[i] = chip->read_byte(mtd);
2553 /* Read manufacturer and device IDs */
2554 *maf_id = id_data[0];
2555 dev_id = id_data[1];
2558 /* Read manufacturer and device IDs */
2559 *maf_id = chip->read_byte(mtd);
2560 dev_id = chip->read_byte(mtd);
2564 /* Try again to make sure, as some systems the bus-hold or other
2565 * interface concerns can cause random data which looks like a
2566 * possibly credible NAND flash to appear. If the two results do
2567 * not match, ignore the device completely.
2570 #ifdef CONFIG_MTD_NAND_SPRD
2571 chip->cmdfunc(mtd, NAND_CMD_READID, -1, -1);
2572 flash_id = chip->nfc_readid(mtd);
2574 /* Read manufacturer and device IDs*/
2575 tmp_manf = flash_id & 0xff;
2576 tmp_id = (flash_id >> 8) & 0xff;
2578 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2580 /* Read manufacturer and device IDs */
2582 tmp_manf = chip->read_byte(mtd);
2583 tmp_id = chip->read_byte(mtd);
2586 if (tmp_manf != *maf_id || tmp_id != dev_id) {
2587 printk(KERN_INFO "%s: second ID read did not match "
2588 "%02x,%02x against %02x,%02x\n", __func__,
2589 *maf_id, dev_id, tmp_manf, tmp_id);
2590 return ERR_PTR(-ENODEV);
2593 /* Lookup the flash id */
2594 for (i = 0; nand_flash_ids[i].name != NULL; i++) {
2595 if (dev_id == nand_flash_ids[i].id) {
2596 type = &nand_flash_ids[i];
2602 /* supress warning if there is no nand */
2603 if (*maf_id != 0x00 && *maf_id != 0xff &&
2604 dev_id != 0x00 && dev_id != 0xff)
2605 printk(KERN_INFO "%s: unknown NAND device: "
2606 "Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
2607 __func__, *maf_id, dev_id);
2608 return ERR_PTR(-ENODEV);
2612 mtd->name = type->name;
2614 chip->chipsize = (uint64_t)type->chipsize << 20;
2616 /* Newer devices have all the information in additional id bytes */
2617 if (!type->pagesize) {
2619 #ifdef CONFIG_MTD_NAND_SPRD
2620 /* The 3rd id byte holds MLC / multichip data */
2621 chip->cellinfo = (flash_id >> 16) & 0xff;
2622 /* The 4th id byte is the important one */
2623 extid = (flash_id >> 24) & 0xff;
2625 /* The 3rd id byte holds MLC / multichip data */
2626 chip->cellinfo = chip->read_byte(mtd);
2627 /* The 4th id byte is the important one */
2628 extid = chip->read_byte(mtd);
2631 mtd->writesize = 1024 << (extid & 0x3);
2634 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
2636 /* Calc blocksize. Blocksize is multiples of 64KiB */
2637 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2639 /* Get buswidth information */
2640 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2644 * Old devices have chip data hardcoded in the device id table
2646 mtd->erasesize = type->erasesize;
2647 mtd->writesize = type->pagesize;
2648 mtd->oobsize = mtd->writesize / 32;
2649 busw = type->options & NAND_BUSWIDTH_16;
2652 /* Try to identify manufacturer */
2653 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2654 if (nand_manuf_ids[maf_idx].id == *maf_id)
2659 * Check, if buswidth is correct. Hardware drivers should set
2662 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2663 printk(KERN_INFO "NAND device: Manufacturer ID:"
2664 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2665 dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2666 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2667 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2669 return ERR_PTR(-EINVAL);
2672 /* Calculate the address shift from the page size */
2673 chip->page_shift = ffs(mtd->writesize) - 1;
2674 /* Convert chipsize to number of pages per chip -1. */
2675 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2677 chip->bbt_erase_shift = chip->phys_erase_shift =
2678 ffs(mtd->erasesize) - 1;
2679 if (chip->chipsize & 0xffffffff)
2680 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
2682 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)) + 31;
2684 /* Set the bad block position */
2685 chip->badblockpos = mtd->writesize > 512 ?
2686 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2688 /* Get chip options, preserve non chip based options */
2689 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2690 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
2693 * Set chip as a default. Board drivers can override it, if necessary
2695 chip->options |= NAND_NO_AUTOINCR;
2697 /* Check if chip is a not a samsung device. Do not clear the
2698 * options for chips which are not having an extended id.
2700 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2701 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2703 /* Check for AND chips with 4 page planes */
2704 if (chip->options & NAND_4PAGE_ARRAY)
2705 chip->erase_cmd = multi_erase_cmd;
2707 chip->erase_cmd = single_erase_cmd;
2709 /* Do not replace user supplied command function ! */
2710 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2711 chip->cmdfunc = nand_command_lp;
2713 MTDDEBUG (MTD_DEBUG_LEVEL0, "NAND device: Manufacturer ID:"
2714 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2715 nand_manuf_ids[maf_idx].name, type->name);
2718 #if defined(CONFIG_NAND_SC8810) || defined(CONFIG_TIGER)|| defined(CONFIG_SC8830) || defined(CONFIG_SC9630)
2719 extern void nand_hardware_config(struct mtd_info *mtd, struct nand_chip*, u8[5]);
2720 nand_hardware_config(mtd, chip, id_data);
2727 * nand_scan_ident - [NAND Interface] Scan for the NAND device
2728 * @mtd: MTD device structure
2729 * @maxchips: Number of chips to scan for
2731 * This is the first phase of the normal nand_scan() function. It
2732 * reads the flash ID and sets up MTD fields accordingly.
2734 * The mtd->owner field must be set to the module of the caller.
2736 int nand_scan_ident(struct mtd_info *mtd, int maxchips)
2738 int i, busw, nand_maf_id;
2739 struct nand_chip *chip = mtd->priv;
2740 struct nand_flash_dev *type;
2742 /* Get buswidth to select the correct functions */
2743 busw = chip->options & NAND_BUSWIDTH_16;
2744 /* Set the default functions */
2745 nand_set_defaults(chip, busw);
2747 /* Read the flash type */
2748 type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
2754 #ifndef CONFIG_SYS_NAND_QUIET_TEST
2755 printk(KERN_WARNING "No NAND device found!!!\n");
2757 chip->select_chip(mtd, -1);
2758 return PTR_ERR(type);
2761 /* Check for a chip array */
2762 for (i = 1; i < maxchips; i++) {
2763 chip->select_chip(mtd, i);
2764 /* See comment in nand_get_flash_type for reset */
2765 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2766 /* Send the command for reading device ID */
2767 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2768 /* Read manufacturer and device IDs */
2769 if (nand_maf_id != chip->read_byte(mtd) ||
2770 type->id != chip->read_byte(mtd))
2775 printk(KERN_INFO "%d NAND chips detected\n", i);
2778 /* Store the number of chips and calc total size for mtd */
2780 mtd->size = i * chip->chipsize;
2787 * nand_scan_tail - [NAND Interface] Scan for the NAND device
2788 * @mtd: MTD device structure
2790 * This is the second phase of the normal nand_scan() function. It
2791 * fills out all the uninitialized function pointers with the defaults
2792 * and scans for a bad block table if appropriate.
2794 int nand_scan_tail(struct mtd_info *mtd)
2797 struct nand_chip *chip = mtd->priv;
2799 if (!(chip->options & NAND_OWN_BUFFERS))
2800 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2801 if (!chip->buffers) {
2804 /* Set the internal oob buffer location, just after the page data */
2805 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
2808 * If no default placement scheme is given, select an appropriate one
2810 if (!chip->ecc.layout) {
2811 switch (mtd->oobsize) {
2813 chip->ecc.layout = &nand_oob_8;
2816 chip->ecc.layout = &nand_oob_16;
2819 chip->ecc.layout = &nand_oob_64;
2822 chip->ecc.layout = &nand_oob_128;
2825 printf("No oob scheme defined for "
2826 "oobsize %d\n", mtd->oobsize);
2830 if (!chip->write_page)
2831 chip->write_page = nand_write_page;
2834 * check ECC mode, default to software if 3byte/512byte hardware ECC is
2835 * selected and we have 256 byte pagesize fallback to software ECC
2838 switch (chip->ecc.mode) {
2839 case NAND_ECC_HW_OOB_FIRST:
2840 /* Similar to NAND_ECC_HW, but a separate read_page handle */
2841 if (!chip->ecc.calculate || !chip->ecc.correct ||
2843 printk(KERN_WARNING "No ECC functions supplied, "
2844 "Hardware ECC not possible\n");
2847 if (!chip->ecc.read_page)
2848 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
2851 /* Use standard hwecc read page function ? */
2852 if (!chip->ecc.read_page)
2853 chip->ecc.read_page = nand_read_page_hwecc;
2854 if (!chip->ecc.write_page)
2855 chip->ecc.write_page = nand_write_page_hwecc;
2856 if (!chip->ecc.read_page_raw)
2857 chip->ecc.read_page_raw = nand_read_page_raw;
2858 if (!chip->ecc.write_page_raw)
2859 chip->ecc.write_page_raw = nand_write_page_raw;
2860 if (!chip->ecc.read_oob)
2861 chip->ecc.read_oob = nand_read_oob_std;
2862 if (!chip->ecc.write_oob)
2863 chip->ecc.write_oob = nand_write_oob_std;
2865 case NAND_ECC_HW_SYNDROME:
2866 if ((!chip->ecc.calculate || !chip->ecc.correct ||
2867 !chip->ecc.hwctl) &&
2868 (!chip->ecc.read_page ||
2869 chip->ecc.read_page == nand_read_page_hwecc ||
2870 !chip->ecc.write_page ||
2871 chip->ecc.write_page == nand_write_page_hwecc)) {
2872 printk(KERN_WARNING "No ECC functions supplied, "
2873 "Hardware ECC not possible\n");
2876 /* Use standard syndrome read/write page function ? */
2877 if (!chip->ecc.read_page)
2878 chip->ecc.read_page = nand_read_page_syndrome;
2879 if (!chip->ecc.write_page)
2880 chip->ecc.write_page = nand_write_page_syndrome;
2881 if (!chip->ecc.read_page_raw)
2882 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
2883 if (!chip->ecc.write_page_raw)
2884 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
2885 if (!chip->ecc.read_oob)
2886 chip->ecc.read_oob = nand_read_oob_syndrome;
2887 if (!chip->ecc.write_oob)
2888 chip->ecc.write_oob = nand_write_oob_syndrome;
2890 if (mtd->writesize >= chip->ecc.size)
2892 printk(KERN_WARNING "%d byte HW ECC not possible on "
2893 "%d byte page size, fallback to SW ECC\n",
2894 chip->ecc.size, mtd->writesize);
2895 chip->ecc.mode = NAND_ECC_SOFT;
2898 chip->ecc.calculate = nand_calculate_ecc;
2899 chip->ecc.correct = nand_correct_data;
2900 chip->ecc.read_page = nand_read_page_swecc;
2901 chip->ecc.read_subpage = nand_read_subpage;
2902 chip->ecc.write_page = nand_write_page_swecc;
2903 chip->ecc.read_page_raw = nand_read_page_raw;
2904 chip->ecc.write_page_raw = nand_write_page_raw;
2905 chip->ecc.read_oob = nand_read_oob_std;
2906 chip->ecc.write_oob = nand_write_oob_std;
2907 chip->ecc.size = 256;
2908 chip->ecc.bytes = 3;
2912 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2913 "This is not recommended !!\n");
2914 chip->ecc.read_page = nand_read_page_raw;
2915 chip->ecc.write_page = nand_write_page_raw;
2916 chip->ecc.read_oob = nand_read_oob_std;
2917 chip->ecc.read_page_raw = nand_read_page_raw;
2918 chip->ecc.write_page_raw = nand_write_page_raw;
2919 chip->ecc.write_oob = nand_write_oob_std;
2920 chip->ecc.size = mtd->writesize;
2921 chip->ecc.bytes = 0;
2925 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
2931 * The number of bytes available for a client to place data into
2932 * the out of band area
2934 chip->ecc.layout->oobavail = 0;
2935 for (i = 0; chip->ecc.layout->oobfree[i].length
2936 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
2937 chip->ecc.layout->oobavail +=
2938 chip->ecc.layout->oobfree[i].length;
2939 mtd->oobavail = chip->ecc.layout->oobavail;
2942 * Set the number of read / write steps for one page depending on ECC
2945 chip->ecc.steps = mtd->writesize / chip->ecc.size;
2946 if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
2947 printk(KERN_WARNING "Invalid ecc parameters\n");
2950 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
2953 * Allow subpage writes up to ecc.steps. Not possible for MLC
2956 chip->options |= NAND_NO_SUBPAGE_WRITE;
2957 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2958 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
2959 switch(chip->ecc.steps) {
2961 mtd->subpage_sft = 1;
2966 mtd->subpage_sft = 2;
2970 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
2972 /* Initialize state */
2973 chip->state = FL_READY;
2975 /* De-select the device */
2976 chip->select_chip(mtd, -1);
2978 /* Invalidate the pagebuffer reference */
2981 /* Fill in remaining MTD driver data */
2982 mtd->type = MTD_NANDFLASH;
2983 mtd->flags = MTD_CAP_NANDFLASH;
2984 mtd->erase = nand_erase;
2986 mtd->unpoint = NULL;
2987 mtd->read = nand_read;
2988 mtd->write = nand_write;
2989 mtd->read_oob = nand_read_oob;
2990 mtd->write_oob = nand_write_oob;
2991 mtd->sync = nand_sync;
2994 mtd->block_isbad = nand_block_isbad;
2995 mtd->block_markbad = nand_block_markbad;
2997 /* propagate ecc.layout to mtd_info */
2998 mtd->ecclayout = chip->ecc.layout;
3000 /* Check, if we should skip the bad block table scan */
3001 if (chip->options & NAND_SKIP_BBTSCAN)
3002 chip->options |= NAND_BBT_SCANNED;
3008 * nand_scan - [NAND Interface] Scan for the NAND device
3009 * @mtd: MTD device structure
3010 * @maxchips: Number of chips to scan for
3012 * This fills out all the uninitialized function pointers
3013 * with the defaults.
3014 * The flash ID is read and the mtd/chip structures are
3015 * filled with the appropriate values.
3016 * The mtd->owner field must be set to the module of the caller
3019 int nand_scan(struct mtd_info *mtd, int maxchips)
3023 ret = nand_scan_ident(mtd, maxchips);
3025 ret = nand_scan_tail(mtd);
3030 * nand_release - [NAND Interface] Free resources held by the NAND device
3031 * @mtd: MTD device structure
3033 void nand_release(struct mtd_info *mtd)
3035 struct nand_chip *chip = mtd->priv;
3037 #ifdef CONFIG_MTD_PARTITIONS
3038 /* Deregister partitions */
3039 del_mtd_partitions(mtd);
3042 /* Free bad block table memory */
3044 if (!(chip->options & NAND_OWN_BUFFERS))
3045 kfree(chip->buffers);