drivers/mtd/nand/nand_base.c

   1 /*
   2  *  drivers/mtd/nand.c
   3  *
   4  *  Overview:
   5  *   This is the generic MTD driver for NAND flash devices. It should be
   6  *   capable of working with almost all NAND chips currently available.
   7  *   Basic support for AG-AND chips is provided.
   8  *
   9  *      Additional technical information is available on
  10  *      http://www.linux-mtd.infradead.org/doc/nand.html
  11  *
  12  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  13  *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
  14  *
  15  *  Credits:
  16  *      David Woodhouse for adding multichip support
  17  *
  18  *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  19  *      rework for 2K page size chips
  20  *
  21  *  TODO:
  22  *      Enable cached programming for 2k page size chips
  23  *      Check, if mtd->ecctype should be set to MTD_ECC_HW
  24  *      if we have HW ecc support.
  25  *      The AG-AND chips have nice features for speed improvement,
  26  *      which are not supported yet. Read / program 4 pages in one go.
  27  *      BBT table is not serialized, has to be fixed
  28  *
  29  * This program is free software; you can redistribute it and/or modify
  30  * it under the terms of the GNU General Public License version 2 as
  31  * published by the Free Software Foundation.
  32  *
  33  */
  34
  35 #include <common.h>
  36
  37 #define ENOTSUPP        524     /* Operation is not supported */
  38
  39 #include <malloc.h>
  40 #include <watchdog.h>
  41 #include <linux/err.h>
  42 #include <linux/mtd/compat.h>
  43 #include <linux/mtd/mtd.h>
  44 #include <linux/mtd/nand.h>
  45 #include <linux/mtd/nand_ecc.h>
  46 #include <linux/mtd/nand_bch.h>
  47
  48 #ifdef CONFIG_MTD_PARTITIONS
  49 #include <linux/mtd/partitions.h>
  50 #endif
  51
  52 #include <asm/io.h>
  53 #include <asm/errno.h>
  54
  55 /*
  56  * CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting
  57  * a flash.  NAND flash is initialized prior to interrupts so standard timers
  58  * can't be used.  CONFIG_SYS_NAND_RESET_CNT should be set to a value
  59  * which is greater than (max NAND reset time / NAND status read time).
  60  * A conservative default of 200000 (500 us / 25 ns) is used as a default.
  61  */
  62 #ifndef CONFIG_SYS_NAND_RESET_CNT
  63 #define CONFIG_SYS_NAND_RESET_CNT 200000
  64 #endif
  65
  66 /* Define default oob placement schemes for large and small page devices */
  67 static struct nand_ecclayout nand_oob_8 = {
  68         .eccbytes = 3,
  69         .eccpos = {0, 1, 2},
  70         .oobfree = {
  71                 {.offset = 3,
  72                  .length = 2},
  73                 {.offset = 6,
  74                  .length = 2} }
  75 };
  76
  77 static struct nand_ecclayout nand_oob_16 = {
  78         .eccbytes = 6,
  79         .eccpos = {0, 1, 2, 3, 6, 7},
  80         .oobfree = {
  81                 {.offset = 8,
  82                  . length = 8} }
  83 };
  84
  85 static struct nand_ecclayout nand_oob_64 = {
  86         .eccbytes = 24,
  87         .eccpos = {
  88                    40, 41, 42, 43, 44, 45, 46, 47,
  89                    48, 49, 50, 51, 52, 53, 54, 55,
  90                    56, 57, 58, 59, 60, 61, 62, 63},
  91         .oobfree = {
  92                 {.offset = 2,
  93                  .length = 38} }
  94 };
  95
  96 static struct nand_ecclayout nand_oob_128 = {
  97         .eccbytes = 48,
  98         .eccpos = {
  99                    80, 81, 82, 83, 84, 85, 86, 87,
 100                    88, 89, 90, 91, 92, 93, 94, 95,
 101                    96, 97, 98, 99, 100, 101, 102, 103,
 102                    104, 105, 106, 107, 108, 109, 110, 111,
 103                    112, 113, 114, 115, 116, 117, 118, 119,
 104                    120, 121, 122, 123, 124, 125, 126, 127},
 105         .oobfree = {
 106                 {.offset = 2,
 107                  .length = 78} }
 108 };
 109
 110 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
 111                            int new_state);
 112
 113 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
 114                              struct mtd_oob_ops *ops);
 115
 116 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this);
 117
 118 /**
 119  * nand_release_device - [GENERIC] release chip
 120  * @mtd:        MTD device structure
 121  *
 122  * Deselect, release chip lock and wake up anyone waiting on the device
 123  */
 124 static void nand_release_device(struct mtd_info *mtd)
 125 {
 126         struct nand_chip *this = mtd->priv;
 127         this->select_chip(mtd, -1);     /* De-select the NAND device */
 128 }
 129
 130 /**
 131  * nand_read_byte - [DEFAULT] read one byte from the chip
 132  * @mtd:        MTD device structure
 133  *
 134  * Default read function for 8bit buswith
 135  */
 136 uint8_t nand_read_byte(struct mtd_info *mtd)
 137 {
 138         struct nand_chip *chip = mtd->priv;
 139         return readb(chip->IO_ADDR_R);
 140 }
 141
 142 /**
 143  * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
 144  * @mtd:        MTD device structure
 145  *
 146  * Default read function for 16bit buswith with
 147  * endianess conversion
 148  */
 149 static uint8_t nand_read_byte16(struct mtd_info *mtd)
 150 {
 151         struct nand_chip *chip = mtd->priv;
 152         return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
 153 }
 154
 155 /**
 156  * nand_read_word - [DEFAULT] read one word from the chip
 157  * @mtd:        MTD device structure
 158  *
 159  * Default read function for 16bit buswith without
 160  * endianess conversion
 161  */
 162 static u16 nand_read_word(struct mtd_info *mtd)
 163 {
 164         struct nand_chip *chip = mtd->priv;
 165         return readw(chip->IO_ADDR_R);
 166 }
 167
 168 /**
 169  * nand_select_chip - [DEFAULT] control CE line
 170  * @mtd:        MTD device structure
 171  * @chipnr:     chipnumber to select, -1 for deselect
 172  *
 173  * Default select function for 1 chip devices.
 174  */
 175 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 176 {
 177         struct nand_chip *chip = mtd->priv;
 178
 179         switch (chipnr) {
 180         case -1:
 181                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
 182                 break;
 183         case 0:
 184                 break;
 185
 186         default:
 187                 BUG();
 188         }
 189 }
 190
 191 /**
 192  * nand_write_buf - [DEFAULT] write buffer to chip
 193  * @mtd:        MTD device structure
 194  * @buf:        data buffer
 195  * @len:        number of bytes to write
 196  *
 197  * Default write function for 8bit buswith
 198  */
 199 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 200 {
 201         int i;
 202         struct nand_chip *chip = mtd->priv;
 203
 204         for (i = 0; i < len; i++)
 205                 writeb(buf[i], chip->IO_ADDR_W);
 206 }
 207
 208 /**
 209  * nand_read_buf - [DEFAULT] read chip data into buffer
 210  * @mtd:        MTD device structure
 211  * @buf:        buffer to store date
 212  * @len:        number of bytes to read
 213  *
 214  * Default read function for 8bit buswith
 215  */
 216 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 217 {
 218         int i;
 219         struct nand_chip *chip = mtd->priv;
 220
 221         for (i = 0; i < len; i++)
 222                 buf[i] = readb(chip->IO_ADDR_R);
 223 }
 224
 225 /**
 226  * nand_verify_buf - [DEFAULT] Verify chip data against buffer
 227  * @mtd:        MTD device structure
 228  * @buf:        buffer containing the data to compare
 229  * @len:        number of bytes to compare
 230  *
 231  * Default verify function for 8bit buswith
 232  */
 233 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 234 {
 235         int i;
 236         struct nand_chip *chip = mtd->priv;
 237
 238         for (i = 0; i < len; i++)
 239                 if (buf[i] != readb(chip->IO_ADDR_R))
 240                         return -EFAULT;
 241         return 0;
 242 }
 243
 244 /**
 245  * nand_write_buf16 - [DEFAULT] write buffer to chip
 246  * @mtd:        MTD device structure
 247  * @buf:        data buffer
 248  * @len:        number of bytes to write
 249  *
 250  * Default write function for 16bit buswith
 251  */
 252 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 253 {
 254         int i;
 255         struct nand_chip *chip = mtd->priv;
 256         u16 *p = (u16 *) buf;
 257         len >>= 1;
 258
 259         for (i = 0; i < len; i++)
 260                 writew(p[i], chip->IO_ADDR_W);
 261
 262 }
 263
 264 /**
 265  * nand_read_buf16 - [DEFAULT] read chip data into buffer
 266  * @mtd:        MTD device structure
 267  * @buf:        buffer to store date
 268  * @len:        number of bytes to read
 269  *
 270  * Default read function for 16bit buswith
 271  */
 272 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 273 {
 274         int i;
 275         struct nand_chip *chip = mtd->priv;
 276         u16 *p = (u16 *) buf;
 277         len >>= 1;
 278
 279         for (i = 0; i < len; i++)
 280                 p[i] = readw(chip->IO_ADDR_R);
 281 }
 282
 283 /**
 284  * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
 285  * @mtd:        MTD device structure
 286  * @buf:        buffer containing the data to compare
 287  * @len:        number of bytes to compare
 288  *
 289  * Default verify function for 16bit buswith
 290  */
 291 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 292 {
 293         int i;
 294         struct nand_chip *chip = mtd->priv;
 295         u16 *p = (u16 *) buf;
 296         len >>= 1;
 297
 298         for (i = 0; i < len; i++)
 299                 if (p[i] != readw(chip->IO_ADDR_R))
 300                         return -EFAULT;
 301
 302         return 0;
 303 }
 304
 305 /**
 306  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
 307  * @mtd:        MTD device structure
 308  * @ofs:        offset from device start
 309  * @getchip:    0, if the chip is already selected
 310  *
 311  * Check, if the block is bad.
 312  */
 313 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 314 {
 315         int page, chipnr, res = 0;
 316         struct nand_chip *chip = mtd->priv;
 317         u16 bad;
 318
 319         page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 320
 321         if (getchip) {
 322                 chipnr = (int)(ofs >> chip->chip_shift);
 323
 324                 nand_get_device(chip, mtd, FL_READING);
 325
 326                 /* Select the NAND device */
 327                 chip->select_chip(mtd, chipnr);
 328         }
 329
 330         if (chip->options & NAND_BUSWIDTH_16) {
 331                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
 332                               page);
 333                 bad = cpu_to_le16(chip->read_word(mtd));
 334                 if (chip->badblockpos & 0x1)
 335                         bad >>= 8;
 336                 if ((bad & 0xFF) != 0xff)
 337                         res = 1;
 338         } else {
 339                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
 340                 if (chip->read_byte(mtd) != 0xff)
 341                         res = 1;
 342         }
 343
 344         if (getchip)
 345                 nand_release_device(mtd);
 346
 347         return res;
 348 }
 349
 350 /**
 351  * nand_default_block_markbad - [DEFAULT] mark a block bad
 352  * @mtd:        MTD device structure
 353  * @ofs:        offset from device start
 354  *
 355  * This is the default implementation, which can be overridden by
 356  * a hardware specific driver.
 357 */
 358 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 359 {
 360         struct nand_chip *chip = mtd->priv;
 361         uint8_t buf[2] = { 0, 0 };
 362         int block, ret;
 363
 364         /* Get block number */
 365         block = (int)(ofs >> chip->bbt_erase_shift);
 366         if (chip->bbt)
 367                 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
 368
 369         /* Do we have a flash based bad block table ? */
 370         if (chip->options & NAND_USE_FLASH_BBT)
 371                 ret = nand_update_bbt(mtd, ofs);
 372         else {
 373                 /* We write two bytes, so we dont have to mess with 16 bit
 374                  * access
 375                  */
 376                 nand_get_device(chip, mtd, FL_WRITING);
 377                 ofs += mtd->oobsize;
 378                 chip->ops.len = chip->ops.ooblen = 2;
 379                 chip->ops.datbuf = NULL;
 380                 chip->ops.oobbuf = buf;
 381                 chip->ops.ooboffs = chip->badblockpos & ~0x01;
 382
 383                 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
 384                 nand_release_device(mtd);
 385         }
 386         if (!ret)
 387                 mtd->ecc_stats.badblocks++;
 388
 389         return ret;
 390 }
 391
 392 /**
 393  * nand_check_wp - [GENERIC] check if the chip is write protected
 394  * @mtd:        MTD device structure
 395  * Check, if the device is write protected
 396  *
 397  * The function expects, that the device is already selected
 398  */
 399 static int nand_check_wp(struct mtd_info *mtd)
 400 {
 401         struct nand_chip *chip = mtd->priv;
 402         /* Check the WP bit */
 403         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 404         return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
 405 }
 406
 407 /**
 408  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
 409  * @mtd:        MTD device structure
 410  * @ofs:        offset from device start
 411  * @getchip:    0, if the chip is already selected
 412  * @allowbbt:   1, if its allowed to access the bbt area
 413  *
 414  * Check, if the block is bad. Either by reading the bad block table or
 415  * calling of the scan function.
 416  */
 417 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
 418                                int allowbbt)
 419 {
 420         struct nand_chip *chip = mtd->priv;
 421
 422         if (!(chip->options & NAND_BBT_SCANNED)) {
 423                 chip->options |= NAND_BBT_SCANNED;
 424                 chip->scan_bbt(mtd);
 425         }
 426
 427         if (!chip->bbt)
 428                 return chip->block_bad(mtd, ofs, getchip);
 429
 430         /* Return info from the table */
 431         return nand_isbad_bbt(mtd, ofs, allowbbt);
 432 }
 433
 434 /*
 435  * Wait for the ready pin, after a command
 436  * The timeout is catched later.
 437  */
 438 void nand_wait_ready(struct mtd_info *mtd)
 439 {
 440         struct nand_chip *chip = mtd->priv;
 441         u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
 442         u32 time_start;
 443
 444         time_start = get_timer(0);
 445
 446         /* wait until command is processed or timeout occures */
 447         while (get_timer(time_start) < timeo) {
 448                 if (chip->dev_ready)
 449                         if (chip->dev_ready(mtd))
 450                                 break;
 451         }
 452 }
 453
 454 /**
 455  * nand_command - [DEFAULT] Send command to NAND device
 456  * @mtd:        MTD device structure
 457  * @command:    the command to be sent
 458  * @column:     the column address for this command, -1 if none
 459  * @page_addr:  the page address for this command, -1 if none
 460  *
 461  * Send command to NAND device. This function is used for small page
 462  * devices (256/512 Bytes per page)
 463  */
 464 static void nand_command(struct mtd_info *mtd, unsigned int command,
 465                          int column, int page_addr)
 466 {
 467         register struct nand_chip *chip = mtd->priv;
 468         int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
 469         uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
 470
 471         /*
 472          * Write out the command to the device.
 473          */
 474         if (command == NAND_CMD_SEQIN) {
 475                 int readcmd;
 476
 477                 if (column >= mtd->writesize) {
 478                         /* OOB area */
 479                         column -= mtd->writesize;
 480                         readcmd = NAND_CMD_READOOB;
 481                 } else if (column < 256) {
 482                         /* First 256 bytes --> READ0 */
 483                         readcmd = NAND_CMD_READ0;
 484                 } else {
 485                         column -= 256;
 486                         readcmd = NAND_CMD_READ1;
 487                 }
 488                 chip->cmd_ctrl(mtd, readcmd, ctrl);
 489                 ctrl &= ~NAND_CTRL_CHANGE;
 490         }
 491         chip->cmd_ctrl(mtd, command, ctrl);
 492
 493         /*
 494          * Address cycle, when necessary
 495          */
 496         ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
 497         /* Serially input address */
 498         if (column != -1) {
 499                 /* Adjust columns for 16 bit buswidth */
 500                 if (chip->options & NAND_BUSWIDTH_16)
 501                         column >>= 1;
 502                 chip->cmd_ctrl(mtd, column, ctrl);
 503                 ctrl &= ~NAND_CTRL_CHANGE;
 504         }
 505         if (page_addr != -1) {
 506                 chip->cmd_ctrl(mtd, page_addr, ctrl);
 507                 ctrl &= ~NAND_CTRL_CHANGE;
 508                 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
 509                 /* One more address cycle for devices > 32MiB */
 510                 if (chip->chipsize > (32 << 20))
 511                         chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
 512         }
 513         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 514
 515         /*
 516          * program and erase have their own busy handlers
 517          * status and sequential in needs no delay
 518          */
 519         switch (command) {
 520
 521         case NAND_CMD_PAGEPROG:
 522         case NAND_CMD_ERASE1:
 523         case NAND_CMD_ERASE2:
 524         case NAND_CMD_SEQIN:
 525         case NAND_CMD_STATUS:
 526                 return;
 527
 528         case NAND_CMD_RESET:
 529                 if (chip->dev_ready)
 530                         break;
 531                 udelay(chip->chip_delay);
 532                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 533                                NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 534                 chip->cmd_ctrl(mtd,
 535                                NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 536                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
 537                         (rst_sts_cnt--));
 538                 return;
 539
 540                 /* This applies to read commands */
 541         default:
 542                 /*
 543                  * If we don't have access to the busy pin, we apply the given
 544                  * command delay
 545                  */
 546                 if (!chip->dev_ready) {
 547                         udelay(chip->chip_delay);
 548                         return;
 549                 }
 550         }
 551         /* Apply this short delay always to ensure that we do wait tWB in
 552          * any case on any machine. */
 553         ndelay(100);
 554
 555         nand_wait_ready(mtd);
 556 }
 557
 558 /**
 559  * nand_command_lp - [DEFAULT] Send command to NAND large page device
 560  * @mtd:        MTD device structure
 561  * @command:    the command to be sent
 562  * @column:     the column address for this command, -1 if none
 563  * @page_addr:  the page address for this command, -1 if none
 564  *
 565  * Send command to NAND device. This is the version for the new large page
 566  * devices We dont have the separate regions as we have in the small page
 567  * devices.  We must emulate NAND_CMD_READOOB to keep the code compatible.
 568  */
 569 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
 570                             int column, int page_addr)
 571 {
 572         register struct nand_chip *chip = mtd->priv;
 573         uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
 574
 575         /* Emulate NAND_CMD_READOOB */
 576         if (command == NAND_CMD_READOOB) {
 577                 column += mtd->writesize;
 578                 command = NAND_CMD_READ0;
 579         }
 580
 581         /* Command latch cycle */
 582         chip->cmd_ctrl(mtd, command & 0xff,
 583                        NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 584
 585         if (column != -1 || page_addr != -1) {
 586                 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
 587
 588                 /* Serially input address */
 589                 if (column != -1) {
 590                         /* Adjust columns for 16 bit buswidth */
 591                         if (chip->options & NAND_BUSWIDTH_16)
 592                                 column >>= 1;
 593                         chip->cmd_ctrl(mtd, column, ctrl);
 594                         ctrl &= ~NAND_CTRL_CHANGE;
 595                         chip->cmd_ctrl(mtd, column >> 8, ctrl);
 596                 }
 597                 if (page_addr != -1) {
 598                         chip->cmd_ctrl(mtd, page_addr, ctrl);
 599                         chip->cmd_ctrl(mtd, page_addr >> 8,
 600                                        NAND_NCE | NAND_ALE);
 601                         /* One more address cycle for devices > 128MiB */
 602                         if (chip->chipsize > (128 << 20))
 603                                 chip->cmd_ctrl(mtd, page_addr >> 16,
 604                                                NAND_NCE | NAND_ALE);
 605                 }
 606         }
 607         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 608
 609         /*
 610          * program and erase have their own busy handlers
 611          * status, sequential in, and deplete1 need no delay
 612          */
 613         switch (command) {
 614
 615         case NAND_CMD_CACHEDPROG:
 616         case NAND_CMD_PAGEPROG:
 617         case NAND_CMD_ERASE1:
 618         case NAND_CMD_ERASE2:
 619         case NAND_CMD_SEQIN:
 620         case NAND_CMD_RNDIN:
 621         case NAND_CMD_STATUS:
 622         case NAND_CMD_DEPLETE1:
 623                 return;
 624
 625                 /*
 626                  * read error status commands require only a short delay
 627                  */
 628         case NAND_CMD_STATUS_ERROR:
 629         case NAND_CMD_STATUS_ERROR0:
 630         case NAND_CMD_STATUS_ERROR1:
 631         case NAND_CMD_STATUS_ERROR2:
 632         case NAND_CMD_STATUS_ERROR3:
 633                 udelay(chip->chip_delay);
 634                 return;
 635
 636         case NAND_CMD_RESET:
 637                 if (chip->dev_ready)
 638                         break;
 639                 udelay(chip->chip_delay);
 640                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 641                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 642                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 643                                NAND_NCE | NAND_CTRL_CHANGE);
 644                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
 645                         (rst_sts_cnt--));
 646                 return;
 647
 648         case NAND_CMD_RNDOUT:
 649                 /* No ready / busy check necessary */
 650                 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
 651                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 652                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 653                                NAND_NCE | NAND_CTRL_CHANGE);
 654                 return;
 655
 656         case NAND_CMD_READ0:
 657                 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
 658                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 659                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 660                                NAND_NCE | NAND_CTRL_CHANGE);
 661
 662                 /* This applies to read commands */
 663         default:
 664                 /*
 665                  * If we don't have access to the busy pin, we apply the given
 666                  * command delay
 667                  */
 668                 if (!chip->dev_ready) {
 669                         udelay(chip->chip_delay);
 670                         return;
 671                 }
 672         }
 673
 674         /* Apply this short delay always to ensure that we do wait tWB in
 675          * any case on any machine. */
 676         ndelay(100);
 677
 678         nand_wait_ready(mtd);
 679 }
 680
 681 /**
 682  * nand_get_device - [GENERIC] Get chip for selected access
 683  * @chip:       the nand chip descriptor
 684  * @mtd:        MTD device structure
 685  * @new_state:  the state which is requested
 686  *
 687  * Get the device and lock it for exclusive access
 688  */
 689 static int nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state)
 690 {
 691         this->state = new_state;
 692         return 0;
 693 }
 694
 695 /**
 696  * nand_wait - [DEFAULT]  wait until the command is done
 697  * @mtd:        MTD device structure
 698  * @chip:       NAND chip structure
 699  *
 700  * Wait for command done. This applies to erase and program only
 701  * Erase can take up to 400ms and program up to 20ms according to
 702  * general NAND and SmartMedia specs
 703  */
 704 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this)
 705 {
 706         unsigned long   timeo;
 707         int state = this->state;
 708         u32 time_start;
 709
 710         if (state == FL_ERASING)
 711                 timeo = (CONFIG_SYS_HZ * 400) / 1000;
 712         else
 713                 timeo = (CONFIG_SYS_HZ * 20) / 1000;
 714
 715         if ((state == FL_ERASING) && (this->options & NAND_IS_AND))
 716                 this->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
 717         else
 718                 this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 719
 720         time_start = get_timer(0);
 721
 722         while (1) {
 723                 if (get_timer(time_start) > timeo) {
 724                         printf("Timeout!");
 725                         return 0x01;
 726                 }
 727
 728                 if (this->dev_ready) {
 729                         if (this->dev_ready(mtd))
 730                                 break;
 731                 } else {
 732                         if (this->read_byte(mtd) & NAND_STATUS_READY)
 733                                 break;
 734                 }
 735         }
 736 #ifdef PPCHAMELON_NAND_TIMER_HACK
 737         time_start = get_timer(0);
 738         while (get_timer(time_start) < 10)
 739                 ;
 740 #endif /*  PPCHAMELON_NAND_TIMER_HACK */
 741
 742         return this->read_byte(mtd);
 743 }
 744
 745 /**
 746  * nand_read_page_raw - [Intern] read raw page data without ecc
 747  * @mtd:        mtd info structure
 748  * @chip:       nand chip info structure
 749  * @buf:        buffer to store read data
 750  * @page:       page number to read
 751  *
 752  * Not for syndrome calculating ecc controllers, which use a special oob layout
 753  */
 754 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
 755                               uint8_t *buf, int page)
 756 {
 757         chip->read_buf(mtd, buf, mtd->writesize);
 758         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 759         return 0;
 760 }
 761
 762 /**
 763  * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
 764  * @mtd:        mtd info structure
 765  * @chip:       nand chip info structure
 766  * @buf:        buffer to store read data
 767  * @page:       page number to read
 768  *
 769  * We need a special oob layout and handling even when OOB isn't used.
 770  */
 771 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
 772                                         struct nand_chip *chip,
 773                                         uint8_t *buf, int page)
 774 {
 775         int eccsize = chip->ecc.size;
 776         int eccbytes = chip->ecc.bytes;
 777         uint8_t *oob = chip->oob_poi;
 778         int steps, size;
 779
 780         for (steps = chip->ecc.steps; steps > 0; steps--) {
 781                 chip->read_buf(mtd, buf, eccsize);
 782                 buf += eccsize;
 783
 784                 if (chip->ecc.prepad) {
 785                         chip->read_buf(mtd, oob, chip->ecc.prepad);
 786                         oob += chip->ecc.prepad;
 787                 }
 788
 789                 chip->read_buf(mtd, oob, eccbytes);
 790                 oob += eccbytes;
 791
 792                 if (chip->ecc.postpad) {
 793                         chip->read_buf(mtd, oob, chip->ecc.postpad);
 794                         oob += chip->ecc.postpad;
 795                 }
 796         }
 797
 798         size = mtd->oobsize - (oob - chip->oob_poi);
 799         if (size)
 800                 chip->read_buf(mtd, oob, size);
 801
 802         return 0;
 803 }
 804
 805 /**
 806  * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
 807  * @mtd:        mtd info structure
 808  * @chip:       nand chip info structure
 809  * @buf:        buffer to store read data
 810  * @page:       page number to read
 811  */
 812 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
 813                                 uint8_t *buf, int page)
 814 {
 815         int i, eccsize = chip->ecc.size;
 816         int eccbytes = chip->ecc.bytes;
 817         int eccsteps = chip->ecc.steps;
 818         uint8_t *p = buf;
 819         uint8_t *ecc_calc = chip->buffers->ecccalc;
 820         uint8_t *ecc_code = chip->buffers->ecccode;
 821         uint32_t *eccpos = chip->ecc.layout->eccpos;
 822
 823         chip->ecc.read_page_raw(mtd, chip, buf, page);
 824
 825         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
 826                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 827
 828         for (i = 0; i < chip->ecc.total; i++)
 829                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 830
 831         eccsteps = chip->ecc.steps;
 832         p = buf;
 833
 834         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 835                 int stat;
 836
 837                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 838                 if (stat < 0)
 839                         mtd->ecc_stats.failed++;
 840                 else
 841                         mtd->ecc_stats.corrected += stat;
 842         }
 843         return 0;
 844 }
 845
 846 /**
 847  * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
 848  * @mtd:        mtd info structure
 849  * @chip:       nand chip info structure
 850  * @data_offs:  offset of requested data within the page
 851  * @readlen:    data length
 852  * @bufpoi:     buffer to store read data
 853  */
 854 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
 855                         uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
 856 {
 857         int start_step, end_step, num_steps;
 858         uint32_t *eccpos = chip->ecc.layout->eccpos;
 859         uint8_t *p;
 860         int data_col_addr, i, gaps = 0;
 861         int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
 862         int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
 863
 864         /* Column address wihin the page aligned to ECC size (256bytes). */
 865         start_step = data_offs / chip->ecc.size;
 866         end_step = (data_offs + readlen - 1) / chip->ecc.size;
 867         num_steps = end_step - start_step + 1;
 868
 869         /* Data size aligned to ECC ecc.size*/
 870         datafrag_len = num_steps * chip->ecc.size;
 871         eccfrag_len = num_steps * chip->ecc.bytes;
 872
 873         data_col_addr = start_step * chip->ecc.size;
 874         /* If we read not a page aligned data */
 875         if (data_col_addr != 0)
 876                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
 877
 878         p = bufpoi + data_col_addr;
 879         chip->read_buf(mtd, p, datafrag_len);
 880
 881         /* Calculate  ECC */
 882         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
 883                 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
 884
 885         /* The performance is faster if to position offsets
 886            according to ecc.pos. Let make sure here that
 887            there are no gaps in ecc positions */
 888         for (i = 0; i < eccfrag_len - 1; i++) {
 889                 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
 890                         eccpos[i + start_step * chip->ecc.bytes + 1]) {
 891                         gaps = 1;
 892                         break;
 893                 }
 894         }
 895         if (gaps) {
 896                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
 897                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 898         } else {
 899                 /* send the command to read the particular ecc bytes */
 900                 /* take care about buswidth alignment in read_buf */
 901                 aligned_pos = eccpos[start_step * chip->ecc.bytes] & ~(busw - 1);
 902                 aligned_len = eccfrag_len;
 903                 if (eccpos[start_step * chip->ecc.bytes] & (busw - 1))
 904                         aligned_len++;
 905                 if (eccpos[(start_step + num_steps) * chip->ecc.bytes] & (busw - 1))
 906                         aligned_len++;
 907
 908                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize + aligned_pos, -1);
 909                 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
 910         }
 911
 912         for (i = 0; i < eccfrag_len; i++)
 913                 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + start_step * chip->ecc.bytes]];
 914
 915         p = bufpoi + data_col_addr;
 916         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
 917                 int stat;
 918
 919                 stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
 920                 if (stat == -1)
 921                         mtd->ecc_stats.failed++;
 922                 else
 923                         mtd->ecc_stats.corrected += stat;
 924         }
 925         return 0;
 926 }
 927
 928 /**
 929  * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
 930  * @mtd:        mtd info structure
 931  * @chip:       nand chip info structure
 932  * @buf:        buffer to store read data
 933  * @page:       page number to read
 934  *
 935  * Not for syndrome calculating ecc controllers which need a special oob layout
 936  */
 937 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
 938                                 uint8_t *buf, int page)
 939 {
 940         int i, eccsize = chip->ecc.size;
 941         int eccbytes = chip->ecc.bytes;
 942         int eccsteps = chip->ecc.steps;
 943         uint8_t *p = buf;
 944         uint8_t *ecc_calc = chip->buffers->ecccalc;
 945         uint8_t *ecc_code = chip->buffers->ecccode;
 946         uint32_t *eccpos = chip->ecc.layout->eccpos;
 947
 948         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 949                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 950                 chip->read_buf(mtd, p, eccsize);
 951                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 952         }
 953         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 954
 955         for (i = 0; i < chip->ecc.total; i++)
 956                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 957
 958         eccsteps = chip->ecc.steps;
 959         p = buf;
 960
 961         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 962                 int stat;
 963
 964                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 965                 if (stat < 0)
 966                         mtd->ecc_stats.failed++;
 967                 else
 968                         mtd->ecc_stats.corrected += stat;
 969         }
 970         return 0;
 971 }
 972
 973 /**
 974  * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
 975  * @mtd:        mtd info structure
 976  * @chip:       nand chip info structure
 977  * @buf:        buffer to store read data
 978  * @page:       page number to read
 979  *
 980  * Hardware ECC for large page chips, require OOB to be read first.
 981  * For this ECC mode, the write_page method is re-used from ECC_HW.
 982  * These methods read/write ECC from the OOB area, unlike the
 983  * ECC_HW_SYNDROME support with multiple ECC steps, follows the
 984  * "infix ECC" scheme and reads/writes ECC from the data area, by
 985  * overwriting the NAND manufacturer bad block markings.
 986  */
 987 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
 988         struct nand_chip *chip, uint8_t *buf, int page)
 989 {
 990         int i, eccsize = chip->ecc.size;
 991         int eccbytes = chip->ecc.bytes;
 992         int eccsteps = chip->ecc.steps;
 993         uint8_t *p = buf;
 994         uint8_t *ecc_code = chip->buffers->ecccode;
 995         uint32_t *eccpos = chip->ecc.layout->eccpos;
 996         uint8_t *ecc_calc = chip->buffers->ecccalc;
 997
 998         /* Read the OOB area first */
 999         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1000         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1001         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1002
1003         for (i = 0; i < chip->ecc.total; i++)
1004                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1005
1006         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1007                 int stat;
1008
1009                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1010                 chip->read_buf(mtd, p, eccsize);
1011                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1012
1013                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1014                 if (stat < 0)
1015                         mtd->ecc_stats.failed++;
1016                 else
1017                         mtd->ecc_stats.corrected += stat;
1018         }
1019         return 0;
1020 }
1021
1022 /**
1023  * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
1024  * @mtd:        mtd info structure
1025  * @chip:       nand chip info structure
1026  * @buf:        buffer to store read data
1027  * @page:       page number to read
1028  *
1029  * The hw generator calculates the error syndrome automatically. Therefor
1030  * we need a special oob layout and handling.
1031  */
1032 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1033                                    uint8_t *buf, int page)
1034 {
1035         int i, eccsize = chip->ecc.size;
1036         int eccbytes = chip->ecc.bytes;
1037         int eccsteps = chip->ecc.steps;
1038         uint8_t *p = buf;
1039         uint8_t *oob = chip->oob_poi;
1040
1041         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1042                 int stat;
1043
1044                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1045                 chip->read_buf(mtd, p, eccsize);
1046
1047                 if (chip->ecc.prepad) {
1048                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1049                         oob += chip->ecc.prepad;
1050                 }
1051
1052                 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1053                 chip->read_buf(mtd, oob, eccbytes);
1054                 stat = chip->ecc.correct(mtd, p, oob, NULL);
1055
1056                 if (stat < 0)
1057                         mtd->ecc_stats.failed++;
1058                 else
1059                         mtd->ecc_stats.corrected += stat;
1060
1061                 oob += eccbytes;
1062
1063                 if (chip->ecc.postpad) {
1064                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1065                         oob += chip->ecc.postpad;
1066                 }
1067         }
1068
1069         /* Calculate remaining oob bytes */
1070         i = mtd->oobsize - (oob - chip->oob_poi);
1071         if (i)
1072                 chip->read_buf(mtd, oob, i);
1073
1074         return 0;
1075 }
1076
1077 /**
1078  * nand_transfer_oob - [Internal] Transfer oob to client buffer
1079  * @chip:       nand chip structure
1080  * @oob:        oob destination address
1081  * @ops:        oob ops structure
1082  * @len:        size of oob to transfer
1083  */
1084 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1085                                   struct mtd_oob_ops *ops, size_t len)
1086 {
1087         switch (ops->mode) {
1088
1089         case MTD_OOB_PLACE:
1090         case MTD_OOB_RAW:
1091                 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1092                 return oob + len;
1093
1094         case MTD_OOB_AUTO: {
1095                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1096                 uint32_t boffs = 0, roffs = ops->ooboffs;
1097                 size_t bytes = 0;
1098
1099                 for (; free->length && len; free++, len -= bytes) {
1100                         /* Read request not from offset 0 ? */
1101                         if (unlikely(roffs)) {
1102                                 if (roffs >= free->length) {
1103                                         roffs -= free->length;
1104                                         continue;
1105                                 }
1106                                 boffs = free->offset + roffs;
1107                                 bytes = min_t(size_t, len,
1108                                               (free->length - roffs));
1109                                 roffs = 0;
1110                         } else {
1111                                 bytes = min_t(size_t, len, free->length);
1112                                 boffs = free->offset;
1113                         }
1114                         memcpy(oob, chip->oob_poi + boffs, bytes);
1115                         oob += bytes;
1116                 }
1117                 return oob;
1118         }
1119         default:
1120                 BUG();
1121         }
1122         return NULL;
1123 }
1124
1125 /**
1126  * nand_do_read_ops - [Internal] Read data with ECC
1127  *
1128  * @mtd:        MTD device structure
1129  * @from:       offset to read from
1130  * @ops:        oob ops structure
1131  *
1132  * Internal function. Called with chip held.
1133  */
1134 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1135                             struct mtd_oob_ops *ops)
1136 {
1137         int chipnr, page, realpage, col, bytes, aligned;
1138         struct nand_chip *chip = mtd->priv;
1139         struct mtd_ecc_stats stats;
1140         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1141         int sndcmd = 1;
1142         int ret = 0;
1143         uint32_t readlen = ops->len;
1144         uint32_t oobreadlen = ops->ooblen;
1145         uint8_t *bufpoi, *oob, *buf;
1146
1147         stats = mtd->ecc_stats;
1148
1149         chipnr = (int)(from >> chip->chip_shift);
1150         chip->select_chip(mtd, chipnr);
1151
1152         realpage = (int)(from >> chip->page_shift);
1153         page = realpage & chip->pagemask;
1154
1155         col = (int)(from & (mtd->writesize - 1));
1156
1157         buf = ops->datbuf;
1158         oob = ops->oobbuf;
1159
1160         while (1) {
1161                 WATCHDOG_RESET();
1162
1163                 bytes = min(mtd->writesize - col, readlen);
1164                 aligned = (bytes == mtd->writesize);
1165
1166                 /* Is the current page in the buffer ? */
1167                 if (realpage != chip->pagebuf || oob) {
1168                         bufpoi = aligned ? buf : chip->buffers->databuf;
1169
1170                         if (likely(sndcmd)) {
1171                                 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1172                                 sndcmd = 0;
1173                         }
1174
1175                         /* Now read the page into the buffer */
1176                         if (unlikely(ops->mode == MTD_OOB_RAW))
1177                                 ret = chip->ecc.read_page_raw(mtd, chip,
1178                                                               bufpoi, page);
1179                         else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1180                                 ret = chip->ecc.read_subpage(mtd, chip,
1181                                                         col, bytes, bufpoi);
1182                         else
1183                                 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1184                                                           page);
1185                         if (ret < 0)
1186                                 break;
1187
1188                         /* Transfer not aligned data */
1189                         if (!aligned) {
1190                                 if (!NAND_SUBPAGE_READ(chip) && !oob)
1191                                         chip->pagebuf = realpage;
1192                                 memcpy(buf, chip->buffers->databuf + col, bytes);
1193                         }
1194
1195                         buf += bytes;
1196
1197                         if (unlikely(oob)) {
1198                                 /* Raw mode does data:oob:data:oob */
1199                                 if (ops->mode != MTD_OOB_RAW) {
1200                                         int toread = min(oobreadlen,
1201                                                 chip->ecc.layout->oobavail);
1202                                         if (toread) {
1203                                                 oob = nand_transfer_oob(chip,
1204                                                         oob, ops, toread);
1205                                                 oobreadlen -= toread;
1206                                         }
1207                                 } else
1208                                         buf = nand_transfer_oob(chip,
1209                                                 buf, ops, mtd->oobsize);
1210                         }
1211
1212                         if (!(chip->options & NAND_NO_READRDY)) {
1213                                 /*
1214                                  * Apply delay or wait for ready/busy pin. Do
1215                                  * this before the AUTOINCR check, so no
1216                                  * problems arise if a chip which does auto
1217                                  * increment is marked as NOAUTOINCR by the
1218                                  * board driver.
1219                                  */
1220                                 if (!chip->dev_ready)
1221                                         udelay(chip->chip_delay);
1222                                 else
1223                                         nand_wait_ready(mtd);
1224                         }
1225                 } else {
1226                         memcpy(buf, chip->buffers->databuf + col, bytes);
1227                         buf += bytes;
1228                 }
1229
1230                 readlen -= bytes;
1231
1232                 if (!readlen)
1233                         break;
1234
1235                 /* For subsequent reads align to page boundary. */
1236                 col = 0;
1237                 /* Increment page address */
1238                 realpage++;
1239
1240                 page = realpage & chip->pagemask;
1241                 /* Check, if we cross a chip boundary */
1242                 if (!page) {
1243                         chipnr++;
1244                         chip->select_chip(mtd, -1);
1245                         chip->select_chip(mtd, chipnr);
1246                 }
1247
1248                 /* Check, if the chip supports auto page increment
1249                  * or if we have hit a block boundary.
1250                  */
1251                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1252                         sndcmd = 1;
1253         }
1254
1255         ops->retlen = ops->len - (size_t) readlen;
1256         if (oob)
1257                 ops->oobretlen = ops->ooblen - oobreadlen;
1258
1259         if (ret)
1260                 return ret;
1261
1262         if (mtd->ecc_stats.failed - stats.failed)
1263                 return -EBADMSG;
1264
1265         return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1266 }
1267
1268 /**
1269  * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1270  * @mtd:        MTD device structure
1271  * @from:       offset to read from
1272  * @len:        number of bytes to read
1273  * @retlen:     pointer to variable to store the number of read bytes
1274  * @buf:        the databuffer to put data
1275  *
1276  * Get hold of the chip and call nand_do_read
1277  */
1278 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1279                      size_t *retlen, uint8_t *buf)
1280 {
1281         struct nand_chip *chip = mtd->priv;
1282         int ret;
1283
1284         /* Do not allow reads past end of device */
1285         if ((from + len) > mtd->size)
1286                 return -EINVAL;
1287         if (!len)
1288                 return 0;
1289
1290         nand_get_device(chip, mtd, FL_READING);
1291
1292         chip->ops.len = len;
1293         chip->ops.datbuf = buf;
1294         chip->ops.oobbuf = NULL;
1295
1296         ret = nand_do_read_ops(mtd, from, &chip->ops);
1297
1298         *retlen = chip->ops.retlen;
1299
1300         nand_release_device(mtd);
1301
1302         return ret;
1303 }
1304
1305 /**
1306  * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1307  * @mtd:        mtd info structure
1308  * @chip:       nand chip info structure
1309  * @page:       page number to read
1310  * @sndcmd:     flag whether to issue read command or not
1311  */
1312 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1313                              int page, int sndcmd)
1314 {
1315         if (sndcmd) {
1316                 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1317                 sndcmd = 0;
1318         }
1319         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1320         return sndcmd;
1321 }
1322
1323 /**
1324  * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1325  *                          with syndromes
1326  * @mtd:        mtd info structure
1327  * @chip:       nand chip info structure
1328  * @page:       page number to read
1329  * @sndcmd:     flag whether to issue read command or not
1330  */
1331 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1332                                   int page, int sndcmd)
1333 {
1334         uint8_t *buf = chip->oob_poi;
1335         int length = mtd->oobsize;
1336         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1337         int eccsize = chip->ecc.size;
1338         uint8_t *bufpoi = buf;
1339         int i, toread, sndrnd = 0, pos;
1340
1341         chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1342         for (i = 0; i < chip->ecc.steps; i++) {
1343                 if (sndrnd) {
1344                         pos = eccsize + i * (eccsize + chunk);
1345                         if (mtd->writesize > 512)
1346                                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1347                         else
1348                                 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1349                 } else
1350                         sndrnd = 1;
1351                 toread = min_t(int, length, chunk);
1352                 chip->read_buf(mtd, bufpoi, toread);
1353                 bufpoi += toread;
1354                 length -= toread;
1355         }
1356         if (length > 0)
1357                 chip->read_buf(mtd, bufpoi, length);
1358
1359         return 1;
1360 }
1361
1362 /**
1363  * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1364  * @mtd:        mtd info structure
1365  * @chip:       nand chip info structure
1366  * @page:       page number to write
1367  */
1368 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1369                               int page)
1370 {
1371         int status = 0;
1372         const uint8_t *buf = chip->oob_poi;
1373         int length = mtd->oobsize;
1374
1375         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1376         chip->write_buf(mtd, buf, length);
1377         /* Send command to program the OOB data */
1378         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1379
1380         status = chip->waitfunc(mtd, chip);
1381
1382         return status & NAND_STATUS_FAIL ? -EIO : 0;
1383 }
1384
1385 /**
1386  * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1387  *                           with syndrome - only for large page flash !
1388  * @mtd:        mtd info structure
1389  * @chip:       nand chip info structure
1390  * @page:       page number to write
1391  */
1392 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1393                                    struct nand_chip *chip, int page)
1394 {
1395         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1396         int eccsize = chip->ecc.size, length = mtd->oobsize;
1397         int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1398         const uint8_t *bufpoi = chip->oob_poi;
1399
1400         /*
1401          * data-ecc-data-ecc ... ecc-oob
1402          * or
1403          * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1404          */
1405         if (!chip->ecc.prepad && !chip->ecc.postpad) {
1406                 pos = steps * (eccsize + chunk);
1407                 steps = 0;
1408         } else
1409                 pos = eccsize;
1410
1411         chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1412         for (i = 0; i < steps; i++) {
1413                 if (sndcmd) {
1414                         if (mtd->writesize <= 512) {
1415                                 uint32_t fill = 0xFFFFFFFF;
1416
1417                                 len = eccsize;
1418                                 while (len > 0) {
1419                                         int num = min_t(int, len, 4);
1420                                         chip->write_buf(mtd, (uint8_t *)&fill,
1421                                                         num);
1422                                         len -= num;
1423                                 }
1424                         } else {
1425                                 pos = eccsize + i * (eccsize + chunk);
1426                                 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1427                         }
1428                 } else
1429                         sndcmd = 1;
1430                 len = min_t(int, length, chunk);
1431                 chip->write_buf(mtd, bufpoi, len);
1432                 bufpoi += len;
1433                 length -= len;
1434         }
1435         if (length > 0)
1436                 chip->write_buf(mtd, bufpoi, length);
1437
1438         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1439         status = chip->waitfunc(mtd, chip);
1440
1441         return status & NAND_STATUS_FAIL ? -EIO : 0;
1442 }
1443
1444 /**
1445  * nand_do_read_oob - [Intern] NAND read out-of-band
1446  * @mtd:        MTD device structure
1447  * @from:       offset to read from
1448  * @ops:        oob operations description structure
1449  *
1450  * NAND read out-of-band data from the spare area
1451  */
1452 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1453                             struct mtd_oob_ops *ops)
1454 {
1455         int page, realpage, chipnr, sndcmd = 1;
1456         struct nand_chip *chip = mtd->priv;
1457         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1458         int readlen = ops->ooblen;
1459         int len;
1460         uint8_t *buf = ops->oobbuf;
1461
1462         MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08Lx, len = %i\n",
1463                         __func__, (unsigned long long)from, readlen);
1464
1465         if (ops->mode == MTD_OOB_AUTO)
1466                 len = chip->ecc.layout->oobavail;
1467         else
1468                 len = mtd->oobsize;
1469
1470         if (unlikely(ops->ooboffs >= len)) {
1471                 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start read "
1472                                         "outside oob\n", __func__);
1473                 return -EINVAL;
1474         }
1475
1476         /* Do not allow reads past end of device */
1477         if (unlikely(from >= mtd->size ||
1478                      ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1479                                         (from >> chip->page_shift)) * len)) {
1480                 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end "
1481                                         "of device\n", __func__);
1482                 return -EINVAL;
1483         }
1484
1485         chipnr = (int)(from >> chip->chip_shift);
1486         chip->select_chip(mtd, chipnr);
1487
1488         /* Shift to get page */
1489         realpage = (int)(from >> chip->page_shift);
1490         page = realpage & chip->pagemask;
1491
1492         while (1) {
1493                 WATCHDOG_RESET();
1494                 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1495
1496                 len = min(len, readlen);
1497                 buf = nand_transfer_oob(chip, buf, ops, len);
1498
1499                 if (!(chip->options & NAND_NO_READRDY)) {
1500                         /*
1501                          * Apply delay or wait for ready/busy pin. Do this
1502                          * before the AUTOINCR check, so no problems arise if a
1503                          * chip which does auto increment is marked as
1504                          * NOAUTOINCR by the board driver.
1505                          */
1506                         if (!chip->dev_ready)
1507                                 udelay(chip->chip_delay);
1508                         else
1509                                 nand_wait_ready(mtd);
1510                 }
1511
1512                 readlen -= len;
1513                 if (!readlen)
1514                         break;
1515
1516                 /* Increment page address */
1517                 realpage++;
1518
1519                 page = realpage & chip->pagemask;
1520                 /* Check, if we cross a chip boundary */
1521                 if (!page) {
1522                         chipnr++;
1523                         chip->select_chip(mtd, -1);
1524                         chip->select_chip(mtd, chipnr);
1525                 }
1526
1527                 /* Check, if the chip supports auto page increment
1528                  * or if we have hit a block boundary.
1529                  */
1530                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1531                         sndcmd = 1;
1532         }
1533
1534         ops->oobretlen = ops->ooblen;
1535         return 0;
1536 }
1537
1538 /**
1539  * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1540  * @mtd:        MTD device structure
1541  * @from:       offset to read from
1542  * @ops:        oob operation description structure
1543  *
1544  * NAND read data and/or out-of-band data
1545  */
1546 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1547                          struct mtd_oob_ops *ops)
1548 {
1549         struct nand_chip *chip = mtd->priv;
1550         int ret = -ENOTSUPP;
1551
1552         ops->retlen = 0;
1553
1554         /* Do not allow reads past end of device */
1555         if (ops->datbuf && (from + ops->len) > mtd->size) {
1556                 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read "
1557                                 "beyond end of device\n", __func__);
1558                 return -EINVAL;
1559         }
1560
1561         nand_get_device(chip, mtd, FL_READING);
1562
1563         switch (ops->mode) {
1564         case MTD_OOB_PLACE:
1565         case MTD_OOB_AUTO:
1566         case MTD_OOB_RAW:
1567                 break;
1568
1569         default:
1570                 goto out;
1571         }
1572
1573         if (!ops->datbuf)
1574                 ret = nand_do_read_oob(mtd, from, ops);
1575         else
1576                 ret = nand_do_read_ops(mtd, from, ops);
1577
1578 out:
1579         nand_release_device(mtd);
1580         return ret;
1581 }
1582
1583
1584 /**
1585  * nand_write_page_raw - [Intern] raw page write function
1586  * @mtd:        mtd info structure
1587  * @chip:       nand chip info structure
1588  * @buf:        data buffer
1589  *
1590  * Not for syndrome calculating ecc controllers, which use a special oob layout
1591  */
1592 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1593                                 const uint8_t *buf)
1594 {
1595         chip->write_buf(mtd, buf, mtd->writesize);
1596         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1597 }
1598
1599 /**
1600  * nand_write_page_raw_syndrome - [Intern] raw page write function
1601  * @mtd:        mtd info structure
1602  * @chip:       nand chip info structure
1603  * @buf:        data buffer
1604  *
1605  * We need a special oob layout and handling even when ECC isn't checked.
1606  */
1607 static void nand_write_page_raw_syndrome(struct mtd_info *mtd,
1608                                         struct nand_chip *chip,
1609                                         const uint8_t *buf)
1610 {
1611         int eccsize = chip->ecc.size;
1612         int eccbytes = chip->ecc.bytes;
1613         uint8_t *oob = chip->oob_poi;
1614         int steps, size;
1615
1616         for (steps = chip->ecc.steps; steps > 0; steps--) {
1617                 chip->write_buf(mtd, buf, eccsize);
1618                 buf += eccsize;
1619
1620                 if (chip->ecc.prepad) {
1621                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1622                         oob += chip->ecc.prepad;
1623                 }
1624
1625                 chip->read_buf(mtd, oob, eccbytes);
1626                 oob += eccbytes;
1627
1628                 if (chip->ecc.postpad) {
1629                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1630                         oob += chip->ecc.postpad;
1631                 }
1632         }
1633
1634         size = mtd->oobsize - (oob - chip->oob_poi);
1635         if (size)
1636                 chip->write_buf(mtd, oob, size);
1637 }
1638 /**
1639  * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1640  * @mtd:        mtd info structure
1641  * @chip:       nand chip info structure
1642  * @buf:        data buffer
1643  */
1644 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1645                                   const uint8_t *buf)
1646 {
1647         int i, eccsize = chip->ecc.size;
1648         int eccbytes = chip->ecc.bytes;
1649         int eccsteps = chip->ecc.steps;
1650         uint8_t *ecc_calc = chip->buffers->ecccalc;
1651         const uint8_t *p = buf;
1652         uint32_t *eccpos = chip->ecc.layout->eccpos;
1653
1654         /* Software ecc calculation */
1655         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1656                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1657
1658         for (i = 0; i < chip->ecc.total; i++)
1659                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1660
1661         chip->ecc.write_page_raw(mtd, chip, buf);
1662 }
1663
1664 /**
1665  * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1666  * @mtd:        mtd info structure
1667  * @chip:       nand chip info structure
1668  * @buf:        data buffer
1669  */
1670 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1671                                   const uint8_t *buf)
1672 {
1673         int i, eccsize = chip->ecc.size;
1674         int eccbytes = chip->ecc.bytes;
1675         int eccsteps = chip->ecc.steps;
1676         uint8_t *ecc_calc = chip->buffers->ecccalc;
1677         const uint8_t *p = buf;
1678         uint32_t *eccpos = chip->ecc.layout->eccpos;
1679
1680         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1681                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1682                 chip->write_buf(mtd, p, eccsize);
1683                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1684         }
1685
1686         for (i = 0; i < chip->ecc.total; i++)
1687                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1688
1689         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1690 }
1691
1692 /**
1693  * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1694  * @mtd:        mtd info structure
1695  * @chip:       nand chip info structure
1696  * @buf:        data buffer
1697  *
1698  * The hw generator calculates the error syndrome automatically. Therefor
1699  * we need a special oob layout and handling.
1700  */
1701 static void nand_write_page_syndrome(struct mtd_info *mtd,
1702                                     struct nand_chip *chip, const uint8_t *buf)
1703 {
1704         int i, eccsize = chip->ecc.size;
1705         int eccbytes = chip->ecc.bytes;
1706         int eccsteps = chip->ecc.steps;
1707         const uint8_t *p = buf;
1708         uint8_t *oob = chip->oob_poi;
1709
1710         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1711
1712                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1713                 chip->write_buf(mtd, p, eccsize);
1714
1715                 if (chip->ecc.prepad) {
1716                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1717                         oob += chip->ecc.prepad;
1718                 }
1719
1720                 chip->ecc.calculate(mtd, p, oob);
1721                 chip->write_buf(mtd, oob, eccbytes);
1722                 oob += eccbytes;
1723
1724                 if (chip->ecc.postpad) {
1725                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1726                         oob += chip->ecc.postpad;
1727                 }
1728         }
1729
1730         /* Calculate remaining oob bytes */
1731         i = mtd->oobsize - (oob - chip->oob_poi);
1732         if (i)
1733                 chip->write_buf(mtd, oob, i);
1734 }
1735
1736 /**
1737  * nand_write_page - [REPLACEABLE] write one page
1738  * @mtd:        MTD device structure
1739  * @chip:       NAND chip descriptor
1740  * @buf:        the data to write
1741  * @page:       page number to write
1742  * @cached:     cached programming
1743  * @raw:        use _raw version of write_page
1744  */
1745 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1746                            const uint8_t *buf, int page, int cached, int raw)
1747 {
1748         int status;
1749
1750         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1751
1752         if (unlikely(raw))
1753                 chip->ecc.write_page_raw(mtd, chip, buf);
1754         else
1755                 chip->ecc.write_page(mtd, chip, buf);
1756
1757         /*
1758          * Cached progamming disabled for now, Not sure if its worth the
1759          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1760          */
1761         cached = 0;
1762
1763         if (!cached || !(chip->options & NAND_CACHEPRG)) {
1764
1765                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1766                 status = chip->waitfunc(mtd, chip);
1767                 /*
1768                  * See if operation failed and additional status checks are
1769                  * available
1770                  */
1771                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1772                         status = chip->errstat(mtd, chip, FL_WRITING, status,
1773                                                page);
1774
1775                 if (status & NAND_STATUS_FAIL)
1776                         return -EIO;
1777         } else {
1778                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1779                 status = chip->waitfunc(mtd, chip);
1780         }
1781
1782 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1783         /* Send command to read back the data */
1784         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1785
1786         if (chip->verify_buf(mtd, buf, mtd->writesize))
1787                 return -EIO;
1788 #endif
1789         return 0;
1790 }
1791
1792 /**
1793  * nand_fill_oob - [Internal] Transfer client buffer to oob
1794  * @chip:       nand chip structure
1795  * @oob:        oob data buffer
1796  * @ops:        oob ops structure
1797  */
1798 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
1799                                   struct mtd_oob_ops *ops)
1800 {
1801         size_t len = ops->ooblen;
1802
1803         switch (ops->mode) {
1804
1805         case MTD_OOB_PLACE:
1806         case MTD_OOB_RAW:
1807                 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1808                 return oob + len;
1809
1810         case MTD_OOB_AUTO: {
1811                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1812                 uint32_t boffs = 0, woffs = ops->ooboffs;
1813                 size_t bytes = 0;
1814
1815                 for (; free->length && len; free++, len -= bytes) {
1816                         /* Write request not from offset 0 ? */
1817                         if (unlikely(woffs)) {
1818                                 if (woffs >= free->length) {
1819                                         woffs -= free->length;
1820                                         continue;
1821                                 }
1822                                 boffs = free->offset + woffs;
1823                                 bytes = min_t(size_t, len,
1824                                               (free->length - woffs));
1825                                 woffs = 0;
1826                         } else {
1827                                 bytes = min_t(size_t, len, free->length);
1828                                 boffs = free->offset;
1829                         }
1830                         memcpy(chip->oob_poi + boffs, oob, bytes);
1831                         oob += bytes;
1832                 }
1833                 return oob;
1834         }
1835         default:
1836                 BUG();
1837         }
1838         return NULL;
1839 }
1840
1841 #define NOTALIGNED(x)   (x & (chip->subpagesize - 1)) != 0
1842
1843 /**
1844  * nand_do_write_ops - [Internal] NAND write with ECC
1845  * @mtd:        MTD device structure
1846  * @to:         offset to write to
1847  * @ops:        oob operations description structure
1848  *
1849  * NAND write with ECC
1850  */
1851 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1852                              struct mtd_oob_ops *ops)
1853 {
1854         int chipnr, realpage, page, blockmask, column;
1855         struct nand_chip *chip = mtd->priv;
1856         uint32_t writelen = ops->len;
1857         uint8_t *oob = ops->oobbuf;
1858         uint8_t *buf = ops->datbuf;
1859         int ret, subpage;
1860
1861         ops->retlen = 0;
1862         if (!writelen)
1863                 return 0;
1864
1865         column = to & (mtd->writesize - 1);
1866         subpage = column || (writelen & (mtd->writesize - 1));
1867
1868         if (subpage && oob)
1869                 return -EINVAL;
1870
1871         chipnr = (int)(to >> chip->chip_shift);
1872         chip->select_chip(mtd, chipnr);
1873
1874         /* Check, if it is write protected */
1875         if (nand_check_wp(mtd)) {
1876                 printk (KERN_NOTICE "nand_do_write_ops: Device is write protected\n");
1877                 return -EIO;
1878         }
1879
1880         realpage = (int)(to >> chip->page_shift);
1881         page = realpage & chip->pagemask;
1882         blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1883
1884         /* Invalidate the page cache, when we write to the cached page */
1885         if (to <= (chip->pagebuf << chip->page_shift) &&
1886             (chip->pagebuf << chip->page_shift) < (to + ops->len))
1887                 chip->pagebuf = -1;
1888
1889         /* If we're not given explicit OOB data, let it be 0xFF */
1890         if (likely(!oob))
1891                 memset(chip->oob_poi, 0xff, mtd->oobsize);
1892
1893         while (1) {
1894                 WATCHDOG_RESET();
1895
1896                 int bytes = mtd->writesize;
1897                 int cached = writelen > bytes && page != blockmask;
1898                 uint8_t *wbuf = buf;
1899
1900                 /* Partial page write ? */
1901                 if (unlikely(column || writelen < (mtd->writesize - 1))) {
1902                         cached = 0;
1903                         bytes = min_t(int, bytes - column, (int) writelen);
1904                         chip->pagebuf = -1;
1905                         memset(chip->buffers->databuf, 0xff, mtd->writesize);
1906                         memcpy(&chip->buffers->databuf[column], buf, bytes);
1907                         wbuf = chip->buffers->databuf;
1908                 }
1909
1910                 if (unlikely(oob))
1911                         oob = nand_fill_oob(chip, oob, ops);
1912
1913                 ret = chip->write_page(mtd, chip, wbuf, page, cached,
1914                                        (ops->mode == MTD_OOB_RAW));
1915                 if (ret)
1916                         break;
1917
1918                 writelen -= bytes;
1919                 if (!writelen)
1920                         break;
1921
1922                 column = 0;
1923                 buf += bytes;
1924                 realpage++;
1925
1926                 page = realpage & chip->pagemask;
1927                 /* Check, if we cross a chip boundary */
1928                 if (!page) {
1929                         chipnr++;
1930                         chip->select_chip(mtd, -1);
1931                         chip->select_chip(mtd, chipnr);
1932                 }
1933         }
1934
1935         ops->retlen = ops->len - writelen;
1936         if (unlikely(oob))
1937                 ops->oobretlen = ops->ooblen;
1938         return ret;
1939 }
1940
1941 /**
1942  * nand_write - [MTD Interface] NAND write with ECC
1943  * @mtd:        MTD device structure
1944  * @to:         offset to write to
1945  * @len:        number of bytes to write
1946  * @retlen:     pointer to variable to store the number of written bytes
1947  * @buf:        the data to write
1948  *
1949  * NAND write with ECC
1950  */
1951 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
1952                           size_t *retlen, const uint8_t *buf)
1953 {
1954         struct nand_chip *chip = mtd->priv;
1955         int ret;
1956
1957         /* Do not allow writes past end of device */
1958         if ((to + len) > mtd->size)
1959                 return -EINVAL;
1960         if (!len)
1961                 return 0;
1962
1963         nand_get_device(chip, mtd, FL_WRITING);
1964
1965         chip->ops.len = len;
1966         chip->ops.datbuf = (uint8_t *)buf;
1967         chip->ops.oobbuf = NULL;
1968
1969         ret = nand_do_write_ops(mtd, to, &chip->ops);
1970
1971         *retlen = chip->ops.retlen;
1972
1973         nand_release_device(mtd);
1974
1975         return ret;
1976 }
1977
1978 /**
1979  * nand_do_write_oob - [MTD Interface] NAND write out-of-band
1980  * @mtd:        MTD device structure
1981  * @to:         offset to write to
1982  * @ops:        oob operation description structure
1983  *
1984  * NAND write out-of-band
1985  */
1986 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
1987                              struct mtd_oob_ops *ops)
1988 {
1989         int chipnr, page, status, len;
1990         struct nand_chip *chip = mtd->priv;
1991
1992         MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
1993                          __func__, (unsigned int)to, (int)ops->ooblen);
1994
1995         if (ops->mode == MTD_OOB_AUTO)
1996                 len = chip->ecc.layout->oobavail;
1997         else
1998                 len = mtd->oobsize;
1999
2000         /* Do not allow write past end of page */
2001         if ((ops->ooboffs + ops->ooblen) > len) {
2002                 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to write "
2003                                 "past end of page\n", __func__);
2004                 return -EINVAL;
2005         }
2006
2007         if (unlikely(ops->ooboffs >= len)) {
2008                 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start "
2009                                 "write outside oob\n", __func__);
2010                 return -EINVAL;
2011         }
2012
2013         /* Do not allow write past end of device */
2014         if (unlikely(to >= mtd->size ||
2015                      ops->ooboffs + ops->ooblen >
2016                         ((mtd->size >> chip->page_shift) -
2017                          (to >> chip->page_shift)) * len)) {
2018                 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2019                                 "end of device\n", __func__);
2020                 return -EINVAL;
2021         }
2022
2023         chipnr = (int)(to >> chip->chip_shift);
2024         chip->select_chip(mtd, chipnr);
2025
2026         /* Shift to get page */
2027         page = (int)(to >> chip->page_shift);
2028
2029         /*
2030          * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2031          * of my DiskOnChip 2000 test units) will clear the whole data page too
2032          * if we don't do this. I have no clue why, but I seem to have 'fixed'
2033          * it in the doc2000 driver in August 1999.  dwmw2.
2034          */
2035         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2036
2037         /* Check, if it is write protected */
2038         if (nand_check_wp(mtd))
2039                 return -EROFS;
2040
2041         /* Invalidate the page cache, if we write to the cached page */
2042         if (page == chip->pagebuf)
2043                 chip->pagebuf = -1;
2044
2045         memset(chip->oob_poi, 0xff, mtd->oobsize);
2046         nand_fill_oob(chip, ops->oobbuf, ops);
2047         status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2048         memset(chip->oob_poi, 0xff, mtd->oobsize);
2049
2050         if (status)
2051                 return status;
2052
2053         ops->oobretlen = ops->ooblen;
2054
2055         return 0;
2056 }
2057
2058 /**
2059  * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2060  * @mtd:        MTD device structure
2061  * @to:         offset to write to
2062  * @ops:        oob operation description structure
2063  */
2064 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2065                           struct mtd_oob_ops *ops)
2066 {
2067         struct nand_chip *chip = mtd->priv;
2068         int ret = -ENOTSUPP;
2069
2070         ops->retlen = 0;
2071
2072         /* Do not allow writes past end of device */
2073         if (ops->datbuf && (to + ops->len) > mtd->size) {
2074                 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2075                                 "end of device\n", __func__);
2076                 return -EINVAL;
2077         }
2078
2079         nand_get_device(chip, mtd, FL_WRITING);
2080
2081         switch (ops->mode) {
2082         case MTD_OOB_PLACE:
2083         case MTD_OOB_AUTO:
2084         case MTD_OOB_RAW:
2085                 break;
2086
2087         default:
2088                 goto out;
2089         }
2090
2091         if (!ops->datbuf)
2092                 ret = nand_do_write_oob(mtd, to, ops);
2093         else
2094                 ret = nand_do_write_ops(mtd, to, ops);
2095
2096 out:
2097         nand_release_device(mtd);
2098         return ret;
2099 }
2100
2101 /**
2102  * single_erease_cmd - [GENERIC] NAND standard block erase command function
2103  * @mtd:        MTD device structure
2104  * @page:       the page address of the block which will be erased
2105  *
2106  * Standard erase command for NAND chips
2107  */
2108 static void single_erase_cmd(struct mtd_info *mtd, int page)
2109 {
2110         struct nand_chip *chip = mtd->priv;
2111         /* Send commands to erase a block */
2112         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2113         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2114 }
2115
2116 /**
2117  * multi_erease_cmd - [GENERIC] AND specific block erase command function
2118  * @mtd:        MTD device structure
2119  * @page:       the page address of the block which will be erased
2120  *
2121  * AND multi block erase command function
2122  * Erase 4 consecutive blocks
2123  */
2124 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2125 {
2126         struct nand_chip *chip = mtd->priv;
2127         /* Send commands to erase a block */
2128         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2129         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2130         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2131         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2132         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2133 }
2134
2135 /**
2136  * nand_erase - [MTD Interface] erase block(s)
2137  * @mtd:        MTD device structure
2138  * @instr:      erase instruction
2139  *
2140  * Erase one ore more blocks
2141  */
2142 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2143 {
2144         return nand_erase_nand(mtd, instr, 0);
2145 }
2146
2147 #define BBT_PAGE_MASK   0xffffff3f
2148 /**
2149  * nand_erase_nand - [Internal] erase block(s)
2150  * @mtd:        MTD device structure
2151  * @instr:      erase instruction
2152  * @allowbbt:   allow erasing the bbt area
2153  *
2154  * Erase one ore more blocks
2155  */
2156 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2157                     int allowbbt)
2158 {
2159         int page, status, pages_per_block, ret, chipnr;
2160         struct nand_chip *chip = mtd->priv;
2161         loff_t rewrite_bbt[CONFIG_SYS_NAND_MAX_CHIPS] = {0};
2162         unsigned int bbt_masked_page = 0xffffffff;
2163         loff_t len;
2164
2165         MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
2166                                 __func__, (unsigned long long)instr->addr,
2167                                 (unsigned long long)instr->len);
2168
2169         /* Start address must align on block boundary */
2170         if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
2171                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
2172                 return -EINVAL;
2173         }
2174
2175         /* Length must align on block boundary */
2176         if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
2177                 MTDDEBUG (MTD_DEBUG_LEVEL0,
2178                           "nand_erase: Length not block aligned\n");
2179                 return -EINVAL;
2180         }
2181
2182         /* Do not allow erase past end of device */
2183         if ((instr->len + instr->addr) > mtd->size) {
2184                 MTDDEBUG (MTD_DEBUG_LEVEL0,
2185                           "nand_erase: Erase past end of device\n");
2186                 return -EINVAL;
2187         }
2188
2189         instr->fail_addr = 0xffffffff;
2190
2191         /* Grab the lock and see if the device is available */
2192         nand_get_device(chip, mtd, FL_ERASING);
2193
2194         /* Shift to get first page */
2195         page = (int)(instr->addr >> chip->page_shift);
2196         chipnr = (int)(instr->addr >> chip->chip_shift);
2197
2198         /* Calculate pages in each block */
2199         pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2200
2201         /* Select the NAND device */
2202         chip->select_chip(mtd, chipnr);
2203
2204         /* Check, if it is write protected */
2205         if (nand_check_wp(mtd)) {
2206                 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
2207                                         __func__);
2208                 instr->state = MTD_ERASE_FAILED;
2209                 goto erase_exit;
2210         }
2211
2212         /*
2213          * If BBT requires refresh, set the BBT page mask to see if the BBT
2214          * should be rewritten. Otherwise the mask is set to 0xffffffff which
2215          * can not be matched. This is also done when the bbt is actually
2216          * erased to avoid recusrsive updates
2217          */
2218         if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2219                 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2220
2221         /* Loop through the pages */
2222         len = instr->len;
2223
2224         instr->state = MTD_ERASING;
2225
2226         while (len) {
2227                 WATCHDOG_RESET();
2228                 /*
2229                  * heck if we have a bad block, we do not erase bad blocks !
2230                  */
2231                 if (!instr->scrub && nand_block_checkbad(mtd, ((loff_t) page) <<
2232                                         chip->page_shift, 0, allowbbt)) {
2233                         printk(KERN_WARNING "%s: attempt to erase a bad block "
2234                                         "at page 0x%08x\n", __func__, page);
2235                         instr->state = MTD_ERASE_FAILED;
2236                         goto erase_exit;
2237                 }
2238
2239                 /*
2240                  * Invalidate the page cache, if we erase the block which
2241                  * contains the current cached page
2242                  */
2243                 if (page <= chip->pagebuf && chip->pagebuf <
2244                     (page + pages_per_block))
2245                         chip->pagebuf = -1;
2246
2247                 chip->erase_cmd(mtd, page & chip->pagemask);
2248
2249                 status = chip->waitfunc(mtd, chip);
2250
2251                 /*
2252                  * See if operation failed and additional status checks are
2253                  * available
2254                  */
2255                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2256                         status = chip->errstat(mtd, chip, FL_ERASING,
2257                                                status, page);
2258
2259                 /* See if block erase succeeded */
2260                 if (status & NAND_STATUS_FAIL) {
2261                         MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, "
2262                                         "page 0x%08x\n", __func__, page);
2263                         instr->state = MTD_ERASE_FAILED;
2264                         instr->fail_addr =
2265                                 ((loff_t)page << chip->page_shift);
2266                         goto erase_exit;
2267                 }
2268
2269                 /*
2270                  * If BBT requires refresh, set the BBT rewrite flag to the
2271                  * page being erased
2272                  */
2273                 if (bbt_masked_page != 0xffffffff &&
2274                     (page & BBT_PAGE_MASK) == bbt_masked_page)
2275                         rewrite_bbt[chipnr] =
2276                                 ((loff_t)page << chip->page_shift);
2277
2278                 /* Increment page address and decrement length */
2279                 len -= (1 << chip->phys_erase_shift);
2280                 page += pages_per_block;
2281
2282                 /* Check, if we cross a chip boundary */
2283                 if (len && !(page & chip->pagemask)) {
2284                         chipnr++;
2285                         chip->select_chip(mtd, -1);
2286                         chip->select_chip(mtd, chipnr);
2287
2288                         /*
2289                          * If BBT requires refresh and BBT-PERCHIP, set the BBT
2290                          * page mask to see if this BBT should be rewritten
2291                          */
2292                         if (bbt_masked_page != 0xffffffff &&
2293                             (chip->bbt_td->options & NAND_BBT_PERCHIP))
2294                                 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2295                                         BBT_PAGE_MASK;
2296                 }
2297         }
2298         instr->state = MTD_ERASE_DONE;
2299
2300 erase_exit:
2301
2302         ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2303
2304         /* Deselect and wake up anyone waiting on the device */
2305         nand_release_device(mtd);
2306
2307         /* Do call back function */
2308         if (!ret)
2309                 mtd_erase_callback(instr);
2310
2311         /*
2312          * If BBT requires refresh and erase was successful, rewrite any
2313          * selected bad block tables
2314          */
2315         if (bbt_masked_page == 0xffffffff || ret)
2316                 return ret;
2317
2318         for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2319                 if (!rewrite_bbt[chipnr])
2320                         continue;
2321                 /* update the BBT for chip */
2322                 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: nand_update_bbt "
2323                         "(%d:0x%0llx 0x%0x)\n", __func__, chipnr,
2324                         rewrite_bbt[chipnr], chip->bbt_td->pages[chipnr]);
2325                 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2326         }
2327
2328         /* Return more or less happy */
2329         return ret;
2330 }
2331
2332 /**
2333  * nand_sync - [MTD Interface] sync
2334  * @mtd:        MTD device structure
2335  *
2336  * Sync is actually a wait for chip ready function
2337  */
2338 static void nand_sync(struct mtd_info *mtd)
2339 {
2340         struct nand_chip *chip = mtd->priv;
2341
2342         MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__);
2343
2344         /* Grab the lock and see if the device is available */
2345         nand_get_device(chip, mtd, FL_SYNCING);
2346         /* Release it and go back */
2347         nand_release_device(mtd);
2348 }
2349
2350 /**
2351  * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2352  * @mtd:        MTD device structure
2353  * @offs:       offset relative to mtd start
2354  */
2355 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2356 {
2357         /* Check for invalid offset */
2358         if (offs > mtd->size)
2359                 return -EINVAL;
2360
2361         return nand_block_checkbad(mtd, offs, 1, 0);
2362 }
2363
2364 /**
2365  * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2366  * @mtd:        MTD device structure
2367  * @ofs:        offset relative to mtd start
2368  */
2369 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2370 {
2371         struct nand_chip *chip = mtd->priv;
2372         int ret;
2373
2374         if ((ret = nand_block_isbad(mtd, ofs))) {
2375                 /* If it was bad already, return success and do nothing. */
2376                 if (ret > 0)
2377                         return 0;
2378                 return ret;
2379         }
2380
2381         return chip->block_markbad(mtd, ofs);
2382 }
2383
2384 /*
2385  * Set default functions
2386  */
2387 static void nand_set_defaults(struct nand_chip *chip, int busw)
2388 {
2389         /* check for proper chip_delay setup, set 20us if not */
2390         if (!chip->chip_delay)
2391                 chip->chip_delay = 20;
2392
2393         /* check, if a user supplied command function given */
2394         if (chip->cmdfunc == NULL)
2395                 chip->cmdfunc = nand_command;
2396
2397         /* check, if a user supplied wait function given */
2398         if (chip->waitfunc == NULL)
2399                 chip->waitfunc = nand_wait;
2400
2401         if (!chip->select_chip)
2402                 chip->select_chip = nand_select_chip;
2403         if (!chip->read_byte)
2404                 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2405         if (!chip->read_word)
2406                 chip->read_word = nand_read_word;
2407         if (!chip->block_bad)
2408                 chip->block_bad = nand_block_bad;
2409         if (!chip->block_markbad)
2410                 chip->block_markbad = nand_default_block_markbad;
2411         if (!chip->write_buf)
2412                 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2413         if (!chip->read_buf)
2414                 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2415         if (!chip->verify_buf)
2416                 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2417         if (!chip->scan_bbt)
2418                 chip->scan_bbt = nand_default_bbt;
2419         if (!chip->controller)
2420                 chip->controller = &chip->hwcontrol;
2421 }
2422
2423 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
2424 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2425 {
2426         int i;
2427
2428         while (len--) {
2429                 crc ^= *p++ << 8;
2430                 for (i = 0; i < 8; i++)
2431                         crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2432         }
2433
2434         return crc;
2435 }
2436
2437 /*
2438  * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise
2439  */
2440 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
2441                                         int *busw)
2442 {
2443         struct nand_onfi_params *p = &chip->onfi_params;
2444         int i;
2445         int val;
2446
2447         chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2448         if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2449                 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2450                 return 0;
2451
2452         printk(KERN_INFO "ONFI flash detected\n");
2453         chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2454         for (i = 0; i < 3; i++) {
2455                 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2456                 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2457                                 le16_to_cpu(p->crc)) {
2458                         printk(KERN_INFO "ONFI param page %d valid\n", i);
2459                         break;
2460                 }
2461         }
2462
2463         if (i == 3)
2464                 return 0;
2465
2466         /* check version */
2467         val = le16_to_cpu(p->revision);
2468         if (val & (1 << 5))
2469                 chip->onfi_version = 23;
2470         else if (val & (1 << 4))
2471                 chip->onfi_version = 22;
2472         else if (val & (1 << 3))
2473                 chip->onfi_version = 21;
2474         else if (val & (1 << 2))
2475                 chip->onfi_version = 20;
2476         else if (val & (1 << 1))
2477                 chip->onfi_version = 10;
2478         else
2479                 chip->onfi_version = 0;
2480
2481         if (!chip->onfi_version) {
2482                 printk(KERN_INFO "%s: unsupported ONFI version: %d\n",
2483                                                                 __func__, val);
2484                 return 0;
2485         }
2486
2487         if (!mtd->name)
2488                 mtd->name = p->model;
2489
2490         mtd->writesize = le32_to_cpu(p->byte_per_page);
2491         mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2492         mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
2493         chip->chipsize = (uint64_t)le32_to_cpu(p->blocks_per_lun) * mtd->erasesize;
2494         *busw = 0;
2495         if (le16_to_cpu(p->features) & 1)
2496                 *busw = NAND_BUSWIDTH_16;
2497
2498         return 1;
2499 }
2500 #else
2501 static inline int nand_flash_detect_onfi(struct mtd_info *mtd,
2502                                         struct nand_chip *chip,
2503                                         int *busw)
2504 {
2505         return 0;
2506 }
2507 #endif
2508
2509 static void nand_flash_detect_non_onfi(struct mtd_info *mtd,
2510                                         struct nand_chip *chip,
2511                                         const struct nand_flash_dev *type,
2512                                         int *busw)
2513 {
2514         /* Newer devices have all the information in additional id bytes */
2515         if (!type->pagesize) {
2516                 int extid;
2517                 /* The 3rd id byte holds MLC / multichip data */
2518                 chip->cellinfo = chip->read_byte(mtd);
2519                 /* The 4th id byte is the important one */
2520                 extid = chip->read_byte(mtd);
2521                 /* Calc pagesize */
2522                 mtd->writesize = 1024 << (extid & 0x3);
2523                 extid >>= 2;
2524                 /* Calc oobsize */
2525                 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
2526                 extid >>= 2;
2527                 /* Calc blocksize. Blocksize is multiples of 64KiB */
2528                 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2529                 extid >>= 2;
2530                 /* Get buswidth information */
2531                 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2532
2533         } else {
2534                 /*
2535                  * Old devices have chip data hardcoded in the device id table
2536                  */
2537                 mtd->erasesize = type->erasesize;
2538                 mtd->writesize = type->pagesize;
2539                 mtd->oobsize = mtd->writesize / 32;
2540                 *busw = type->options & NAND_BUSWIDTH_16;
2541         }
2542 }
2543
2544 /*
2545  * Get the flash and manufacturer id and lookup if the type is supported
2546  */
2547 static const struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2548                                                   struct nand_chip *chip,
2549                                                   int busw,
2550                                                   int *maf_id, int *dev_id,
2551                                                   const struct nand_flash_dev *type)
2552 {
2553         int ret, maf_idx;
2554         int tmp_id, tmp_manf;
2555
2556         /* Select the device */
2557         chip->select_chip(mtd, 0);
2558
2559         /*
2560          * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2561          * after power-up
2562          */
2563         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2564
2565         /* Send the command for reading device ID */
2566         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2567
2568         /* Read manufacturer and device IDs */
2569         *maf_id = chip->read_byte(mtd);
2570         *dev_id = chip->read_byte(mtd);
2571
2572         /* Try again to make sure, as some systems the bus-hold or other
2573          * interface concerns can cause random data which looks like a
2574          * possibly credible NAND flash to appear. If the two results do
2575          * not match, ignore the device completely.
2576          */
2577
2578         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2579
2580         /* Read manufacturer and device IDs */
2581
2582         tmp_manf = chip->read_byte(mtd);
2583         tmp_id = chip->read_byte(mtd);
2584
2585         if (tmp_manf != *maf_id || tmp_id != *dev_id) {
2586                 printk(KERN_INFO "%s: second ID read did not match "
2587                        "%02x,%02x against %02x,%02x\n", __func__,
2588                        *maf_id, *dev_id, tmp_manf, tmp_id);
2589                 return ERR_PTR(-ENODEV);
2590         }
2591
2592         if (!type)
2593                 type = nand_flash_ids;
2594
2595         for (; type->name != NULL; type++)
2596                 if (*dev_id == type->id)
2597                         break;
2598
2599         if (!type->name) {
2600                 /* supress warning if there is no nand */
2601                 if (*maf_id != 0x00 && *maf_id != 0xff &&
2602                     *dev_id  != 0x00 && *dev_id  != 0xff)
2603                         printk(KERN_INFO "%s: unknown NAND device: "
2604                                 "Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
2605                                 __func__, *maf_id, *dev_id);
2606                 return ERR_PTR(-ENODEV);
2607         }
2608
2609         if (!mtd->name)
2610                 mtd->name = type->name;
2611
2612         chip->chipsize = (uint64_t)type->chipsize << 20;
2613         chip->onfi_version = 0;
2614
2615         ret = nand_flash_detect_onfi(mtd, chip, &busw);
2616         if (!ret)
2617                 nand_flash_detect_non_onfi(mtd, chip, type, &busw);
2618
2619         /* Get chip options, preserve non chip based options */
2620         chip->options &= ~NAND_CHIPOPTIONS_MSK;
2621         chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
2622
2623         /*
2624          * Set chip as a default. Board drivers can override it, if necessary
2625          */
2626         chip->options |= NAND_NO_AUTOINCR;
2627
2628         /* Try to identify manufacturer */
2629         for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2630                 if (nand_manuf_ids[maf_idx].id == *maf_id)
2631                         break;
2632         }
2633
2634         /*
2635          * Check, if buswidth is correct. Hardware drivers should set
2636          * chip correct !
2637          */
2638         if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2639                 printk(KERN_INFO "NAND device: Manufacturer ID:"
2640                        " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2641                        *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2642                 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2643                        (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2644                        busw ? 16 : 8);
2645                 return ERR_PTR(-EINVAL);
2646         }
2647
2648         /* Calculate the address shift from the page size */
2649         chip->page_shift = ffs(mtd->writesize) - 1;
2650         /* Convert chipsize to number of pages per chip -1. */
2651         chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2652
2653         chip->bbt_erase_shift = chip->phys_erase_shift =
2654                 ffs(mtd->erasesize) - 1;
2655         if (chip->chipsize & 0xffffffff)
2656                 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
2657         else
2658                 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)) + 31;
2659
2660         /* Set the bad block position */
2661         chip->badblockpos = mtd->writesize > 512 ?
2662                 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2663
2664         /* Check if chip is a not a samsung device. Do not clear the
2665          * options for chips which are not having an extended id.
2666          */
2667         if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2668                 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2669
2670         /* Check for AND chips with 4 page planes */
2671         if (chip->options & NAND_4PAGE_ARRAY)
2672                 chip->erase_cmd = multi_erase_cmd;
2673         else
2674                 chip->erase_cmd = single_erase_cmd;
2675
2676         /* Do not replace user supplied command function ! */
2677         if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2678                 chip->cmdfunc = nand_command_lp;
2679
2680         MTDDEBUG (MTD_DEBUG_LEVEL0, "NAND device: Manufacturer ID:"
2681                   " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, *dev_id,
2682                   nand_manuf_ids[maf_idx].name, type->name);
2683
2684         return type;
2685 }
2686
2687 /**
2688  * nand_scan_ident - [NAND Interface] Scan for the NAND device
2689  * @mtd:             MTD device structure
2690  * @maxchips:        Number of chips to scan for
2691  * @table:           Alternative NAND ID table
2692  *
2693  * This is the first phase of the normal nand_scan() function. It
2694  * reads the flash ID and sets up MTD fields accordingly.
2695  *
2696  * The mtd->owner field must be set to the module of the caller.
2697  */
2698 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
2699                     const struct nand_flash_dev *table)
2700 {
2701         int i, busw, nand_maf_id, nand_dev_id;
2702         struct nand_chip *chip = mtd->priv;
2703         const struct nand_flash_dev *type;
2704
2705         /* Get buswidth to select the correct functions */
2706         busw = chip->options & NAND_BUSWIDTH_16;
2707         /* Set the default functions */
2708         nand_set_defaults(chip, busw);
2709
2710         /* Read the flash type */
2711         type = nand_get_flash_type(mtd, chip, busw,
2712                                 &nand_maf_id, &nand_dev_id, table);
2713
2714         if (IS_ERR(type)) {
2715 #ifndef CONFIG_SYS_NAND_QUIET_TEST
2716                 printk(KERN_WARNING "No NAND device found!!!\n");
2717 #endif
2718                 chip->select_chip(mtd, -1);
2719                 return PTR_ERR(type);
2720         }
2721
2722         /* Check for a chip array */
2723         for (i = 1; i < maxchips; i++) {
2724                 chip->select_chip(mtd, i);
2725                 /* See comment in nand_get_flash_type for reset */
2726                 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2727                 /* Send the command for reading device ID */
2728                 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2729                 /* Read manufacturer and device IDs */
2730                 if (nand_maf_id != chip->read_byte(mtd) ||
2731                     nand_dev_id != chip->read_byte(mtd))
2732                         break;
2733         }
2734 #ifdef DEBUG
2735         if (i > 1)
2736                 printk(KERN_INFO "%d NAND chips detected\n", i);
2737 #endif
2738
2739         /* Store the number of chips and calc total size for mtd */
2740         chip->numchips = i;
2741         mtd->size = i * chip->chipsize;
2742
2743         return 0;
2744 }
2745
2746
2747 /**
2748  * nand_scan_tail - [NAND Interface] Scan for the NAND device
2749  * @mtd:            MTD device structure
2750  *
2751  * This is the second phase of the normal nand_scan() function. It
2752  * fills out all the uninitialized function pointers with the defaults
2753  * and scans for a bad block table if appropriate.
2754  */
2755 int nand_scan_tail(struct mtd_info *mtd)
2756 {
2757         int i;
2758         struct nand_chip *chip = mtd->priv;
2759
2760         if (!(chip->options & NAND_OWN_BUFFERS))
2761                 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2762         if (!chip->buffers)
2763                 return -ENOMEM;
2764
2765         /* Set the internal oob buffer location, just after the page data */
2766         chip->oob_poi = chip->buffers->databuf + mtd->writesize;
2767
2768         /*
2769          * If no default placement scheme is given, select an appropriate one
2770          */
2771         if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
2772                 switch (mtd->oobsize) {
2773                 case 8:
2774                         chip->ecc.layout = &nand_oob_8;
2775                         break;
2776                 case 16:
2777                         chip->ecc.layout = &nand_oob_16;
2778                         break;
2779                 case 64:
2780                         chip->ecc.layout = &nand_oob_64;
2781                         break;
2782                 case 128:
2783                         chip->ecc.layout = &nand_oob_128;
2784                         break;
2785                 default:
2786                         printk(KERN_WARNING "No oob scheme defined for "
2787                                "oobsize %d\n", mtd->oobsize);
2788                 }
2789         }
2790
2791         if (!chip->write_page)
2792                 chip->write_page = nand_write_page;
2793
2794         /*
2795          * check ECC mode, default to software if 3byte/512byte hardware ECC is
2796          * selected and we have 256 byte pagesize fallback to software ECC
2797          */
2798
2799         switch (chip->ecc.mode) {
2800         case NAND_ECC_HW_OOB_FIRST:
2801                 /* Similar to NAND_ECC_HW, but a separate read_page handle */
2802                 if (!chip->ecc.calculate || !chip->ecc.correct ||
2803                      !chip->ecc.hwctl) {
2804                         printk(KERN_WARNING "No ECC functions supplied; "
2805                                "Hardware ECC not possible\n");
2806                         BUG();
2807                 }
2808                 if (!chip->ecc.read_page)
2809                         chip->ecc.read_page = nand_read_page_hwecc_oob_first;
2810
2811         case NAND_ECC_HW:
2812                 /* Use standard hwecc read page function ? */
2813                 if (!chip->ecc.read_page)
2814                         chip->ecc.read_page = nand_read_page_hwecc;
2815                 if (!chip->ecc.write_page)
2816                         chip->ecc.write_page = nand_write_page_hwecc;
2817                 if (!chip->ecc.read_page_raw)
2818                         chip->ecc.read_page_raw = nand_read_page_raw;
2819                 if (!chip->ecc.write_page_raw)
2820                         chip->ecc.write_page_raw = nand_write_page_raw;
2821                 if (!chip->ecc.read_oob)
2822                         chip->ecc.read_oob = nand_read_oob_std;
2823                 if (!chip->ecc.write_oob)
2824                         chip->ecc.write_oob = nand_write_oob_std;
2825
2826         case NAND_ECC_HW_SYNDROME:
2827                 if ((!chip->ecc.calculate || !chip->ecc.correct ||
2828                      !chip->ecc.hwctl) &&
2829                     (!chip->ecc.read_page ||
2830                      chip->ecc.read_page == nand_read_page_hwecc ||
2831                      !chip->ecc.write_page ||
2832                      chip->ecc.write_page == nand_write_page_hwecc)) {
2833                         printk(KERN_WARNING "No ECC functions supplied; "
2834                                "Hardware ECC not possible\n");
2835                         BUG();
2836                 }
2837                 /* Use standard syndrome read/write page function ? */
2838                 if (!chip->ecc.read_page)
2839                         chip->ecc.read_page = nand_read_page_syndrome;
2840                 if (!chip->ecc.write_page)
2841                         chip->ecc.write_page = nand_write_page_syndrome;
2842                 if (!chip->ecc.read_page_raw)
2843                         chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
2844                 if (!chip->ecc.write_page_raw)
2845                         chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
2846                 if (!chip->ecc.read_oob)
2847                         chip->ecc.read_oob = nand_read_oob_syndrome;
2848                 if (!chip->ecc.write_oob)
2849                         chip->ecc.write_oob = nand_write_oob_syndrome;
2850
2851                 if (mtd->writesize >= chip->ecc.size)
2852                         break;
2853                 printk(KERN_WARNING "%d byte HW ECC not possible on "
2854                        "%d byte page size, fallback to SW ECC\n",
2855                        chip->ecc.size, mtd->writesize);
2856                 chip->ecc.mode = NAND_ECC_SOFT;
2857
2858         case NAND_ECC_SOFT:
2859                 chip->ecc.calculate = nand_calculate_ecc;
2860                 chip->ecc.correct = nand_correct_data;
2861                 chip->ecc.read_page = nand_read_page_swecc;
2862                 chip->ecc.read_subpage = nand_read_subpage;
2863                 chip->ecc.write_page = nand_write_page_swecc;
2864                 chip->ecc.read_page_raw = nand_read_page_raw;
2865                 chip->ecc.write_page_raw = nand_write_page_raw;
2866                 chip->ecc.read_oob = nand_read_oob_std;
2867                 chip->ecc.write_oob = nand_write_oob_std;
2868                 chip->ecc.size = 256;
2869                 chip->ecc.bytes = 3;
2870                 break;
2871
2872         case NAND_ECC_SOFT_BCH:
2873                 if (!mtd_nand_has_bch()) {
2874                         printk(KERN_WARNING "CONFIG_MTD_ECC_BCH not enabled\n");
2875                         return -EINVAL;
2876                 }
2877                 chip->ecc.calculate = nand_bch_calculate_ecc;
2878                 chip->ecc.correct = nand_bch_correct_data;
2879                 chip->ecc.read_page = nand_read_page_swecc;
2880                 chip->ecc.read_subpage = nand_read_subpage;
2881                 chip->ecc.write_page = nand_write_page_swecc;
2882                 chip->ecc.read_page_raw = nand_read_page_raw;
2883                 chip->ecc.write_page_raw = nand_write_page_raw;
2884                 chip->ecc.read_oob = nand_read_oob_std;
2885                 chip->ecc.write_oob = nand_write_oob_std;
2886                 /*
2887                  * Board driver should supply ecc.size and ecc.bytes values to
2888                  * select how many bits are correctable; see nand_bch_init()
2889                  * for details.
2890                  * Otherwise, default to 4 bits for large page devices
2891                  */
2892                 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
2893                         chip->ecc.size = 512;
2894                         chip->ecc.bytes = 7;
2895                 }
2896                 chip->ecc.priv = nand_bch_init(mtd,
2897                                                chip->ecc.size,
2898                                                chip->ecc.bytes,
2899                                                &chip->ecc.layout);
2900                 if (!chip->ecc.priv)
2901                         printk(KERN_WARNING "BCH ECC initialization failed!\n");
2902
2903                 break;
2904
2905         case NAND_ECC_NONE:
2906                 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2907                        "This is not recommended !!\n");
2908                 chip->ecc.read_page = nand_read_page_raw;
2909                 chip->ecc.write_page = nand_write_page_raw;
2910                 chip->ecc.read_oob = nand_read_oob_std;
2911                 chip->ecc.read_page_raw = nand_read_page_raw;
2912                 chip->ecc.write_page_raw = nand_write_page_raw;
2913                 chip->ecc.write_oob = nand_write_oob_std;
2914                 chip->ecc.size = mtd->writesize;
2915                 chip->ecc.bytes = 0;
2916                 break;
2917
2918         default:
2919                 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
2920                        chip->ecc.mode);
2921                 BUG();
2922         }
2923
2924         /*
2925          * The number of bytes available for a client to place data into
2926          * the out of band area
2927          */
2928         chip->ecc.layout->oobavail = 0;
2929         for (i = 0; chip->ecc.layout->oobfree[i].length
2930                         && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
2931                 chip->ecc.layout->oobavail +=
2932                         chip->ecc.layout->oobfree[i].length;
2933         mtd->oobavail = chip->ecc.layout->oobavail;
2934
2935         /*
2936          * Set the number of read / write steps for one page depending on ECC
2937          * mode
2938          */
2939         chip->ecc.steps = mtd->writesize / chip->ecc.size;
2940         if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
2941                 printk(KERN_WARNING "Invalid ecc parameters\n");
2942                 BUG();
2943         }
2944         chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
2945
2946         /*
2947          * Allow subpage writes up to ecc.steps. Not possible for MLC
2948          * FLASH.
2949          */
2950         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2951             !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
2952                 switch (chip->ecc.steps) {
2953                 case 2:
2954                         mtd->subpage_sft = 1;
2955                         break;
2956                 case 4:
2957                 case 8:
2958                 case 16:
2959                         mtd->subpage_sft = 2;
2960                         break;
2961                 }
2962         }
2963         chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
2964
2965         /* Initialize state */
2966         chip->state = FL_READY;
2967
2968         /* De-select the device */
2969         chip->select_chip(mtd, -1);
2970
2971         /* Invalidate the pagebuffer reference */
2972         chip->pagebuf = -1;
2973
2974         /* Fill in remaining MTD driver data */
2975         mtd->type = MTD_NANDFLASH;
2976         mtd->flags = MTD_CAP_NANDFLASH;
2977         mtd->erase = nand_erase;
2978         mtd->point = NULL;
2979         mtd->unpoint = NULL;
2980         mtd->read = nand_read;
2981         mtd->write = nand_write;
2982         mtd->read_oob = nand_read_oob;
2983         mtd->write_oob = nand_write_oob;
2984         mtd->sync = nand_sync;
2985         mtd->lock = NULL;
2986         mtd->unlock = NULL;
2987         mtd->block_isbad = nand_block_isbad;
2988         mtd->block_markbad = nand_block_markbad;
2989
2990         /* propagate ecc.layout to mtd_info */
2991         mtd->ecclayout = chip->ecc.layout;
2992
2993         /* Check, if we should skip the bad block table scan */
2994         if (chip->options & NAND_SKIP_BBTSCAN)
2995                 chip->options |= NAND_BBT_SCANNED;
2996
2997         return 0;
2998 }
2999
3000 /**
3001  * nand_scan - [NAND Interface] Scan for the NAND device
3002  * @mtd:        MTD device structure
3003  * @maxchips:   Number of chips to scan for
3004  *
3005  * This fills out all the uninitialized function pointers
3006  * with the defaults.
3007  * The flash ID is read and the mtd/chip structures are
3008  * filled with the appropriate values.
3009  * The mtd->owner field must be set to the module of the caller
3010  *
3011  */
3012 int nand_scan(struct mtd_info *mtd, int maxchips)
3013 {
3014         int ret;
3015
3016         ret = nand_scan_ident(mtd, maxchips, NULL);
3017         if (!ret)
3018                 ret = nand_scan_tail(mtd);
3019         return ret;
3020 }
3021
3022 /**
3023  * nand_release - [NAND Interface] Free resources held by the NAND device
3024  * @mtd:        MTD device structure
3025 */
3026 void nand_release(struct mtd_info *mtd)
3027 {
3028         struct nand_chip *chip = mtd->priv;
3029
3030         if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3031                 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3032
3033 #ifdef CONFIG_MTD_PARTITIONS
3034         /* Deregister partitions */
3035         del_mtd_partitions(mtd);
3036 #endif
3037
3038         /* Free bad block table memory */
3039         kfree(chip->bbt);
3040         if (!(chip->options & NAND_OWN_BUFFERS))
3041                 kfree(chip->buffers);
3042 }