drivers/mtd/nand/nand_base.c

   1 /*
   2  *  drivers/mtd/nand.c
   3  *
   4  *  Overview:
   5  *   This is the generic MTD driver for NAND flash devices. It should be
   6  *   capable of working with almost all NAND chips currently available.
   7  *   Basic support for AG-AND chips is provided.
   8  *
   9  *      Additional technical information is available on
  10  *      http://www.linux-mtd.infradead.org/doc/nand.html
  11  *
  12  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  13  *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
  14  *
  15  *  Credits:
  16  *      David Woodhouse for adding multichip support
  17  *
  18  *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  19  *      rework for 2K page size chips
  20  *
  21  *  TODO:
  22  *      Enable cached programming for 2k page size chips
  23  *      Check, if mtd->ecctype should be set to MTD_ECC_HW
  24  *      if we have HW ecc support.
  25  *      The AG-AND chips have nice features for speed improvement,
  26  *      which are not supported yet. Read / program 4 pages in one go.
  27  *      BBT table is not serialized, has to be fixed
  28  *
  29  * This program is free software; you can redistribute it and/or modify
  30  * it under the terms of the GNU General Public License version 2 as
  31  * published by the Free Software Foundation.
  32  *
  33  */
  34
  35 #include <common.h>
  36
  37 #define ENOTSUPP        524     /* Operation is not supported */
  38
  39 #include <malloc.h>
  40 #include <watchdog.h>
  41 #include <linux/err.h>
  42 #include <linux/mtd/compat.h>
  43 #include <linux/mtd/mtd.h>
  44 #include <linux/mtd/nand.h>
  45 #include <linux/mtd/nand_ecc.h>
  46
  47 #ifdef CONFIG_MTD_PARTITIONS
  48 #include <linux/mtd/partitions.h>
  49 #endif
  50
  51 #include <asm/io.h>
  52 #include <asm/errno.h>
  53
  54 /*
  55  * CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting
  56  * a flash.  NAND flash is initialized prior to interrupts so standard timers
  57  * can't be used.  CONFIG_SYS_NAND_RESET_CNT should be set to a value
  58  * which is greater than (max NAND reset time / NAND status read time).
  59  * A conservative default of 200000 (500 us / 25 ns) is used as a default.
  60  */
  61 #ifndef CONFIG_SYS_NAND_RESET_CNT
  62 #define CONFIG_SYS_NAND_RESET_CNT 200000
  63 #endif
  64
  65 /* Define default oob placement schemes for large and small page devices */
  66 static struct nand_ecclayout nand_oob_8 = {
  67         .eccbytes = 3,
  68         .eccpos = {0, 1, 2},
  69         .oobfree = {
  70                 {.offset = 3,
  71                  .length = 2},
  72                 {.offset = 6,
  73                  .length = 2}}
  74 };
  75
  76 static struct nand_ecclayout nand_oob_16 = {
  77         .eccbytes = 6,
  78         .eccpos = {0, 1, 2, 3, 6, 7},
  79         .oobfree = {
  80                 {.offset = 8,
  81                  . length = 8}}
  82 };
  83
  84 static struct nand_ecclayout nand_oob_64 = {
  85         .eccbytes = 24,
  86         .eccpos = {
  87                    40, 41, 42, 43, 44, 45, 46, 47,
  88                    48, 49, 50, 51, 52, 53, 54, 55,
  89                    56, 57, 58, 59, 60, 61, 62, 63},
  90         .oobfree = {
  91                 {.offset = 2,
  92                  .length = 38}}
  93 };
  94
  95 static struct nand_ecclayout nand_oob_128 = {
  96         .eccbytes = 48,
  97         .eccpos = {
  98                     80,  81,  82,  83,  84,  85,  86,  87,
  99                     88,  89,  90,  91,  92,  93,  94,  95,
 100                     96,  97,  98,  99, 100, 101, 102, 103,
 101                    104, 105, 106, 107, 108, 109, 110, 111,
 102                    112, 113, 114, 115, 116, 117, 118, 119,
 103                    120, 121, 122, 123, 124, 125, 126, 127},
 104         .oobfree = {
 105                 {.offset = 2,
 106                  .length = 78}}
 107 };
 108
 109
 110 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
 111                            int new_state);
 112
 113 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
 114                              struct mtd_oob_ops *ops);
 115
 116 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this);
 117
 118 /**
 119  * nand_release_device - [GENERIC] release chip
 120  * @mtd:        MTD device structure
 121  *
 122  * Deselect, release chip lock and wake up anyone waiting on the device
 123  */
 124 static void nand_release_device (struct mtd_info *mtd)
 125 {
 126         struct nand_chip *this = mtd->priv;
 127         this->select_chip(mtd, -1);     /* De-select the NAND device */
 128 }
 129
 130 /**
 131  * nand_read_byte - [DEFAULT] read one byte from the chip
 132  * @mtd:        MTD device structure
 133  *
 134  * Default read function for 8bit buswith
 135  */
 136 static uint8_t nand_read_byte(struct mtd_info *mtd)
 137 {
 138         struct nand_chip *chip = mtd->priv;
 139         return readb(chip->IO_ADDR_R);
 140 }
 141
 142 /**
 143  * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
 144  * @mtd:        MTD device structure
 145  *
 146  * Default read function for 16bit buswith with
 147  * endianess conversion
 148  */
 149 static uint8_t nand_read_byte16(struct mtd_info *mtd)
 150 {
 151         struct nand_chip *chip = mtd->priv;
 152         return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
 153 }
 154
 155 /**
 156  * nand_read_word - [DEFAULT] read one word from the chip
 157  * @mtd:        MTD device structure
 158  *
 159  * Default read function for 16bit buswith without
 160  * endianess conversion
 161  */
 162 static u16 nand_read_word(struct mtd_info *mtd)
 163 {
 164         struct nand_chip *chip = mtd->priv;
 165         return readw(chip->IO_ADDR_R);
 166 }
 167
 168 /**
 169  * nand_select_chip - [DEFAULT] control CE line
 170  * @mtd:        MTD device structure
 171  * @chipnr:     chipnumber to select, -1 for deselect
 172  *
 173  * Default select function for 1 chip devices.
 174  */
 175 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 176 {
 177         struct nand_chip *chip = mtd->priv;
 178
 179         switch (chipnr) {
 180         case -1:
 181                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
 182                 break;
 183         case 0:
 184                 break;
 185
 186         default:
 187                 BUG();
 188         }
 189 }
 190
 191 /**
 192  * nand_write_buf - [DEFAULT] write buffer to chip
 193  * @mtd:        MTD device structure
 194  * @buf:        data buffer
 195  * @len:        number of bytes to write
 196  *
 197  * Default write function for 8bit buswith
 198  */
 199 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 200 {
 201         int i;
 202         struct nand_chip *chip = mtd->priv;
 203
 204         for (i = 0; i < len; i++)
 205                 writeb(buf[i], chip->IO_ADDR_W);
 206 }
 207
 208 /**
 209  * nand_read_buf - [DEFAULT] read chip data into buffer
 210  * @mtd:        MTD device structure
 211  * @buf:        buffer to store date
 212  * @len:        number of bytes to read
 213  *
 214  * Default read function for 8bit buswith
 215  */
 216 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 217 {
 218         int i;
 219         struct nand_chip *chip = mtd->priv;
 220
 221         for (i = 0; i < len; i++)
 222                 buf[i] = readb(chip->IO_ADDR_R);
 223 }
 224
 225 /**
 226  * nand_verify_buf - [DEFAULT] Verify chip data against buffer
 227  * @mtd:        MTD device structure
 228  * @buf:        buffer containing the data to compare
 229  * @len:        number of bytes to compare
 230  *
 231  * Default verify function for 8bit buswith
 232  */
 233 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 234 {
 235         int i;
 236         struct nand_chip *chip = mtd->priv;
 237
 238         for (i = 0; i < len; i++)
 239                 if (buf[i] != readb(chip->IO_ADDR_R))
 240                         return -EFAULT;
 241         return 0;
 242 }
 243
 244 /**
 245  * nand_write_buf16 - [DEFAULT] write buffer to chip
 246  * @mtd:        MTD device structure
 247  * @buf:        data buffer
 248  * @len:        number of bytes to write
 249  *
 250  * Default write function for 16bit buswith
 251  */
 252 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 253 {
 254         int i;
 255         struct nand_chip *chip = mtd->priv;
 256         u16 *p = (u16 *) buf;
 257         len >>= 1;
 258
 259         for (i = 0; i < len; i++)
 260                 writew(p[i], chip->IO_ADDR_W);
 261
 262 }
 263
 264 /**
 265  * nand_read_buf16 - [DEFAULT] read chip data into buffer
 266  * @mtd:        MTD device structure
 267  * @buf:        buffer to store date
 268  * @len:        number of bytes to read
 269  *
 270  * Default read function for 16bit buswith
 271  */
 272 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 273 {
 274         int i;
 275         struct nand_chip *chip = mtd->priv;
 276         u16 *p = (u16 *) buf;
 277         len >>= 1;
 278
 279         for (i = 0; i < len; i++)
 280                 p[i] = readw(chip->IO_ADDR_R);
 281 }
 282
 283 /**
 284  * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
 285  * @mtd:        MTD device structure
 286  * @buf:        buffer containing the data to compare
 287  * @len:        number of bytes to compare
 288  *
 289  * Default verify function for 16bit buswith
 290  */
 291 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 292 {
 293         int i;
 294         struct nand_chip *chip = mtd->priv;
 295         u16 *p = (u16 *) buf;
 296         len >>= 1;
 297
 298         for (i = 0; i < len; i++)
 299                 if (p[i] != readw(chip->IO_ADDR_R))
 300                         return -EFAULT;
 301
 302         return 0;
 303 }
 304
 305 /**
 306  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
 307  * @mtd:        MTD device structure
 308  * @ofs:        offset from device start
 309  * @getchip:    0, if the chip is already selected
 310  *
 311  * Check, if the block is bad.
 312  */
 313 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 314 {
 315         int page, chipnr, res = 0;
 316         struct nand_chip *chip = mtd->priv;
 317         u16 bad;
 318
 319         page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 320
 321         if (getchip) {
 322                 chipnr = (int)(ofs >> chip->chip_shift);
 323
 324                 nand_get_device(chip, mtd, FL_READING);
 325
 326                 /* Select the NAND device */
 327                 chip->select_chip(mtd, chipnr);
 328         }
 329
 330         if (chip->options & NAND_BUSWIDTH_16) {
 331                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
 332                               page);
 333                 bad = cpu_to_le16(chip->read_word(mtd));
 334                 if (chip->badblockpos & 0x1)
 335                         bad >>= 8;
 336                 if ((bad & 0xFF) != 0xff)
 337                         res = 1;
 338         } else {
 339                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
 340                 if (chip->read_byte(mtd) != 0xff)
 341                         res = 1;
 342         }
 343
 344         if (getchip)
 345                 nand_release_device(mtd);
 346
 347         return res;
 348 }
 349
 350 /**
 351  * nand_default_block_markbad - [DEFAULT] mark a block bad
 352  * @mtd:        MTD device structure
 353  * @ofs:        offset from device start
 354  *
 355  * This is the default implementation, which can be overridden by
 356  * a hardware specific driver.
 357 */
 358 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 359 {
 360         struct nand_chip *chip = mtd->priv;
 361         uint8_t buf[2] = { 0, 0 };
 362         int block, ret;
 363
 364         /* Get block number */
 365         block = (int)(ofs >> chip->bbt_erase_shift);
 366         if (chip->bbt)
 367                 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
 368
 369         /* Do we have a flash based bad block table ? */
 370         if (chip->options & NAND_USE_FLASH_BBT)
 371                 ret = nand_update_bbt(mtd, ofs);
 372         else {
 373                 /* We write two bytes, so we dont have to mess with 16 bit
 374                  * access
 375                  */
 376                 nand_get_device(chip, mtd, FL_WRITING);
 377                 ofs += mtd->oobsize;
 378                 chip->ops.len = chip->ops.ooblen = 2;
 379                 chip->ops.datbuf = NULL;
 380                 chip->ops.oobbuf = buf;
 381                 chip->ops.ooboffs = chip->badblockpos & ~0x01;
 382
 383                 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
 384                 nand_release_device(mtd);
 385         }
 386         if (!ret)
 387                 mtd->ecc_stats.badblocks++;
 388
 389         return ret;
 390 }
 391
 392 /**
 393  * nand_check_wp - [GENERIC] check if the chip is write protected
 394  * @mtd:        MTD device structure
 395  * Check, if the device is write protected
 396  *
 397  * The function expects, that the device is already selected
 398  */
 399 static int nand_check_wp(struct mtd_info *mtd)
 400 {
 401         struct nand_chip *chip = mtd->priv;
 402         /* Check the WP bit */
 403         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 404         return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
 405 }
 406
 407 /**
 408  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
 409  * @mtd:        MTD device structure
 410  * @ofs:        offset from device start
 411  * @getchip:    0, if the chip is already selected
 412  * @allowbbt:   1, if its allowed to access the bbt area
 413  *
 414  * Check, if the block is bad. Either by reading the bad block table or
 415  * calling of the scan function.
 416  */
 417 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
 418                                int allowbbt)
 419 {
 420         struct nand_chip *chip = mtd->priv;
 421
 422         if (!(chip->options & NAND_BBT_SCANNED)) {
 423                 chip->options |= NAND_BBT_SCANNED;
 424                 chip->scan_bbt(mtd);
 425         }
 426
 427         if (!chip->bbt)
 428                 return chip->block_bad(mtd, ofs, getchip);
 429
 430         /* Return info from the table */
 431         return nand_isbad_bbt(mtd, ofs, allowbbt);
 432 }
 433
 434 /*
 435  * Wait for the ready pin, after a command
 436  * The timeout is catched later.
 437  */
 438 void nand_wait_ready(struct mtd_info *mtd)
 439 {
 440         struct nand_chip *chip = mtd->priv;
 441         u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
 442         u32 time_start;
 443
 444         time_start = get_timer(0);
 445
 446         /* wait until command is processed or timeout occures */
 447         while (get_timer(time_start) < timeo) {
 448                 if (chip->dev_ready)
 449                         if (chip->dev_ready(mtd))
 450                                 break;
 451         }
 452 }
 453
 454 /**
 455  * nand_command - [DEFAULT] Send command to NAND device
 456  * @mtd:        MTD device structure
 457  * @command:    the command to be sent
 458  * @column:     the column address for this command, -1 if none
 459  * @page_addr:  the page address for this command, -1 if none
 460  *
 461  * Send command to NAND device. This function is used for small page
 462  * devices (256/512 Bytes per page)
 463  */
 464 static void nand_command(struct mtd_info *mtd, unsigned int command,
 465                          int column, int page_addr)
 466 {
 467         register struct nand_chip *chip = mtd->priv;
 468         int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
 469         uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
 470
 471         /*
 472          * Write out the command to the device.
 473          */
 474         if (command == NAND_CMD_SEQIN) {
 475                 int readcmd;
 476
 477                 if (column >= mtd->writesize) {
 478                         /* OOB area */
 479                         column -= mtd->writesize;
 480                         readcmd = NAND_CMD_READOOB;
 481                 } else if (column < 256) {
 482                         /* First 256 bytes --> READ0 */
 483                         readcmd = NAND_CMD_READ0;
 484                 } else {
 485                         column -= 256;
 486                         readcmd = NAND_CMD_READ1;
 487                 }
 488                 chip->cmd_ctrl(mtd, readcmd, ctrl);
 489                 ctrl &= ~NAND_CTRL_CHANGE;
 490         }
 491         chip->cmd_ctrl(mtd, command, ctrl);
 492
 493         /*
 494          * Address cycle, when necessary
 495          */
 496         ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
 497         /* Serially input address */
 498         if (column != -1) {
 499                 /* Adjust columns for 16 bit buswidth */
 500                 if (chip->options & NAND_BUSWIDTH_16)
 501                         column >>= 1;
 502                 chip->cmd_ctrl(mtd, column, ctrl);
 503                 ctrl &= ~NAND_CTRL_CHANGE;
 504         }
 505         if (page_addr != -1) {
 506                 chip->cmd_ctrl(mtd, page_addr, ctrl);
 507                 ctrl &= ~NAND_CTRL_CHANGE;
 508                 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
 509                 /* One more address cycle for devices > 32MiB */
 510                 if (chip->chipsize > (32 << 20))
 511                         chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
 512         }
 513         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 514
 515         /*
 516          * program and erase have their own busy handlers
 517          * status and sequential in needs no delay
 518          */
 519         switch (command) {
 520
 521         case NAND_CMD_PAGEPROG:
 522         case NAND_CMD_ERASE1:
 523         case NAND_CMD_ERASE2:
 524         case NAND_CMD_SEQIN:
 525         case NAND_CMD_STATUS:
 526                 return;
 527
 528         case NAND_CMD_RESET:
 529                 if (chip->dev_ready)
 530                         break;
 531                 udelay(chip->chip_delay);
 532                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 533                                NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 534                 chip->cmd_ctrl(mtd,
 535                                NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 536                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
 537                         (rst_sts_cnt--));
 538                 return;
 539
 540                 /* This applies to read commands */
 541         default:
 542                 /*
 543                  * If we don't have access to the busy pin, we apply the given
 544                  * command delay
 545                  */
 546                 if (!chip->dev_ready) {
 547                         udelay(chip->chip_delay);
 548                         return;
 549                 }
 550         }
 551         /* Apply this short delay always to ensure that we do wait tWB in
 552          * any case on any machine. */
 553         ndelay(100);
 554
 555         nand_wait_ready(mtd);
 556 }
 557
 558 /**
 559  * nand_command_lp - [DEFAULT] Send command to NAND large page device
 560  * @mtd:        MTD device structure
 561  * @command:    the command to be sent
 562  * @column:     the column address for this command, -1 if none
 563  * @page_addr:  the page address for this command, -1 if none
 564  *
 565  * Send command to NAND device. This is the version for the new large page
 566  * devices We dont have the separate regions as we have in the small page
 567  * devices.  We must emulate NAND_CMD_READOOB to keep the code compatible.
 568  */
 569 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
 570                             int column, int page_addr)
 571 {
 572         register struct nand_chip *chip = mtd->priv;
 573         uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
 574
 575         /* Emulate NAND_CMD_READOOB */
 576         if (command == NAND_CMD_READOOB) {
 577                 column += mtd->writesize;
 578                 command = NAND_CMD_READ0;
 579         }
 580
 581         /* Command latch cycle */
 582         chip->cmd_ctrl(mtd, command & 0xff,
 583                        NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 584
 585         if (column != -1 || page_addr != -1) {
 586                 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
 587
 588                 /* Serially input address */
 589                 if (column != -1) {
 590                         /* Adjust columns for 16 bit buswidth */
 591                         if (chip->options & NAND_BUSWIDTH_16)
 592                                 column >>= 1;
 593                         chip->cmd_ctrl(mtd, column, ctrl);
 594                         ctrl &= ~NAND_CTRL_CHANGE;
 595                         chip->cmd_ctrl(mtd, column >> 8, ctrl);
 596                 }
 597                 if (page_addr != -1) {
 598                         chip->cmd_ctrl(mtd, page_addr, ctrl);
 599                         chip->cmd_ctrl(mtd, page_addr >> 8,
 600                                        NAND_NCE | NAND_ALE);
 601                         /* One more address cycle for devices > 128MiB */
 602                         if (chip->chipsize > (128 << 20))
 603                                 chip->cmd_ctrl(mtd, page_addr >> 16,
 604                                                NAND_NCE | NAND_ALE);
 605                 }
 606         }
 607         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 608
 609         /*
 610          * program and erase have their own busy handlers
 611          * status, sequential in, and deplete1 need no delay
 612          */
 613         switch (command) {
 614
 615         case NAND_CMD_CACHEDPROG:
 616         case NAND_CMD_PAGEPROG:
 617         case NAND_CMD_ERASE1:
 618         case NAND_CMD_ERASE2:
 619         case NAND_CMD_SEQIN:
 620         case NAND_CMD_RNDIN:
 621         case NAND_CMD_STATUS:
 622         case NAND_CMD_DEPLETE1:
 623                 return;
 624
 625                 /*
 626                  * read error status commands require only a short delay
 627                  */
 628         case NAND_CMD_STATUS_ERROR:
 629         case NAND_CMD_STATUS_ERROR0:
 630         case NAND_CMD_STATUS_ERROR1:
 631         case NAND_CMD_STATUS_ERROR2:
 632         case NAND_CMD_STATUS_ERROR3:
 633                 udelay(chip->chip_delay);
 634                 return;
 635
 636         case NAND_CMD_RESET:
 637                 if (chip->dev_ready)
 638                         break;
 639                 udelay(chip->chip_delay);
 640                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 641                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 642                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 643                                NAND_NCE | NAND_CTRL_CHANGE);
 644                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
 645                         (rst_sts_cnt--));
 646                 return;
 647
 648         case NAND_CMD_RNDOUT:
 649                 /* No ready / busy check necessary */
 650                 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
 651                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 652                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 653                                NAND_NCE | NAND_CTRL_CHANGE);
 654                 return;
 655
 656         case NAND_CMD_READ0:
 657                 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
 658                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 659                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 660                                NAND_NCE | NAND_CTRL_CHANGE);
 661
 662                 /* This applies to read commands */
 663         default:
 664                 /*
 665                  * If we don't have access to the busy pin, we apply the given
 666                  * command delay
 667                  */
 668                 if (!chip->dev_ready) {
 669                         udelay(chip->chip_delay);
 670                         return;
 671                 }
 672         }
 673
 674         /* Apply this short delay always to ensure that we do wait tWB in
 675          * any case on any machine. */
 676         ndelay(100);
 677
 678         nand_wait_ready(mtd);
 679 }
 680
 681 /**
 682  * nand_get_device - [GENERIC] Get chip for selected access
 683  * @chip:       the nand chip descriptor
 684  * @mtd:        MTD device structure
 685  * @new_state:  the state which is requested
 686  *
 687  * Get the device and lock it for exclusive access
 688  */
 689 static int nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state)
 690 {
 691         this->state = new_state;
 692         return 0;
 693 }
 694
 695 /**
 696  * nand_wait - [DEFAULT]  wait until the command is done
 697  * @mtd:        MTD device structure
 698  * @chip:       NAND chip structure
 699  *
 700  * Wait for command done. This applies to erase and program only
 701  * Erase can take up to 400ms and program up to 20ms according to
 702  * general NAND and SmartMedia specs
 703  */
 704 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this)
 705 {
 706         unsigned long   timeo;
 707         int state = this->state;
 708         u32 time_start;
 709
 710         if (state == FL_ERASING)
 711                 timeo = (CONFIG_SYS_HZ * 400) / 1000;
 712         else
 713                 timeo = (CONFIG_SYS_HZ * 20) / 1000;
 714
 715         if ((state == FL_ERASING) && (this->options & NAND_IS_AND))
 716                 this->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
 717         else
 718                 this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 719
 720         time_start = get_timer(0);
 721
 722         while (1) {
 723                 if (get_timer(time_start) > timeo) {
 724                         printf("Timeout!");
 725                         return 0x01;
 726                 }
 727
 728                 if (this->dev_ready) {
 729                         if (this->dev_ready(mtd))
 730                                 break;
 731                 } else {
 732                         if (this->read_byte(mtd) & NAND_STATUS_READY)
 733                                 break;
 734                 }
 735         }
 736 #ifdef PPCHAMELON_NAND_TIMER_HACK
 737         time_start = get_timer(0);
 738         while (get_timer(time_start) < 10)
 739                 ;
 740 #endif /*  PPCHAMELON_NAND_TIMER_HACK */
 741
 742         return this->read_byte(mtd);
 743 }
 744
 745 /**
 746  * nand_read_page_raw - [Intern] read raw page data without ecc
 747  * @mtd:        mtd info structure
 748  * @chip:       nand chip info structure
 749  * @buf:        buffer to store read data
 750  * @page:       page number to read
 751  *
 752  * Not for syndrome calculating ecc controllers, which use a special oob layout
 753  */
 754 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
 755                               uint8_t *buf, int page)
 756 {
 757         chip->read_buf(mtd, buf, mtd->writesize);
 758         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 759         return 0;
 760 }
 761
 762 /**
 763  * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
 764  * @mtd:        mtd info structure
 765  * @chip:       nand chip info structure
 766  * @buf:        buffer to store read data
 767  * @page:       page number to read
 768  *
 769  * We need a special oob layout and handling even when OOB isn't used.
 770  */
 771 static int nand_read_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
 772                               uint8_t *buf, int page)
 773 {
 774         int eccsize = chip->ecc.size;
 775         int eccbytes = chip->ecc.bytes;
 776         uint8_t *oob = chip->oob_poi;
 777         int steps, size;
 778
 779         for (steps = chip->ecc.steps; steps > 0; steps--) {
 780                 chip->read_buf(mtd, buf, eccsize);
 781                 buf += eccsize;
 782
 783                 if (chip->ecc.prepad) {
 784                         chip->read_buf(mtd, oob, chip->ecc.prepad);
 785                         oob += chip->ecc.prepad;
 786                 }
 787
 788                 chip->read_buf(mtd, oob, eccbytes);
 789                 oob += eccbytes;
 790
 791                 if (chip->ecc.postpad) {
 792                         chip->read_buf(mtd, oob, chip->ecc.postpad);
 793                         oob += chip->ecc.postpad;
 794                 }
 795         }
 796
 797         size = mtd->oobsize - (oob - chip->oob_poi);
 798         if (size)
 799                 chip->read_buf(mtd, oob, size);
 800
 801         return 0;
 802 }
 803
 804 /**
 805  * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
 806  * @mtd:        mtd info structure
 807  * @chip:       nand chip info structure
 808  * @buf:        buffer to store read data
 809  * @page:       page number to read
 810  */
 811 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
 812                                 uint8_t *buf, int page)
 813 {
 814         int i, eccsize = chip->ecc.size;
 815         int eccbytes = chip->ecc.bytes;
 816         int eccsteps = chip->ecc.steps;
 817         uint8_t *p = buf;
 818         uint8_t *ecc_calc = chip->buffers->ecccalc;
 819         uint8_t *ecc_code = chip->buffers->ecccode;
 820         uint32_t *eccpos = chip->ecc.layout->eccpos;
 821
 822         chip->ecc.read_page_raw(mtd, chip, buf, page);
 823
 824         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
 825                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 826
 827         for (i = 0; i < chip->ecc.total; i++)
 828                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 829
 830         eccsteps = chip->ecc.steps;
 831         p = buf;
 832
 833         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 834                 int stat;
 835
 836                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 837                 if (stat < 0)
 838                         mtd->ecc_stats.failed++;
 839                 else
 840                         mtd->ecc_stats.corrected += stat;
 841         }
 842         return 0;
 843 }
 844
 845 /**
 846  * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
 847  * @mtd:        mtd info structure
 848  * @chip:       nand chip info structure
 849  * @data_offs:  offset of requested data within the page
 850  * @readlen:    data length
 851  * @bufpoi:     buffer to store read data
 852  */
 853 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
 854 {
 855         int start_step, end_step, num_steps;
 856         uint32_t *eccpos = chip->ecc.layout->eccpos;
 857         uint8_t *p;
 858         int data_col_addr, i, gaps = 0;
 859         int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
 860         int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
 861
 862         /* Column address wihin the page aligned to ECC size (256bytes). */
 863         start_step = data_offs / chip->ecc.size;
 864         end_step = (data_offs + readlen - 1) / chip->ecc.size;
 865         num_steps = end_step - start_step + 1;
 866
 867         /* Data size aligned to ECC ecc.size*/
 868         datafrag_len = num_steps * chip->ecc.size;
 869         eccfrag_len = num_steps * chip->ecc.bytes;
 870
 871         data_col_addr = start_step * chip->ecc.size;
 872         /* If we read not a page aligned data */
 873         if (data_col_addr != 0)
 874                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
 875
 876         p = bufpoi + data_col_addr;
 877         chip->read_buf(mtd, p, datafrag_len);
 878
 879         /* Calculate  ECC */
 880         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
 881                 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
 882
 883         /* The performance is faster if to position offsets
 884            according to ecc.pos. Let make sure here that
 885            there are no gaps in ecc positions */
 886         for (i = 0; i < eccfrag_len - 1; i++) {
 887                 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
 888                         eccpos[i + start_step * chip->ecc.bytes + 1]) {
 889                         gaps = 1;
 890                         break;
 891                 }
 892         }
 893         if (gaps) {
 894                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
 895                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 896         } else {
 897                 /* send the command to read the particular ecc bytes */
 898                 /* take care about buswidth alignment in read_buf */
 899                 aligned_pos = eccpos[start_step * chip->ecc.bytes] & ~(busw - 1);
 900                 aligned_len = eccfrag_len;
 901                 if (eccpos[start_step * chip->ecc.bytes] & (busw - 1))
 902                         aligned_len++;
 903                 if (eccpos[(start_step + num_steps) * chip->ecc.bytes] & (busw - 1))
 904                         aligned_len++;
 905
 906                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize + aligned_pos, -1);
 907                 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
 908         }
 909
 910         for (i = 0; i < eccfrag_len; i++)
 911                 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + start_step * chip->ecc.bytes]];
 912
 913         p = bufpoi + data_col_addr;
 914         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
 915                 int stat;
 916
 917                 stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
 918                 if (stat == -1)
 919                         mtd->ecc_stats.failed++;
 920                 else
 921                         mtd->ecc_stats.corrected += stat;
 922         }
 923         return 0;
 924 }
 925
 926 /**
 927  * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
 928  * @mtd:        mtd info structure
 929  * @chip:       nand chip info structure
 930  * @buf:        buffer to store read data
 931  * @page:       page number to read
 932  *
 933  * Not for syndrome calculating ecc controllers which need a special oob layout
 934  */
 935 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
 936                                 uint8_t *buf, int page)
 937 {
 938         int i, eccsize = chip->ecc.size;
 939         int eccbytes = chip->ecc.bytes;
 940         int eccsteps = chip->ecc.steps;
 941         uint8_t *p = buf;
 942         uint8_t *ecc_calc = chip->buffers->ecccalc;
 943         uint8_t *ecc_code = chip->buffers->ecccode;
 944         uint32_t *eccpos = chip->ecc.layout->eccpos;
 945
 946         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 947                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 948                 chip->read_buf(mtd, p, eccsize);
 949                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 950         }
 951         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 952
 953         for (i = 0; i < chip->ecc.total; i++)
 954                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 955
 956         eccsteps = chip->ecc.steps;
 957         p = buf;
 958
 959         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 960                 int stat;
 961
 962                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 963                 if (stat < 0)
 964                         mtd->ecc_stats.failed++;
 965                 else
 966                         mtd->ecc_stats.corrected += stat;
 967         }
 968         return 0;
 969 }
 970
 971 /**
 972  * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
 973  * @mtd:        mtd info structure
 974  * @chip:       nand chip info structure
 975  * @buf:        buffer to store read data
 976  * @page:       page number to read
 977  *
 978  * Hardware ECC for large page chips, require OOB to be read first.
 979  * For this ECC mode, the write_page method is re-used from ECC_HW.
 980  * These methods read/write ECC from the OOB area, unlike the
 981  * ECC_HW_SYNDROME support with multiple ECC steps, follows the
 982  * "infix ECC" scheme and reads/writes ECC from the data area, by
 983  * overwriting the NAND manufacturer bad block markings.
 984  */
 985 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
 986         struct nand_chip *chip, uint8_t *buf, int page)
 987 {
 988         int i, eccsize = chip->ecc.size;
 989         int eccbytes = chip->ecc.bytes;
 990         int eccsteps = chip->ecc.steps;
 991         uint8_t *p = buf;
 992         uint8_t *ecc_code = chip->buffers->ecccode;
 993         uint32_t *eccpos = chip->ecc.layout->eccpos;
 994         uint8_t *ecc_calc = chip->buffers->ecccalc;
 995
 996         /* Read the OOB area first */
 997         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
 998         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 999         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1000
1001         for (i = 0; i < chip->ecc.total; i++)
1002                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1003
1004         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1005                 int stat;
1006
1007                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1008                 chip->read_buf(mtd, p, eccsize);
1009                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1010
1011                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1012                 if (stat < 0)
1013                         mtd->ecc_stats.failed++;
1014                 else
1015                         mtd->ecc_stats.corrected += stat;
1016         }
1017         return 0;
1018 }
1019
1020 /**
1021  * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
1022  * @mtd:        mtd info structure
1023  * @chip:       nand chip info structure
1024  * @buf:        buffer to store read data
1025  * @page:       page number to read
1026  *
1027  * The hw generator calculates the error syndrome automatically. Therefor
1028  * we need a special oob layout and handling.
1029  */
1030 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1031                                    uint8_t *buf, int page)
1032 {
1033         int i, eccsize = chip->ecc.size;
1034         int eccbytes = chip->ecc.bytes;
1035         int eccsteps = chip->ecc.steps;
1036         uint8_t *p = buf;
1037         uint8_t *oob = chip->oob_poi;
1038
1039         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1040                 int stat;
1041
1042                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1043                 chip->read_buf(mtd, p, eccsize);
1044
1045                 if (chip->ecc.prepad) {
1046                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1047                         oob += chip->ecc.prepad;
1048                 }
1049
1050                 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1051                 chip->read_buf(mtd, oob, eccbytes);
1052                 stat = chip->ecc.correct(mtd, p, oob, NULL);
1053
1054                 if (stat < 0)
1055                         mtd->ecc_stats.failed++;
1056                 else
1057                         mtd->ecc_stats.corrected += stat;
1058
1059                 oob += eccbytes;
1060
1061                 if (chip->ecc.postpad) {
1062                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1063                         oob += chip->ecc.postpad;
1064                 }
1065         }
1066
1067         /* Calculate remaining oob bytes */
1068         i = mtd->oobsize - (oob - chip->oob_poi);
1069         if (i)
1070                 chip->read_buf(mtd, oob, i);
1071
1072         return 0;
1073 }
1074
1075 /**
1076  * nand_transfer_oob - [Internal] Transfer oob to client buffer
1077  * @chip:       nand chip structure
1078  * @oob:        oob destination address
1079  * @ops:        oob ops structure
1080  * @len:        size of oob to transfer
1081  */
1082 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1083                                   struct mtd_oob_ops *ops, size_t len)
1084 {
1085         switch(ops->mode) {
1086
1087         case MTD_OOB_PLACE:
1088         case MTD_OOB_RAW:
1089                 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1090                 return oob + len;
1091
1092         case MTD_OOB_AUTO: {
1093                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1094                 uint32_t boffs = 0, roffs = ops->ooboffs;
1095                 size_t bytes = 0;
1096
1097                 for(; free->length && len; free++, len -= bytes) {
1098                         /* Read request not from offset 0 ? */
1099                         if (unlikely(roffs)) {
1100                                 if (roffs >= free->length) {
1101                                         roffs -= free->length;
1102                                         continue;
1103                                 }
1104                                 boffs = free->offset + roffs;
1105                                 bytes = min_t(size_t, len,
1106                                               (free->length - roffs));
1107                                 roffs = 0;
1108                         } else {
1109                                 bytes = min_t(size_t, len, free->length);
1110                                 boffs = free->offset;
1111                         }
1112                         memcpy(oob, chip->oob_poi + boffs, bytes);
1113                         oob += bytes;
1114                 }
1115                 return oob;
1116         }
1117         default:
1118                 BUG();
1119         }
1120         return NULL;
1121 }
1122
1123 /**
1124  * nand_do_read_ops - [Internal] Read data with ECC
1125  *
1126  * @mtd:        MTD device structure
1127  * @from:       offset to read from
1128  * @ops:        oob ops structure
1129  *
1130  * Internal function. Called with chip held.
1131  */
1132 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1133                             struct mtd_oob_ops *ops)
1134 {
1135         int chipnr, page, realpage, col, bytes, aligned;
1136         struct nand_chip *chip = mtd->priv;
1137         struct mtd_ecc_stats stats;
1138         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1139         int sndcmd = 1;
1140         int ret = 0;
1141         uint32_t readlen = ops->len;
1142         uint32_t oobreadlen = ops->ooblen;
1143         uint8_t *bufpoi, *oob, *buf;
1144
1145         stats = mtd->ecc_stats;
1146
1147         chipnr = (int)(from >> chip->chip_shift);
1148         chip->select_chip(mtd, chipnr);
1149
1150         realpage = (int)(from >> chip->page_shift);
1151         page = realpage & chip->pagemask;
1152
1153         col = (int)(from & (mtd->writesize - 1));
1154
1155         buf = ops->datbuf;
1156         oob = ops->oobbuf;
1157
1158         while(1) {
1159                 bytes = min(mtd->writesize - col, readlen);
1160                 aligned = (bytes == mtd->writesize);
1161
1162                 /* Is the current page in the buffer ? */
1163                 if (realpage != chip->pagebuf || oob) {
1164                         bufpoi = aligned ? buf : chip->buffers->databuf;
1165
1166                         if (likely(sndcmd)) {
1167                                 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1168                                 sndcmd = 0;
1169                         }
1170
1171                         /* Now read the page into the buffer */
1172                         if (unlikely(ops->mode == MTD_OOB_RAW))
1173                                 ret = chip->ecc.read_page_raw(mtd, chip,
1174                                                 bufpoi, page);
1175                         else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1176                                 ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi);
1177                         else
1178                                 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1179                                                 page);
1180                         if (ret < 0)
1181                                 break;
1182
1183                         /* Transfer not aligned data */
1184                         if (!aligned) {
1185                                 if (!NAND_SUBPAGE_READ(chip) && !oob)
1186                                         chip->pagebuf = realpage;
1187                                 memcpy(buf, chip->buffers->databuf + col, bytes);
1188                         }
1189
1190                         buf += bytes;
1191
1192                         if (unlikely(oob)) {
1193                                 /* Raw mode does data:oob:data:oob */
1194                                 if (ops->mode != MTD_OOB_RAW) {
1195                                         int toread = min(oobreadlen,
1196                                                 chip->ecc.layout->oobavail);
1197                                         if (toread) {
1198                                                 oob = nand_transfer_oob(chip,
1199                                                         oob, ops, toread);
1200                                                 oobreadlen -= toread;
1201                                         }
1202                                 } else
1203                                         buf = nand_transfer_oob(chip,
1204                                                 buf, ops, mtd->oobsize);
1205                         }
1206
1207                         if (!(chip->options & NAND_NO_READRDY)) {
1208                                 /*
1209                                  * Apply delay or wait for ready/busy pin. Do
1210                                  * this before the AUTOINCR check, so no
1211                                  * problems arise if a chip which does auto
1212                                  * increment is marked as NOAUTOINCR by the
1213                                  * board driver.
1214                                  */
1215                                 if (!chip->dev_ready)
1216                                         udelay(chip->chip_delay);
1217                                 else
1218                                         nand_wait_ready(mtd);
1219                         }
1220                 } else {
1221                         memcpy(buf, chip->buffers->databuf + col, bytes);
1222                         buf += bytes;
1223                 }
1224
1225                 readlen -= bytes;
1226
1227                 if (!readlen)
1228                         break;
1229
1230                 /* For subsequent reads align to page boundary. */
1231                 col = 0;
1232                 /* Increment page address */
1233                 realpage++;
1234
1235                 page = realpage & chip->pagemask;
1236                 /* Check, if we cross a chip boundary */
1237                 if (!page) {
1238                         chipnr++;
1239                         chip->select_chip(mtd, -1);
1240                         chip->select_chip(mtd, chipnr);
1241                 }
1242
1243                 /* Check, if the chip supports auto page increment
1244                  * or if we have hit a block boundary.
1245                  */
1246                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1247                         sndcmd = 1;
1248         }
1249
1250         ops->retlen = ops->len - (size_t) readlen;
1251         if (oob)
1252                 ops->oobretlen = ops->ooblen - oobreadlen;
1253
1254         if (ret)
1255                 return ret;
1256
1257         if (mtd->ecc_stats.failed - stats.failed)
1258                 return -EBADMSG;
1259
1260         return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1261 }
1262
1263 /**
1264  * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1265  * @mtd:        MTD device structure
1266  * @from:       offset to read from
1267  * @len:        number of bytes to read
1268  * @retlen:     pointer to variable to store the number of read bytes
1269  * @buf:        the databuffer to put data
1270  *
1271  * Get hold of the chip and call nand_do_read
1272  */
1273 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1274                      size_t *retlen, uint8_t *buf)
1275 {
1276         struct nand_chip *chip = mtd->priv;
1277         int ret;
1278
1279         /* Do not allow reads past end of device */
1280         if ((from + len) > mtd->size)
1281                 return -EINVAL;
1282         if (!len)
1283                 return 0;
1284
1285         nand_get_device(chip, mtd, FL_READING);
1286
1287         chip->ops.len = len;
1288         chip->ops.datbuf = buf;
1289         chip->ops.oobbuf = NULL;
1290
1291         ret = nand_do_read_ops(mtd, from, &chip->ops);
1292
1293         *retlen = chip->ops.retlen;
1294
1295         nand_release_device(mtd);
1296
1297         return ret;
1298 }
1299
1300 /**
1301  * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1302  * @mtd:        mtd info structure
1303  * @chip:       nand chip info structure
1304  * @page:       page number to read
1305  * @sndcmd:     flag whether to issue read command or not
1306  */
1307 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1308                              int page, int sndcmd)
1309 {
1310         if (sndcmd) {
1311                 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1312                 sndcmd = 0;
1313         }
1314         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1315         return sndcmd;
1316 }
1317
1318 /**
1319  * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1320  *                          with syndromes
1321  * @mtd:        mtd info structure
1322  * @chip:       nand chip info structure
1323  * @page:       page number to read
1324  * @sndcmd:     flag whether to issue read command or not
1325  */
1326 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1327                                   int page, int sndcmd)
1328 {
1329         uint8_t *buf = chip->oob_poi;
1330         int length = mtd->oobsize;
1331         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1332         int eccsize = chip->ecc.size;
1333         uint8_t *bufpoi = buf;
1334         int i, toread, sndrnd = 0, pos;
1335
1336         chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1337         for (i = 0; i < chip->ecc.steps; i++) {
1338                 if (sndrnd) {
1339                         pos = eccsize + i * (eccsize + chunk);
1340                         if (mtd->writesize > 512)
1341                                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1342                         else
1343                                 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1344                 } else
1345                         sndrnd = 1;
1346                 toread = min_t(int, length, chunk);
1347                 chip->read_buf(mtd, bufpoi, toread);
1348                 bufpoi += toread;
1349                 length -= toread;
1350         }
1351         if (length > 0)
1352                 chip->read_buf(mtd, bufpoi, length);
1353
1354         return 1;
1355 }
1356
1357 /**
1358  * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1359  * @mtd:        mtd info structure
1360  * @chip:       nand chip info structure
1361  * @page:       page number to write
1362  */
1363 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1364                               int page)
1365 {
1366         int status = 0;
1367         const uint8_t *buf = chip->oob_poi;
1368         int length = mtd->oobsize;
1369
1370         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1371         chip->write_buf(mtd, buf, length);
1372         /* Send command to program the OOB data */
1373         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1374
1375         status = chip->waitfunc(mtd, chip);
1376
1377         return status & NAND_STATUS_FAIL ? -EIO : 0;
1378 }
1379
1380 /**
1381  * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1382  *                           with syndrome - only for large page flash !
1383  * @mtd:        mtd info structure
1384  * @chip:       nand chip info structure
1385  * @page:       page number to write
1386  */
1387 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1388                                    struct nand_chip *chip, int page)
1389 {
1390         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1391         int eccsize = chip->ecc.size, length = mtd->oobsize;
1392         int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1393         const uint8_t *bufpoi = chip->oob_poi;
1394
1395         /*
1396          * data-ecc-data-ecc ... ecc-oob
1397          * or
1398          * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1399          */
1400         if (!chip->ecc.prepad && !chip->ecc.postpad) {
1401                 pos = steps * (eccsize + chunk);
1402                 steps = 0;
1403         } else
1404                 pos = eccsize;
1405
1406         chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1407         for (i = 0; i < steps; i++) {
1408                 if (sndcmd) {
1409                         if (mtd->writesize <= 512) {
1410                                 uint32_t fill = 0xFFFFFFFF;
1411
1412                                 len = eccsize;
1413                                 while (len > 0) {
1414                                         int num = min_t(int, len, 4);
1415                                         chip->write_buf(mtd, (uint8_t *)&fill,
1416                                                         num);
1417                                         len -= num;
1418                                 }
1419                         } else {
1420                                 pos = eccsize + i * (eccsize + chunk);
1421                                 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1422                         }
1423                 } else
1424                         sndcmd = 1;
1425                 len = min_t(int, length, chunk);
1426                 chip->write_buf(mtd, bufpoi, len);
1427                 bufpoi += len;
1428                 length -= len;
1429         }
1430         if (length > 0)
1431                 chip->write_buf(mtd, bufpoi, length);
1432
1433         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1434         status = chip->waitfunc(mtd, chip);
1435
1436         return status & NAND_STATUS_FAIL ? -EIO : 0;
1437 }
1438
1439 /**
1440  * nand_do_read_oob - [Intern] NAND read out-of-band
1441  * @mtd:        MTD device structure
1442  * @from:       offset to read from
1443  * @ops:        oob operations description structure
1444  *
1445  * NAND read out-of-band data from the spare area
1446  */
1447 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1448                             struct mtd_oob_ops *ops)
1449 {
1450         int page, realpage, chipnr, sndcmd = 1;
1451         struct nand_chip *chip = mtd->priv;
1452         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1453         int readlen = ops->ooblen;
1454         int len;
1455         uint8_t *buf = ops->oobbuf;
1456
1457         MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n",
1458                   (unsigned long long)from, readlen);
1459
1460         if (ops->mode == MTD_OOB_AUTO)
1461                 len = chip->ecc.layout->oobavail;
1462         else
1463                 len = mtd->oobsize;
1464
1465         if (unlikely(ops->ooboffs >= len)) {
1466                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1467                           "Attempt to start read outside oob\n");
1468                 return -EINVAL;
1469         }
1470
1471         /* Do not allow reads past end of device */
1472         if (unlikely(from >= mtd->size ||
1473                      ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1474                                         (from >> chip->page_shift)) * len)) {
1475                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1476                           "Attempt read beyond end of device\n");
1477                 return -EINVAL;
1478         }
1479
1480         chipnr = (int)(from >> chip->chip_shift);
1481         chip->select_chip(mtd, chipnr);
1482
1483         /* Shift to get page */
1484         realpage = (int)(from >> chip->page_shift);
1485         page = realpage & chip->pagemask;
1486
1487         while(1) {
1488                 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1489
1490                 len = min(len, readlen);
1491                 buf = nand_transfer_oob(chip, buf, ops, len);
1492
1493                 if (!(chip->options & NAND_NO_READRDY)) {
1494                         /*
1495                          * Apply delay or wait for ready/busy pin. Do this
1496                          * before the AUTOINCR check, so no problems arise if a
1497                          * chip which does auto increment is marked as
1498                          * NOAUTOINCR by the board driver.
1499                          */
1500                         if (!chip->dev_ready)
1501                                 udelay(chip->chip_delay);
1502                         else
1503                                 nand_wait_ready(mtd);
1504                 }
1505
1506                 readlen -= len;
1507                 if (!readlen)
1508                         break;
1509
1510                 /* Increment page address */
1511                 realpage++;
1512
1513                 page = realpage & chip->pagemask;
1514                 /* Check, if we cross a chip boundary */
1515                 if (!page) {
1516                         chipnr++;
1517                         chip->select_chip(mtd, -1);
1518                         chip->select_chip(mtd, chipnr);
1519                 }
1520
1521                 /* Check, if the chip supports auto page increment
1522                  * or if we have hit a block boundary.
1523                  */
1524                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1525                         sndcmd = 1;
1526         }
1527
1528         ops->oobretlen = ops->ooblen;
1529         return 0;
1530 }
1531
1532 /**
1533  * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1534  * @mtd:        MTD device structure
1535  * @from:       offset to read from
1536  * @ops:        oob operation description structure
1537  *
1538  * NAND read data and/or out-of-band data
1539  */
1540 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1541                          struct mtd_oob_ops *ops)
1542 {
1543         struct nand_chip *chip = mtd->priv;
1544         int ret = -ENOTSUPP;
1545
1546         ops->retlen = 0;
1547
1548         /* Do not allow reads past end of device */
1549         if (ops->datbuf && (from + ops->len) > mtd->size) {
1550                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1551                           "Attempt read beyond end of device\n");
1552                 return -EINVAL;
1553         }
1554
1555         nand_get_device(chip, mtd, FL_READING);
1556
1557         switch(ops->mode) {
1558         case MTD_OOB_PLACE:
1559         case MTD_OOB_AUTO:
1560         case MTD_OOB_RAW:
1561                 break;
1562
1563         default:
1564                 goto out;
1565         }
1566
1567         if (!ops->datbuf)
1568                 ret = nand_do_read_oob(mtd, from, ops);
1569         else
1570                 ret = nand_do_read_ops(mtd, from, ops);
1571
1572  out:
1573         nand_release_device(mtd);
1574         return ret;
1575 }
1576
1577
1578 /**
1579  * nand_write_page_raw - [Intern] raw page write function
1580  * @mtd:        mtd info structure
1581  * @chip:       nand chip info structure
1582  * @buf:        data buffer
1583  *
1584  * Not for syndrome calculating ecc controllers, which use a special oob layout
1585  */
1586 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1587                                 const uint8_t *buf)
1588 {
1589         chip->write_buf(mtd, buf, mtd->writesize);
1590         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1591 }
1592
1593 /**
1594  * nand_write_page_raw_syndrome - [Intern] raw page write function
1595  * @mtd:        mtd info structure
1596  * @chip:       nand chip info structure
1597  * @buf:        data buffer
1598  *
1599  * We need a special oob layout and handling even when ECC isn't checked.
1600  */
1601 static void nand_write_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1602                                 const uint8_t *buf)
1603 {
1604         int eccsize = chip->ecc.size;
1605         int eccbytes = chip->ecc.bytes;
1606         uint8_t *oob = chip->oob_poi;
1607         int steps, size;
1608
1609         for (steps = chip->ecc.steps; steps > 0; steps--) {
1610                 chip->write_buf(mtd, buf, eccsize);
1611                 buf += eccsize;
1612
1613                 if (chip->ecc.prepad) {
1614                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1615                         oob += chip->ecc.prepad;
1616                 }
1617
1618                 chip->read_buf(mtd, oob, eccbytes);
1619                 oob += eccbytes;
1620
1621                 if (chip->ecc.postpad) {
1622                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1623                         oob += chip->ecc.postpad;
1624                 }
1625         }
1626
1627         size = mtd->oobsize - (oob - chip->oob_poi);
1628         if (size)
1629                 chip->write_buf(mtd, oob, size);
1630 }
1631 /**
1632  * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1633  * @mtd:        mtd info structure
1634  * @chip:       nand chip info structure
1635  * @buf:        data buffer
1636  */
1637 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1638                                   const uint8_t *buf)
1639 {
1640         int i, eccsize = chip->ecc.size;
1641         int eccbytes = chip->ecc.bytes;
1642         int eccsteps = chip->ecc.steps;
1643         uint8_t *ecc_calc = chip->buffers->ecccalc;
1644         const uint8_t *p = buf;
1645         uint32_t *eccpos = chip->ecc.layout->eccpos;
1646
1647         /* Software ecc calculation */
1648         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1649                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1650
1651         for (i = 0; i < chip->ecc.total; i++)
1652                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1653
1654         chip->ecc.write_page_raw(mtd, chip, buf);
1655 }
1656
1657 /**
1658  * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1659  * @mtd:        mtd info structure
1660  * @chip:       nand chip info structure
1661  * @buf:        data buffer
1662  */
1663 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1664                                   const uint8_t *buf)
1665 {
1666         int i, eccsize = chip->ecc.size;
1667         int eccbytes = chip->ecc.bytes;
1668         int eccsteps = chip->ecc.steps;
1669         uint8_t *ecc_calc = chip->buffers->ecccalc;
1670         const uint8_t *p = buf;
1671         uint32_t *eccpos = chip->ecc.layout->eccpos;
1672
1673         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1674                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1675                 chip->write_buf(mtd, p, eccsize);
1676                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1677         }
1678
1679         for (i = 0; i < chip->ecc.total; i++)
1680                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1681
1682         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1683 }
1684
1685 /**
1686  * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1687  * @mtd:        mtd info structure
1688  * @chip:       nand chip info structure
1689  * @buf:        data buffer
1690  *
1691  * The hw generator calculates the error syndrome automatically. Therefor
1692  * we need a special oob layout and handling.
1693  */
1694 static void nand_write_page_syndrome(struct mtd_info *mtd,
1695                                     struct nand_chip *chip, const uint8_t *buf)
1696 {
1697         int i, eccsize = chip->ecc.size;
1698         int eccbytes = chip->ecc.bytes;
1699         int eccsteps = chip->ecc.steps;
1700         const uint8_t *p = buf;
1701         uint8_t *oob = chip->oob_poi;
1702
1703         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1704
1705                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1706                 chip->write_buf(mtd, p, eccsize);
1707
1708                 if (chip->ecc.prepad) {
1709                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1710                         oob += chip->ecc.prepad;
1711                 }
1712
1713                 chip->ecc.calculate(mtd, p, oob);
1714                 chip->write_buf(mtd, oob, eccbytes);
1715                 oob += eccbytes;
1716
1717                 if (chip->ecc.postpad) {
1718                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1719                         oob += chip->ecc.postpad;
1720                 }
1721         }
1722
1723         /* Calculate remaining oob bytes */
1724         i = mtd->oobsize - (oob - chip->oob_poi);
1725         if (i)
1726                 chip->write_buf(mtd, oob, i);
1727 }
1728
1729 /**
1730  * nand_write_page - [REPLACEABLE] write one page
1731  * @mtd:        MTD device structure
1732  * @chip:       NAND chip descriptor
1733  * @buf:        the data to write
1734  * @page:       page number to write
1735  * @cached:     cached programming
1736  * @raw:        use _raw version of write_page
1737  */
1738 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1739                            const uint8_t *buf, int page, int cached, int raw)
1740 {
1741         int status;
1742
1743         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1744
1745         if (unlikely(raw))
1746                 chip->ecc.write_page_raw(mtd, chip, buf);
1747         else
1748                 chip->ecc.write_page(mtd, chip, buf);
1749
1750         /*
1751          * Cached progamming disabled for now, Not sure if its worth the
1752          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1753          */
1754         cached = 0;
1755
1756         if (!cached || !(chip->options & NAND_CACHEPRG)) {
1757
1758                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1759                 status = chip->waitfunc(mtd, chip);
1760                 /*
1761                  * See if operation failed and additional status checks are
1762                  * available
1763                  */
1764                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1765                         status = chip->errstat(mtd, chip, FL_WRITING, status,
1766                                                page);
1767
1768                 if (status & NAND_STATUS_FAIL)
1769                         return -EIO;
1770         } else {
1771                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1772                 status = chip->waitfunc(mtd, chip);
1773         }
1774
1775 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1776         /* Send command to read back the data */
1777         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1778
1779         if (chip->verify_buf(mtd, buf, mtd->writesize))
1780                 return -EIO;
1781 #endif
1782         return 0;
1783 }
1784
1785 /**
1786  * nand_fill_oob - [Internal] Transfer client buffer to oob
1787  * @chip:       nand chip structure
1788  * @oob:        oob data buffer
1789  * @ops:        oob ops structure
1790  */
1791 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
1792                                   struct mtd_oob_ops *ops)
1793 {
1794         size_t len = ops->ooblen;
1795
1796         switch(ops->mode) {
1797
1798         case MTD_OOB_PLACE:
1799         case MTD_OOB_RAW:
1800                 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1801                 return oob + len;
1802
1803         case MTD_OOB_AUTO: {
1804                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1805                 uint32_t boffs = 0, woffs = ops->ooboffs;
1806                 size_t bytes = 0;
1807
1808                 for(; free->length && len; free++, len -= bytes) {
1809                         /* Write request not from offset 0 ? */
1810                         if (unlikely(woffs)) {
1811                                 if (woffs >= free->length) {
1812                                         woffs -= free->length;
1813                                         continue;
1814                                 }
1815                                 boffs = free->offset + woffs;
1816                                 bytes = min_t(size_t, len,
1817                                               (free->length - woffs));
1818                                 woffs = 0;
1819                         } else {
1820                                 bytes = min_t(size_t, len, free->length);
1821                                 boffs = free->offset;
1822                         }
1823                         memcpy(chip->oob_poi + boffs, oob, bytes);
1824                         oob += bytes;
1825                 }
1826                 return oob;
1827         }
1828         default:
1829                 BUG();
1830         }
1831         return NULL;
1832 }
1833
1834 #define NOTALIGNED(x)   (x & (chip->subpagesize - 1)) != 0
1835
1836 /**
1837  * nand_do_write_ops - [Internal] NAND write with ECC
1838  * @mtd:        MTD device structure
1839  * @to:         offset to write to
1840  * @ops:        oob operations description structure
1841  *
1842  * NAND write with ECC
1843  */
1844 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1845                              struct mtd_oob_ops *ops)
1846 {
1847         int chipnr, realpage, page, blockmask, column;
1848         struct nand_chip *chip = mtd->priv;
1849         uint32_t writelen = ops->len;
1850         uint8_t *oob = ops->oobbuf;
1851         uint8_t *buf = ops->datbuf;
1852         int ret, subpage;
1853
1854         ops->retlen = 0;
1855         if (!writelen)
1856                 return 0;
1857
1858         column = to & (mtd->writesize - 1);
1859         subpage = column || (writelen & (mtd->writesize - 1));
1860
1861         if (subpage && oob)
1862                 return -EINVAL;
1863
1864         chipnr = (int)(to >> chip->chip_shift);
1865         chip->select_chip(mtd, chipnr);
1866
1867         /* Check, if it is write protected */
1868         if (nand_check_wp(mtd)) {
1869                 printk (KERN_NOTICE "nand_do_write_ops: Device is write protected\n");
1870                 return -EIO;
1871         }
1872
1873         realpage = (int)(to >> chip->page_shift);
1874         page = realpage & chip->pagemask;
1875         blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1876
1877         /* Invalidate the page cache, when we write to the cached page */
1878         if (to <= (chip->pagebuf << chip->page_shift) &&
1879             (chip->pagebuf << chip->page_shift) < (to + ops->len))
1880                 chip->pagebuf = -1;
1881
1882         /* If we're not given explicit OOB data, let it be 0xFF */
1883         if (likely(!oob))
1884                 memset(chip->oob_poi, 0xff, mtd->oobsize);
1885
1886         while(1) {
1887                 int bytes = mtd->writesize;
1888                 int cached = writelen > bytes && page != blockmask;
1889                 uint8_t *wbuf = buf;
1890
1891                 /* Partial page write ? */
1892                 if (unlikely(column || writelen < (mtd->writesize - 1))) {
1893                         cached = 0;
1894                         bytes = min_t(int, bytes - column, (int) writelen);
1895                         chip->pagebuf = -1;
1896                         memset(chip->buffers->databuf, 0xff, mtd->writesize);
1897                         memcpy(&chip->buffers->databuf[column], buf, bytes);
1898                         wbuf = chip->buffers->databuf;
1899                 }
1900
1901                 if (unlikely(oob))
1902                         oob = nand_fill_oob(chip, oob, ops);
1903
1904                 ret = chip->write_page(mtd, chip, wbuf, page, cached,
1905                                        (ops->mode == MTD_OOB_RAW));
1906                 if (ret)
1907                         break;
1908
1909                 writelen -= bytes;
1910                 if (!writelen)
1911                         break;
1912
1913                 column = 0;
1914                 buf += bytes;
1915                 realpage++;
1916
1917                 page = realpage & chip->pagemask;
1918                 /* Check, if we cross a chip boundary */
1919                 if (!page) {
1920                         chipnr++;
1921                         chip->select_chip(mtd, -1);
1922                         chip->select_chip(mtd, chipnr);
1923                 }
1924         }
1925
1926         ops->retlen = ops->len - writelen;
1927         if (unlikely(oob))
1928                 ops->oobretlen = ops->ooblen;
1929         return ret;
1930 }
1931
1932 /**
1933  * nand_write - [MTD Interface] NAND write with ECC
1934  * @mtd:        MTD device structure
1935  * @to:         offset to write to
1936  * @len:        number of bytes to write
1937  * @retlen:     pointer to variable to store the number of written bytes
1938  * @buf:        the data to write
1939  *
1940  * NAND write with ECC
1941  */
1942 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
1943                           size_t *retlen, const uint8_t *buf)
1944 {
1945         struct nand_chip *chip = mtd->priv;
1946         int ret;
1947
1948         /* Do not allow reads past end of device */
1949         if ((to + len) > mtd->size)
1950                 return -EINVAL;
1951         if (!len)
1952                 return 0;
1953
1954         nand_get_device(chip, mtd, FL_WRITING);
1955
1956         chip->ops.len = len;
1957         chip->ops.datbuf = (uint8_t *)buf;
1958         chip->ops.oobbuf = NULL;
1959
1960         ret = nand_do_write_ops(mtd, to, &chip->ops);
1961
1962         *retlen = chip->ops.retlen;
1963
1964         nand_release_device(mtd);
1965
1966         return ret;
1967 }
1968
1969 /**
1970  * nand_do_write_oob - [MTD Interface] NAND write out-of-band
1971  * @mtd:        MTD device structure
1972  * @to:         offset to write to
1973  * @ops:        oob operation description structure
1974  *
1975  * NAND write out-of-band
1976  */
1977 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
1978                              struct mtd_oob_ops *ops)
1979 {
1980         int chipnr, page, status, len;
1981         struct nand_chip *chip = mtd->priv;
1982
1983         MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n",
1984                   (unsigned int)to, (int)ops->ooblen);
1985
1986         if (ops->mode == MTD_OOB_AUTO)
1987                 len = chip->ecc.layout->oobavail;
1988         else
1989                 len = mtd->oobsize;
1990
1991         /* Do not allow write past end of page */
1992         if ((ops->ooboffs + ops->ooblen) > len) {
1993                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: "
1994                           "Attempt to write past end of page\n");
1995                 return -EINVAL;
1996         }
1997
1998         if (unlikely(ops->ooboffs >= len)) {
1999                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2000                           "Attempt to start write outside oob\n");
2001                 return -EINVAL;
2002         }
2003
2004         /* Do not allow reads past end of device */
2005         if (unlikely(to >= mtd->size ||
2006                      ops->ooboffs + ops->ooblen >
2007                         ((mtd->size >> chip->page_shift) -
2008                          (to >> chip->page_shift)) * len)) {
2009                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2010                           "Attempt write beyond end of device\n");
2011                 return -EINVAL;
2012         }
2013
2014         chipnr = (int)(to >> chip->chip_shift);
2015         chip->select_chip(mtd, chipnr);
2016
2017         /* Shift to get page */
2018         page = (int)(to >> chip->page_shift);
2019
2020         /*
2021          * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2022          * of my DiskOnChip 2000 test units) will clear the whole data page too
2023          * if we don't do this. I have no clue why, but I seem to have 'fixed'
2024          * it in the doc2000 driver in August 1999.  dwmw2.
2025          */
2026         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2027
2028         /* Check, if it is write protected */
2029         if (nand_check_wp(mtd))
2030                 return -EROFS;
2031
2032         /* Invalidate the page cache, if we write to the cached page */
2033         if (page == chip->pagebuf)
2034                 chip->pagebuf = -1;
2035
2036         memset(chip->oob_poi, 0xff, mtd->oobsize);
2037         nand_fill_oob(chip, ops->oobbuf, ops);
2038         status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2039         memset(chip->oob_poi, 0xff, mtd->oobsize);
2040
2041         if (status)
2042                 return status;
2043
2044         ops->oobretlen = ops->ooblen;
2045
2046         return 0;
2047 }
2048
2049 /**
2050  * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2051  * @mtd:        MTD device structure
2052  * @to:         offset to write to
2053  * @ops:        oob operation description structure
2054  */
2055 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2056                           struct mtd_oob_ops *ops)
2057 {
2058         struct nand_chip *chip = mtd->priv;
2059         int ret = -ENOTSUPP;
2060
2061         ops->retlen = 0;
2062
2063         /* Do not allow writes past end of device */
2064         if (ops->datbuf && (to + ops->len) > mtd->size) {
2065                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2066                           "Attempt read beyond end of device\n");
2067                 return -EINVAL;
2068         }
2069
2070         nand_get_device(chip, mtd, FL_WRITING);
2071
2072         switch(ops->mode) {
2073         case MTD_OOB_PLACE:
2074         case MTD_OOB_AUTO:
2075         case MTD_OOB_RAW:
2076                 break;
2077
2078         default:
2079                 goto out;
2080         }
2081
2082         if (!ops->datbuf)
2083                 ret = nand_do_write_oob(mtd, to, ops);
2084         else
2085                 ret = nand_do_write_ops(mtd, to, ops);
2086
2087  out:
2088         nand_release_device(mtd);
2089         return ret;
2090 }
2091
2092 /**
2093  * single_erease_cmd - [GENERIC] NAND standard block erase command function
2094  * @mtd:        MTD device structure
2095  * @page:       the page address of the block which will be erased
2096  *
2097  * Standard erase command for NAND chips
2098  */
2099 static void single_erase_cmd(struct mtd_info *mtd, int page)
2100 {
2101         struct nand_chip *chip = mtd->priv;
2102         /* Send commands to erase a block */
2103         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2104         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2105 }
2106
2107 /**
2108  * multi_erease_cmd - [GENERIC] AND specific block erase command function
2109  * @mtd:        MTD device structure
2110  * @page:       the page address of the block which will be erased
2111  *
2112  * AND multi block erase command function
2113  * Erase 4 consecutive blocks
2114  */
2115 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2116 {
2117         struct nand_chip *chip = mtd->priv;
2118         /* Send commands to erase a block */
2119         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2120         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2121         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2122         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2123         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2124 }
2125
2126 /**
2127  * nand_erase - [MTD Interface] erase block(s)
2128  * @mtd:        MTD device structure
2129  * @instr:      erase instruction
2130  *
2131  * Erase one ore more blocks
2132  */
2133 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2134 {
2135         return nand_erase_nand(mtd, instr, 0);
2136 }
2137
2138 #define BBT_PAGE_MASK   0xffffff3f
2139 /**
2140  * nand_erase_nand - [Internal] erase block(s)
2141  * @mtd:        MTD device structure
2142  * @instr:      erase instruction
2143  * @allowbbt:   allow erasing the bbt area
2144  *
2145  * Erase one ore more blocks
2146  */
2147 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2148                     int allowbbt)
2149 {
2150         int page, status, pages_per_block, ret, chipnr;
2151         struct nand_chip *chip = mtd->priv;
2152         loff_t rewrite_bbt[CONFIG_SYS_NAND_MAX_CHIPS] = {0};
2153         unsigned int bbt_masked_page = 0xffffffff;
2154         loff_t len;
2155
2156         MTDDEBUG(MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%012llx, "
2157                  "len = %llu\n", (unsigned long long) instr->addr,
2158                  (unsigned long long) instr->len);
2159
2160         /* Start address must align on block boundary */
2161         if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
2162                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
2163                 return -EINVAL;
2164         }
2165
2166         /* Length must align on block boundary */
2167         if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
2168                 MTDDEBUG (MTD_DEBUG_LEVEL0,
2169                           "nand_erase: Length not block aligned\n");
2170                 return -EINVAL;
2171         }
2172
2173         /* Do not allow erase past end of device */
2174         if ((instr->len + instr->addr) > mtd->size) {
2175                 MTDDEBUG (MTD_DEBUG_LEVEL0,
2176                           "nand_erase: Erase past end of device\n");
2177                 return -EINVAL;
2178         }
2179
2180         instr->fail_addr = 0xffffffff;
2181
2182         /* Grab the lock and see if the device is available */
2183         nand_get_device(chip, mtd, FL_ERASING);
2184
2185         /* Shift to get first page */
2186         page = (int)(instr->addr >> chip->page_shift);
2187         chipnr = (int)(instr->addr >> chip->chip_shift);
2188
2189         /* Calculate pages in each block */
2190         pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2191
2192         /* Select the NAND device */
2193         chip->select_chip(mtd, chipnr);
2194
2195         /* Check, if it is write protected */
2196         if (nand_check_wp(mtd)) {
2197                 MTDDEBUG (MTD_DEBUG_LEVEL0,
2198                           "nand_erase: Device is write protected!!!\n");
2199                 instr->state = MTD_ERASE_FAILED;
2200                 goto erase_exit;
2201         }
2202
2203         /*
2204          * If BBT requires refresh, set the BBT page mask to see if the BBT
2205          * should be rewritten. Otherwise the mask is set to 0xffffffff which
2206          * can not be matched. This is also done when the bbt is actually
2207          * erased to avoid recusrsive updates
2208          */
2209         if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2210                 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2211
2212         /* Loop through the pages */
2213         len = instr->len;
2214
2215         instr->state = MTD_ERASING;
2216
2217         while (len) {
2218                 /*
2219                  * heck if we have a bad block, we do not erase bad blocks !
2220                  */
2221                 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2222                                         chip->page_shift, 0, allowbbt)) {
2223                         printk(KERN_WARNING "nand_erase: attempt to erase a "
2224                                "bad block at page 0x%08x\n", page);
2225                         instr->state = MTD_ERASE_FAILED;
2226                         goto erase_exit;
2227                 }
2228
2229                 /*
2230                  * Invalidate the page cache, if we erase the block which
2231                  * contains the current cached page
2232                  */
2233                 if (page <= chip->pagebuf && chip->pagebuf <
2234                     (page + pages_per_block))
2235                         chip->pagebuf = -1;
2236
2237                 chip->erase_cmd(mtd, page & chip->pagemask);
2238
2239                 status = chip->waitfunc(mtd, chip);
2240
2241                 /*
2242                  * See if operation failed and additional status checks are
2243                  * available
2244                  */
2245                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2246                         status = chip->errstat(mtd, chip, FL_ERASING,
2247                                                status, page);
2248
2249                 /* See if block erase succeeded */
2250                 if (status & NAND_STATUS_FAIL) {
2251                         MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: "
2252                                   "Failed erase, page 0x%08x\n", page);
2253                         instr->state = MTD_ERASE_FAILED;
2254                         instr->fail_addr = ((loff_t)page << chip->page_shift);
2255                         goto erase_exit;
2256                 }
2257
2258                 /*
2259                  * If BBT requires refresh, set the BBT rewrite flag to the
2260                  * page being erased
2261                  */
2262                 if (bbt_masked_page != 0xffffffff &&
2263                     (page & BBT_PAGE_MASK) == bbt_masked_page)
2264                         rewrite_bbt[chipnr] =
2265                                 ((loff_t)page << chip->page_shift);
2266
2267                 /* Increment page address and decrement length */
2268                 len -= (1 << chip->phys_erase_shift);
2269                 page += pages_per_block;
2270
2271                 /* Check, if we cross a chip boundary */
2272                 if (len && !(page & chip->pagemask)) {
2273                         chipnr++;
2274                         chip->select_chip(mtd, -1);
2275                         chip->select_chip(mtd, chipnr);
2276
2277                         /*
2278                          * If BBT requires refresh and BBT-PERCHIP, set the BBT
2279                          * page mask to see if this BBT should be rewritten
2280                          */
2281                         if (bbt_masked_page != 0xffffffff &&
2282                             (chip->bbt_td->options & NAND_BBT_PERCHIP))
2283                                 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2284                                         BBT_PAGE_MASK;
2285                 }
2286         }
2287         instr->state = MTD_ERASE_DONE;
2288
2289  erase_exit:
2290
2291         ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2292
2293         /* Deselect and wake up anyone waiting on the device */
2294         nand_release_device(mtd);
2295
2296         /* Do call back function */
2297         if (!ret)
2298                 mtd_erase_callback(instr);
2299
2300         /*
2301          * If BBT requires refresh and erase was successful, rewrite any
2302          * selected bad block tables
2303          */
2304         if (bbt_masked_page == 0xffffffff || ret)
2305                 return ret;
2306
2307         for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2308                 if (!rewrite_bbt[chipnr])
2309                         continue;
2310                 /* update the BBT for chip */
2311                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
2312                           "(%d:0x%0llx 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
2313                           chip->bbt_td->pages[chipnr]);
2314                 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2315         }
2316
2317         /* Return more or less happy */
2318         return ret;
2319 }
2320
2321 /**
2322  * nand_sync - [MTD Interface] sync
2323  * @mtd:        MTD device structure
2324  *
2325  * Sync is actually a wait for chip ready function
2326  */
2327 static void nand_sync(struct mtd_info *mtd)
2328 {
2329         struct nand_chip *chip = mtd->priv;
2330
2331         MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_sync: called\n");
2332
2333         /* Grab the lock and see if the device is available */
2334         nand_get_device(chip, mtd, FL_SYNCING);
2335         /* Release it and go back */
2336         nand_release_device(mtd);
2337 }
2338
2339 /**
2340  * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2341  * @mtd:        MTD device structure
2342  * @offs:       offset relative to mtd start
2343  */
2344 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2345 {
2346         /* Check for invalid offset */
2347         if (offs > mtd->size)
2348                 return -EINVAL;
2349
2350         return nand_block_checkbad(mtd, offs, 1, 0);
2351 }
2352
2353 /**
2354  * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2355  * @mtd:        MTD device structure
2356  * @ofs:        offset relative to mtd start
2357  */
2358 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2359 {
2360         struct nand_chip *chip = mtd->priv;
2361         int ret;
2362
2363         if ((ret = nand_block_isbad(mtd, ofs))) {
2364                 /* If it was bad already, return success and do nothing. */
2365                 if (ret > 0)
2366                         return 0;
2367                 return ret;
2368         }
2369
2370         return chip->block_markbad(mtd, ofs);
2371 }
2372
2373 /*
2374  * Set default functions
2375  */
2376 static void nand_set_defaults(struct nand_chip *chip, int busw)
2377 {
2378         /* check for proper chip_delay setup, set 20us if not */
2379         if (!chip->chip_delay)
2380                 chip->chip_delay = 20;
2381
2382         /* check, if a user supplied command function given */
2383         if (chip->cmdfunc == NULL)
2384                 chip->cmdfunc = nand_command;
2385
2386         /* check, if a user supplied wait function given */
2387         if (chip->waitfunc == NULL)
2388                 chip->waitfunc = nand_wait;
2389
2390         if (!chip->select_chip)
2391                 chip->select_chip = nand_select_chip;
2392         if (!chip->read_byte)
2393                 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2394         if (!chip->read_word)
2395                 chip->read_word = nand_read_word;
2396         if (!chip->block_bad)
2397                 chip->block_bad = nand_block_bad;
2398         if (!chip->block_markbad)
2399                 chip->block_markbad = nand_default_block_markbad;
2400         if (!chip->write_buf)
2401                 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2402         if (!chip->read_buf)
2403                 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2404         if (!chip->verify_buf)
2405                 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2406         if (!chip->scan_bbt)
2407                 chip->scan_bbt = nand_default_bbt;
2408         if (!chip->controller)
2409                 chip->controller = &chip->hwcontrol;
2410 }
2411
2412 /*
2413  * Get the flash and manufacturer id and lookup if the type is supported
2414  */
2415 static const struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2416                                                   struct nand_chip *chip,
2417                                                   int busw, int *maf_id)
2418 {
2419         const struct nand_flash_dev *type = NULL;
2420         int i, dev_id, maf_idx;
2421         int tmp_id, tmp_manf;
2422
2423         /* Select the device */
2424         chip->select_chip(mtd, 0);
2425
2426         /*
2427          * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2428          * after power-up
2429          */
2430         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2431
2432         /* Send the command for reading device ID */
2433         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2434
2435         /* Read manufacturer and device IDs */
2436         *maf_id = chip->read_byte(mtd);
2437         dev_id = chip->read_byte(mtd);
2438
2439         /* Try again to make sure, as some systems the bus-hold or other
2440          * interface concerns can cause random data which looks like a
2441          * possibly credible NAND flash to appear. If the two results do
2442          * not match, ignore the device completely.
2443          */
2444
2445         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2446
2447         /* Read manufacturer and device IDs */
2448
2449         tmp_manf = chip->read_byte(mtd);
2450         tmp_id = chip->read_byte(mtd);
2451
2452         if (tmp_manf != *maf_id || tmp_id != dev_id) {
2453                 printk(KERN_INFO "%s: second ID read did not match "
2454                        "%02x,%02x against %02x,%02x\n", __func__,
2455                        *maf_id, dev_id, tmp_manf, tmp_id);
2456                 return ERR_PTR(-ENODEV);
2457         }
2458
2459         /* Lookup the flash id */
2460         for (i = 0; nand_flash_ids[i].name != NULL; i++) {
2461                 if (dev_id == nand_flash_ids[i].id) {
2462                         type =  &nand_flash_ids[i];
2463                         break;
2464                 }
2465         }
2466
2467         if (!type) {
2468                 /* supress warning if there is no nand */
2469                 if (*maf_id != 0x00 && *maf_id != 0xff &&
2470                     dev_id  != 0x00 && dev_id  != 0xff)
2471                         printk(KERN_INFO "%s: unknown NAND device: "
2472                                 "Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
2473                                 __func__, *maf_id, dev_id);
2474                 return ERR_PTR(-ENODEV);
2475         }
2476
2477         if (!mtd->name)
2478                 mtd->name = type->name;
2479
2480         chip->chipsize = (uint64_t)type->chipsize << 20;
2481
2482         /* Newer devices have all the information in additional id bytes */
2483         if (!type->pagesize) {
2484                 int extid;
2485                 /* The 3rd id byte holds MLC / multichip data */
2486                 chip->cellinfo = chip->read_byte(mtd);
2487                 /* The 4th id byte is the important one */
2488                 extid = chip->read_byte(mtd);
2489                 /* Calc pagesize */
2490                 mtd->writesize = 1024 << (extid & 0x3);
2491                 extid >>= 2;
2492                 /* Calc oobsize */
2493                 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
2494                 extid >>= 2;
2495                 /* Calc blocksize. Blocksize is multiples of 64KiB */
2496                 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2497                 extid >>= 2;
2498                 /* Get buswidth information */
2499                 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2500
2501         } else {
2502                 /*
2503                  * Old devices have chip data hardcoded in the device id table
2504                  */
2505                 mtd->erasesize = type->erasesize;
2506                 mtd->writesize = type->pagesize;
2507                 mtd->oobsize = mtd->writesize / 32;
2508                 busw = type->options & NAND_BUSWIDTH_16;
2509         }
2510
2511         /* Try to identify manufacturer */
2512         for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2513                 if (nand_manuf_ids[maf_idx].id == *maf_id)
2514                         break;
2515         }
2516
2517         /*
2518          * Check, if buswidth is correct. Hardware drivers should set
2519          * chip correct !
2520          */
2521         if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2522                 printk(KERN_INFO "NAND device: Manufacturer ID:"
2523                        " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2524                        dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2525                 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2526                        (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2527                        busw ? 16 : 8);
2528                 return ERR_PTR(-EINVAL);
2529         }
2530
2531         /* Calculate the address shift from the page size */
2532         chip->page_shift = ffs(mtd->writesize) - 1;
2533         /* Convert chipsize to number of pages per chip -1. */
2534         chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2535
2536         chip->bbt_erase_shift = chip->phys_erase_shift =
2537                 ffs(mtd->erasesize) - 1;
2538         if (chip->chipsize & 0xffffffff)
2539                 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
2540         else
2541                 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)) + 31;
2542
2543         /* Set the bad block position */
2544         chip->badblockpos = mtd->writesize > 512 ?
2545                 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2546
2547         /* Get chip options, preserve non chip based options */
2548         chip->options &= ~NAND_CHIPOPTIONS_MSK;
2549         chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
2550
2551         /*
2552          * Set chip as a default. Board drivers can override it, if necessary
2553          */
2554         chip->options |= NAND_NO_AUTOINCR;
2555
2556         /* Check if chip is a not a samsung device. Do not clear the
2557          * options for chips which are not having an extended id.
2558          */
2559         if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2560                 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2561
2562         /* Check for AND chips with 4 page planes */
2563         if (chip->options & NAND_4PAGE_ARRAY)
2564                 chip->erase_cmd = multi_erase_cmd;
2565         else
2566                 chip->erase_cmd = single_erase_cmd;
2567
2568         /* Do not replace user supplied command function ! */
2569         if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2570                 chip->cmdfunc = nand_command_lp;
2571
2572         MTDDEBUG (MTD_DEBUG_LEVEL0, "NAND device: Manufacturer ID:"
2573                   " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2574                   nand_manuf_ids[maf_idx].name, type->name);
2575
2576         return type;
2577 }
2578
2579 /**
2580  * nand_scan_ident - [NAND Interface] Scan for the NAND device
2581  * @mtd:             MTD device structure
2582  * @maxchips:        Number of chips to scan for
2583  *
2584  * This is the first phase of the normal nand_scan() function. It
2585  * reads the flash ID and sets up MTD fields accordingly.
2586  *
2587  * The mtd->owner field must be set to the module of the caller.
2588  */
2589 int nand_scan_ident(struct mtd_info *mtd, int maxchips)
2590 {
2591         int i, busw, nand_maf_id;
2592         struct nand_chip *chip = mtd->priv;
2593         const struct nand_flash_dev *type;
2594
2595         /* Get buswidth to select the correct functions */
2596         busw = chip->options & NAND_BUSWIDTH_16;
2597         /* Set the default functions */
2598         nand_set_defaults(chip, busw);
2599
2600         /* Read the flash type */
2601         type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
2602
2603         if (IS_ERR(type)) {
2604 #ifndef CONFIG_SYS_NAND_QUIET_TEST
2605                 printk(KERN_WARNING "No NAND device found!!!\n");
2606 #endif
2607                 chip->select_chip(mtd, -1);
2608                 return PTR_ERR(type);
2609         }
2610
2611         /* Check for a chip array */
2612         for (i = 1; i < maxchips; i++) {
2613                 chip->select_chip(mtd, i);
2614                 /* See comment in nand_get_flash_type for reset */
2615                 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2616                 /* Send the command for reading device ID */
2617                 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2618                 /* Read manufacturer and device IDs */
2619                 if (nand_maf_id != chip->read_byte(mtd) ||
2620                     type->id != chip->read_byte(mtd))
2621                         break;
2622         }
2623 #ifdef DEBUG
2624         if (i > 1)
2625                 printk(KERN_INFO "%d NAND chips detected\n", i);
2626 #endif
2627
2628         /* Store the number of chips and calc total size for mtd */
2629         chip->numchips = i;
2630         mtd->size = i * chip->chipsize;
2631
2632         return 0;
2633 }
2634
2635
2636 /**
2637  * nand_scan_tail - [NAND Interface] Scan for the NAND device
2638  * @mtd:            MTD device structure
2639  *
2640  * This is the second phase of the normal nand_scan() function. It
2641  * fills out all the uninitialized function pointers with the defaults
2642  * and scans for a bad block table if appropriate.
2643  */
2644 int nand_scan_tail(struct mtd_info *mtd)
2645 {
2646         int i;
2647         struct nand_chip *chip = mtd->priv;
2648
2649         if (!(chip->options & NAND_OWN_BUFFERS))
2650                 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2651         if (!chip->buffers)
2652                 return -ENOMEM;
2653
2654         /* Set the internal oob buffer location, just after the page data */
2655         chip->oob_poi = chip->buffers->databuf + mtd->writesize;
2656
2657         /*
2658          * If no default placement scheme is given, select an appropriate one
2659          */
2660         if (!chip->ecc.layout) {
2661                 switch (mtd->oobsize) {
2662                 case 8:
2663                         chip->ecc.layout = &nand_oob_8;
2664                         break;
2665                 case 16:
2666                         chip->ecc.layout = &nand_oob_16;
2667                         break;
2668                 case 64:
2669                         chip->ecc.layout = &nand_oob_64;
2670                         break;
2671                 case 128:
2672                         chip->ecc.layout = &nand_oob_128;
2673                         break;
2674                 default:
2675                         printk(KERN_WARNING "No oob scheme defined for "
2676                                "oobsize %d\n", mtd->oobsize);
2677                 }
2678         }
2679
2680         if (!chip->write_page)
2681                 chip->write_page = nand_write_page;
2682
2683         /*
2684          * check ECC mode, default to software if 3byte/512byte hardware ECC is
2685          * selected and we have 256 byte pagesize fallback to software ECC
2686          */
2687
2688         switch (chip->ecc.mode) {
2689         case NAND_ECC_HW_OOB_FIRST:
2690                 /* Similar to NAND_ECC_HW, but a separate read_page handle */
2691                 if (!chip->ecc.calculate || !chip->ecc.correct ||
2692                      !chip->ecc.hwctl) {
2693                         printk(KERN_WARNING "No ECC functions supplied, "
2694                                "Hardware ECC not possible\n");
2695                         BUG();
2696                 }
2697                 if (!chip->ecc.read_page)
2698                         chip->ecc.read_page = nand_read_page_hwecc_oob_first;
2699
2700         case NAND_ECC_HW:
2701                 /* Use standard hwecc read page function ? */
2702                 if (!chip->ecc.read_page)
2703                         chip->ecc.read_page = nand_read_page_hwecc;
2704                 if (!chip->ecc.write_page)
2705                         chip->ecc.write_page = nand_write_page_hwecc;
2706                 if (!chip->ecc.read_page_raw)
2707                         chip->ecc.read_page_raw = nand_read_page_raw;
2708                 if (!chip->ecc.write_page_raw)
2709                         chip->ecc.write_page_raw = nand_write_page_raw;
2710                 if (!chip->ecc.read_oob)
2711                         chip->ecc.read_oob = nand_read_oob_std;
2712                 if (!chip->ecc.write_oob)
2713                         chip->ecc.write_oob = nand_write_oob_std;
2714
2715         case NAND_ECC_HW_SYNDROME:
2716                 if ((!chip->ecc.calculate || !chip->ecc.correct ||
2717                      !chip->ecc.hwctl) &&
2718                     (!chip->ecc.read_page ||
2719                      chip->ecc.read_page == nand_read_page_hwecc ||
2720                      !chip->ecc.write_page ||
2721                      chip->ecc.write_page == nand_write_page_hwecc)) {
2722                         printk(KERN_WARNING "No ECC functions supplied, "
2723                                "Hardware ECC not possible\n");
2724                         BUG();
2725                 }
2726                 /* Use standard syndrome read/write page function ? */
2727                 if (!chip->ecc.read_page)
2728                         chip->ecc.read_page = nand_read_page_syndrome;
2729                 if (!chip->ecc.write_page)
2730                         chip->ecc.write_page = nand_write_page_syndrome;
2731                 if (!chip->ecc.read_page_raw)
2732                         chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
2733                 if (!chip->ecc.write_page_raw)
2734                         chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
2735                 if (!chip->ecc.read_oob)
2736                         chip->ecc.read_oob = nand_read_oob_syndrome;
2737                 if (!chip->ecc.write_oob)
2738                         chip->ecc.write_oob = nand_write_oob_syndrome;
2739
2740                 if (mtd->writesize >= chip->ecc.size)
2741                         break;
2742                 printk(KERN_WARNING "%d byte HW ECC not possible on "
2743                        "%d byte page size, fallback to SW ECC\n",
2744                        chip->ecc.size, mtd->writesize);
2745                 chip->ecc.mode = NAND_ECC_SOFT;
2746
2747         case NAND_ECC_SOFT:
2748                 chip->ecc.calculate = nand_calculate_ecc;
2749                 chip->ecc.correct = nand_correct_data;
2750                 chip->ecc.read_page = nand_read_page_swecc;
2751                 chip->ecc.read_subpage = nand_read_subpage;
2752                 chip->ecc.write_page = nand_write_page_swecc;
2753                 chip->ecc.read_page_raw = nand_read_page_raw;
2754                 chip->ecc.write_page_raw = nand_write_page_raw;
2755                 chip->ecc.read_oob = nand_read_oob_std;
2756                 chip->ecc.write_oob = nand_write_oob_std;
2757                 chip->ecc.size = 256;
2758                 chip->ecc.bytes = 3;
2759                 break;
2760
2761         case NAND_ECC_NONE:
2762                 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2763                        "This is not recommended !!\n");
2764                 chip->ecc.read_page = nand_read_page_raw;
2765                 chip->ecc.write_page = nand_write_page_raw;
2766                 chip->ecc.read_oob = nand_read_oob_std;
2767                 chip->ecc.read_page_raw = nand_read_page_raw;
2768                 chip->ecc.write_page_raw = nand_write_page_raw;
2769                 chip->ecc.write_oob = nand_write_oob_std;
2770                 chip->ecc.size = mtd->writesize;
2771                 chip->ecc.bytes = 0;
2772                 break;
2773
2774         default:
2775                 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
2776                        chip->ecc.mode);
2777                 BUG();
2778         }
2779
2780         /*
2781          * The number of bytes available for a client to place data into
2782          * the out of band area
2783          */
2784         chip->ecc.layout->oobavail = 0;
2785         for (i = 0; chip->ecc.layout->oobfree[i].length
2786                         && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
2787                 chip->ecc.layout->oobavail +=
2788                         chip->ecc.layout->oobfree[i].length;
2789         mtd->oobavail = chip->ecc.layout->oobavail;
2790
2791         /*
2792          * Set the number of read / write steps for one page depending on ECC
2793          * mode
2794          */
2795         chip->ecc.steps = mtd->writesize / chip->ecc.size;
2796         if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
2797                 printk(KERN_WARNING "Invalid ecc parameters\n");
2798                 BUG();
2799         }
2800         chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
2801
2802         /*
2803          * Allow subpage writes up to ecc.steps. Not possible for MLC
2804          * FLASH.
2805          */
2806         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2807             !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
2808                 switch(chip->ecc.steps) {
2809                 case 2:
2810                         mtd->subpage_sft = 1;
2811                         break;
2812                 case 4:
2813                 case 8:
2814                 case 16:
2815                         mtd->subpage_sft = 2;
2816                         break;
2817                 }
2818         }
2819         chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
2820
2821         /* Initialize state */
2822         chip->state = FL_READY;
2823
2824         /* De-select the device */
2825         chip->select_chip(mtd, -1);
2826
2827         /* Invalidate the pagebuffer reference */
2828         chip->pagebuf = -1;
2829
2830         /* Fill in remaining MTD driver data */
2831         mtd->type = MTD_NANDFLASH;
2832         mtd->flags = MTD_CAP_NANDFLASH;
2833         mtd->erase = nand_erase;
2834         mtd->point = NULL;
2835         mtd->unpoint = NULL;
2836         mtd->read = nand_read;
2837         mtd->write = nand_write;
2838         mtd->read_oob = nand_read_oob;
2839         mtd->write_oob = nand_write_oob;
2840         mtd->sync = nand_sync;
2841         mtd->lock = NULL;
2842         mtd->unlock = NULL;
2843         mtd->block_isbad = nand_block_isbad;
2844         mtd->block_markbad = nand_block_markbad;
2845
2846         /* propagate ecc.layout to mtd_info */
2847         mtd->ecclayout = chip->ecc.layout;
2848
2849         /* Check, if we should skip the bad block table scan */
2850         if (chip->options & NAND_SKIP_BBTSCAN)
2851                 chip->options |= NAND_BBT_SCANNED;
2852
2853         return 0;
2854 }
2855
2856 /**
2857  * nand_scan - [NAND Interface] Scan for the NAND device
2858  * @mtd:        MTD device structure
2859  * @maxchips:   Number of chips to scan for
2860  *
2861  * This fills out all the uninitialized function pointers
2862  * with the defaults.
2863  * The flash ID is read and the mtd/chip structures are
2864  * filled with the appropriate values.
2865  * The mtd->owner field must be set to the module of the caller
2866  *
2867  */
2868 int nand_scan(struct mtd_info *mtd, int maxchips)
2869 {
2870         int ret;
2871
2872         ret = nand_scan_ident(mtd, maxchips);
2873         if (!ret)
2874                 ret = nand_scan_tail(mtd);
2875         return ret;
2876 }
2877
2878 /**
2879  * nand_release - [NAND Interface] Free resources held by the NAND device
2880  * @mtd:        MTD device structure
2881 */
2882 void nand_release(struct mtd_info *mtd)
2883 {
2884         struct nand_chip *chip = mtd->priv;
2885
2886 #ifdef CONFIG_MTD_PARTITIONS
2887         /* Deregister partitions */
2888         del_mtd_partitions(mtd);
2889 #endif
2890
2891         /* Free bad block table memory */
2892         kfree(chip->bbt);
2893         if (!(chip->options & NAND_OWN_BUFFERS))
2894                 kfree(chip->buffers);
2895 }