drivers/mtd/nand/nand_base.c

   1 /*
   2  *  drivers/mtd/nand.c
   3  *
   4  *  Overview:
   5  *   This is the generic MTD driver for NAND flash devices. It should be
   6  *   capable of working with almost all NAND chips currently available.
   7  *   Basic support for AG-AND chips is provided.
   8  *
   9  *      Additional technical information is available on
  10  *      http://www.linux-mtd.infradead.org/doc/nand.html
  11  *
  12  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  13  *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
  14  *
  15  *  Credits:
  16  *      David Woodhouse for adding multichip support
  17  *
  18  *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  19  *      rework for 2K page size chips
  20  *
  21  *  TODO:
  22  *      Enable cached programming for 2k page size chips
  23  *      Check, if mtd->ecctype should be set to MTD_ECC_HW
  24  *      if we have HW ecc support.
  25  *      The AG-AND chips have nice features for speed improvement,
  26  *      which are not supported yet. Read / program 4 pages in one go.
  27  *      BBT table is not serialized, has to be fixed
  28  *
  29  * This program is free software; you can redistribute it and/or modify
  30  * it under the terms of the GNU General Public License version 2 as
  31  * published by the Free Software Foundation.
  32  *
  33  */
  34
  35 /* XXX U-BOOT XXX */
  36 #if 0
  37 #include <linux/module.h>
  38 #include <linux/delay.h>
  39 #include <linux/errno.h>
  40 #include <linux/err.h>
  41 #include <linux/sched.h>
  42 #include <linux/slab.h>
  43 #include <linux/types.h>
  44 #include <linux/mtd/mtd.h>
  45 #include <linux/mtd/nand.h>
  46 #include <linux/mtd/nand_ecc.h>
  47 #include <linux/mtd/compatmac.h>
  48 #include <linux/interrupt.h>
  49 #include <linux/bitops.h>
  50 #include <linux/leds.h>
  51 #include <asm/io.h>
  52
  53 #ifdef CONFIG_MTD_PARTITIONS
  54 #include <linux/mtd/partitions.h>
  55 #endif
  56
  57 #endif
  58
  59 #include <common.h>
  60
  61 #define ENOTSUPP        524     /* Operation is not supported */
  62
  63 #include <malloc.h>
  64 #include <watchdog.h>
  65 #include <linux/err.h>
  66 #include <linux/mtd/compat.h>
  67 #include <linux/mtd/mtd.h>
  68 #include <linux/mtd/nand.h>
  69 #include <linux/mtd/nand_ecc.h>
  70
  71 #ifdef CONFIG_MTD_PARTITIONS
  72 #include <linux/mtd/partitions.h>
  73 #endif
  74
  75 #include <asm/io.h>
  76 #include <asm/errno.h>
  77
  78 #ifdef CONFIG_JFFS2_NAND
  79 #include <jffs2/jffs2.h>
  80 #endif
  81
  82 /*
  83  * CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting
  84  * a flash.  NAND flash is initialized prior to interrupts so standard timers
  85  * can't be used.  CONFIG_SYS_NAND_RESET_CNT should be set to a value
  86  * which is greater than (max NAND reset time / NAND status read time).
  87  * A conservative default of 200000 (500 us / 25 ns) is used as a default.
  88  */
  89 #ifndef CONFIG_SYS_NAND_RESET_CNT
  90 #define CONFIG_SYS_NAND_RESET_CNT 200000
  91 #endif
  92
  93 /* Define default oob placement schemes for large and small page devices */
  94 static struct nand_ecclayout nand_oob_8 = {
  95         .eccbytes = 3,
  96         .eccpos = {0, 1, 2},
  97         .oobfree = {
  98                 {.offset = 3,
  99                  .length = 2},
 100                 {.offset = 6,
 101                  .length = 2}}
 102 };
 103
 104 static struct nand_ecclayout nand_oob_16 = {
 105         .eccbytes = 6,
 106         .eccpos = {0, 1, 2, 3, 6, 7},
 107         .oobfree = {
 108                 {.offset = 8,
 109                  . length = 8}}
 110 };
 111
 112 static struct nand_ecclayout nand_oob_64 = {
 113         .eccbytes = 24,
 114         .eccpos = {
 115                    40, 41, 42, 43, 44, 45, 46, 47,
 116                    48, 49, 50, 51, 52, 53, 54, 55,
 117                    56, 57, 58, 59, 60, 61, 62, 63},
 118         .oobfree = {
 119                 {.offset = 2,
 120                  .length = 38}}
 121 };
 122
 123 static struct nand_ecclayout nand_oob_128 = {
 124         .eccbytes = 48,
 125         .eccpos = {
 126                     80,  81,  82,  83,  84,  85,  86,  87,
 127                     88,  89,  90,  91,  92,  93,  94,  95,
 128                     96,  97,  98,  99, 100, 101, 102, 103,
 129                    104, 105, 106, 107, 108, 109, 110, 111,
 130                    112, 113, 114, 115, 116, 117, 118, 119,
 131                    120, 121, 122, 123, 124, 125, 126, 127},
 132         .oobfree = {
 133                 {.offset = 2,
 134                  .length = 78}}
 135 };
 136
 137
 138 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
 139                            int new_state);
 140
 141 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
 142                              struct mtd_oob_ops *ops);
 143
 144 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this);
 145
 146 /*
 147  * For devices which display every fart in the system on a separate LED. Is
 148  * compiled away when LED support is disabled.
 149  */
 150 /* XXX U-BOOT XXX */
 151 #if 0
 152 DEFINE_LED_TRIGGER(nand_led_trigger);
 153 #endif
 154
 155 /**
 156  * nand_release_device - [GENERIC] release chip
 157  * @mtd:        MTD device structure
 158  *
 159  * Deselect, release chip lock and wake up anyone waiting on the device
 160  */
 161 /* XXX U-BOOT XXX */
 162 #if 0
 163 static void nand_release_device(struct mtd_info *mtd)
 164 {
 165         struct nand_chip *chip = mtd->priv;
 166
 167         /* De-select the NAND device */
 168         chip->select_chip(mtd, -1);
 169
 170         /* Release the controller and the chip */
 171         spin_lock(&chip->controller->lock);
 172         chip->controller->active = NULL;
 173         chip->state = FL_READY;
 174         wake_up(&chip->controller->wq);
 175         spin_unlock(&chip->controller->lock);
 176 }
 177 #else
 178 static void nand_release_device (struct mtd_info *mtd)
 179 {
 180         struct nand_chip *this = mtd->priv;
 181         this->select_chip(mtd, -1);     /* De-select the NAND device */
 182 }
 183 #endif
 184
 185 /**
 186  * nand_read_byte - [DEFAULT] read one byte from the chip
 187  * @mtd:        MTD device structure
 188  *
 189  * Default read function for 8bit buswith
 190  */
 191 static uint8_t nand_read_byte(struct mtd_info *mtd)
 192 {
 193         struct nand_chip *chip = mtd->priv;
 194         return readb(chip->IO_ADDR_R);
 195 }
 196
 197 /**
 198  * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
 199  * @mtd:        MTD device structure
 200  *
 201  * Default read function for 16bit buswith with
 202  * endianess conversion
 203  */
 204 static uint8_t nand_read_byte16(struct mtd_info *mtd)
 205 {
 206         struct nand_chip *chip = mtd->priv;
 207         return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
 208 }
 209
 210 /**
 211  * nand_read_word - [DEFAULT] read one word from the chip
 212  * @mtd:        MTD device structure
 213  *
 214  * Default read function for 16bit buswith without
 215  * endianess conversion
 216  */
 217 static u16 nand_read_word(struct mtd_info *mtd)
 218 {
 219         struct nand_chip *chip = mtd->priv;
 220         return readw(chip->IO_ADDR_R);
 221 }
 222
 223 /**
 224  * nand_select_chip - [DEFAULT] control CE line
 225  * @mtd:        MTD device structure
 226  * @chipnr:     chipnumber to select, -1 for deselect
 227  *
 228  * Default select function for 1 chip devices.
 229  */
 230 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 231 {
 232         struct nand_chip *chip = mtd->priv;
 233
 234         switch (chipnr) {
 235         case -1:
 236                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
 237                 break;
 238         case 0:
 239                 break;
 240
 241         default:
 242                 BUG();
 243         }
 244 }
 245
 246 /**
 247  * nand_write_buf - [DEFAULT] write buffer to chip
 248  * @mtd:        MTD device structure
 249  * @buf:        data buffer
 250  * @len:        number of bytes to write
 251  *
 252  * Default write function for 8bit buswith
 253  */
 254 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 255 {
 256         int i;
 257         struct nand_chip *chip = mtd->priv;
 258
 259         for (i = 0; i < len; i++)
 260                 writeb(buf[i], chip->IO_ADDR_W);
 261 }
 262
 263 /**
 264  * nand_read_buf - [DEFAULT] read chip data into buffer
 265  * @mtd:        MTD device structure
 266  * @buf:        buffer to store date
 267  * @len:        number of bytes to read
 268  *
 269  * Default read function for 8bit buswith
 270  */
 271 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 272 {
 273         int i;
 274         struct nand_chip *chip = mtd->priv;
 275
 276         for (i = 0; i < len; i++)
 277                 buf[i] = readb(chip->IO_ADDR_R);
 278 }
 279
 280 /**
 281  * nand_verify_buf - [DEFAULT] Verify chip data against buffer
 282  * @mtd:        MTD device structure
 283  * @buf:        buffer containing the data to compare
 284  * @len:        number of bytes to compare
 285  *
 286  * Default verify function for 8bit buswith
 287  */
 288 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 289 {
 290         int i;
 291         struct nand_chip *chip = mtd->priv;
 292
 293         for (i = 0; i < len; i++)
 294                 if (buf[i] != readb(chip->IO_ADDR_R))
 295                         return -EFAULT;
 296         return 0;
 297 }
 298
 299 /**
 300  * nand_write_buf16 - [DEFAULT] write buffer to chip
 301  * @mtd:        MTD device structure
 302  * @buf:        data buffer
 303  * @len:        number of bytes to write
 304  *
 305  * Default write function for 16bit buswith
 306  */
 307 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 308 {
 309         int i;
 310         struct nand_chip *chip = mtd->priv;
 311         u16 *p = (u16 *) buf;
 312         len >>= 1;
 313
 314         for (i = 0; i < len; i++)
 315                 writew(p[i], chip->IO_ADDR_W);
 316
 317 }
 318
 319 /**
 320  * nand_read_buf16 - [DEFAULT] read chip data into buffer
 321  * @mtd:        MTD device structure
 322  * @buf:        buffer to store date
 323  * @len:        number of bytes to read
 324  *
 325  * Default read function for 16bit buswith
 326  */
 327 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 328 {
 329         int i;
 330         struct nand_chip *chip = mtd->priv;
 331         u16 *p = (u16 *) buf;
 332         len >>= 1;
 333
 334         for (i = 0; i < len; i++)
 335                 p[i] = readw(chip->IO_ADDR_R);
 336 }
 337
 338 /**
 339  * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
 340  * @mtd:        MTD device structure
 341  * @buf:        buffer containing the data to compare
 342  * @len:        number of bytes to compare
 343  *
 344  * Default verify function for 16bit buswith
 345  */
 346 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 347 {
 348         int i;
 349         struct nand_chip *chip = mtd->priv;
 350         u16 *p = (u16 *) buf;
 351         len >>= 1;
 352
 353         for (i = 0; i < len; i++)
 354                 if (p[i] != readw(chip->IO_ADDR_R))
 355                         return -EFAULT;
 356
 357         return 0;
 358 }
 359
 360 /**
 361  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
 362  * @mtd:        MTD device structure
 363  * @ofs:        offset from device start
 364  * @getchip:    0, if the chip is already selected
 365  *
 366  * Check, if the block is bad.
 367  */
 368 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 369 {
 370         int page, chipnr, res = 0;
 371         struct nand_chip *chip = mtd->priv;
 372         u16 bad;
 373
 374         page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 375
 376         if (getchip) {
 377                 chipnr = (int)(ofs >> chip->chip_shift);
 378
 379                 nand_get_device(chip, mtd, FL_READING);
 380
 381                 /* Select the NAND device */
 382                 chip->select_chip(mtd, chipnr);
 383         }
 384
 385         if (chip->options & NAND_BUSWIDTH_16) {
 386                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
 387                               page);
 388                 bad = cpu_to_le16(chip->read_word(mtd));
 389                 if (chip->badblockpos & 0x1)
 390                         bad >>= 8;
 391                 if ((bad & 0xFF) != 0xff)
 392                         res = 1;
 393         } else {
 394                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
 395                 if (chip->read_byte(mtd) != 0xff)
 396                         res = 1;
 397         }
 398
 399         if (getchip)
 400                 nand_release_device(mtd);
 401
 402         return res;
 403 }
 404
 405 /**
 406  * nand_default_block_markbad - [DEFAULT] mark a block bad
 407  * @mtd:        MTD device structure
 408  * @ofs:        offset from device start
 409  *
 410  * This is the default implementation, which can be overridden by
 411  * a hardware specific driver.
 412 */
 413 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 414 {
 415         struct nand_chip *chip = mtd->priv;
 416         uint8_t buf[2] = { 0, 0 };
 417         int block, ret;
 418
 419         /* Get block number */
 420         block = (int)(ofs >> chip->bbt_erase_shift);
 421         if (chip->bbt)
 422                 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
 423
 424         /* Do we have a flash based bad block table ? */
 425         if (chip->options & NAND_USE_FLASH_BBT)
 426                 ret = nand_update_bbt(mtd, ofs);
 427         else {
 428                 /* We write two bytes, so we dont have to mess with 16 bit
 429                  * access
 430                  */
 431                 nand_get_device(chip, mtd, FL_WRITING);
 432                 ofs += mtd->oobsize;
 433                 chip->ops.len = chip->ops.ooblen = 2;
 434                 chip->ops.datbuf = NULL;
 435                 chip->ops.oobbuf = buf;
 436                 chip->ops.ooboffs = chip->badblockpos & ~0x01;
 437
 438                 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
 439                 nand_release_device(mtd);
 440         }
 441         if (!ret)
 442                 mtd->ecc_stats.badblocks++;
 443
 444         return ret;
 445 }
 446
 447 /**
 448  * nand_check_wp - [GENERIC] check if the chip is write protected
 449  * @mtd:        MTD device structure
 450  * Check, if the device is write protected
 451  *
 452  * The function expects, that the device is already selected
 453  */
 454 static int nand_check_wp(struct mtd_info *mtd)
 455 {
 456         struct nand_chip *chip = mtd->priv;
 457         /* Check the WP bit */
 458         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 459         return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
 460 }
 461
 462 /**
 463  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
 464  * @mtd:        MTD device structure
 465  * @ofs:        offset from device start
 466  * @getchip:    0, if the chip is already selected
 467  * @allowbbt:   1, if its allowed to access the bbt area
 468  *
 469  * Check, if the block is bad. Either by reading the bad block table or
 470  * calling of the scan function.
 471  */
 472 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
 473                                int allowbbt)
 474 {
 475         struct nand_chip *chip = mtd->priv;
 476
 477         if (!(chip->options & NAND_BBT_SCANNED)) {
 478                 chip->options |= NAND_BBT_SCANNED;
 479                 chip->scan_bbt(mtd);
 480         }
 481
 482         if (!chip->bbt)
 483                 return chip->block_bad(mtd, ofs, getchip);
 484
 485         /* Return info from the table */
 486         return nand_isbad_bbt(mtd, ofs, allowbbt);
 487 }
 488
 489 /*
 490  * Wait for the ready pin, after a command
 491  * The timeout is catched later.
 492  */
 493 /* XXX U-BOOT XXX */
 494 #if 0
 495 void nand_wait_ready(struct mtd_info *mtd)
 496 {
 497         struct nand_chip *chip = mtd->priv;
 498         unsigned long timeo = jiffies + 2;
 499
 500         led_trigger_event(nand_led_trigger, LED_FULL);
 501         /* wait until command is processed or timeout occures */
 502         do {
 503                 if (chip->dev_ready(mtd))
 504                         break;
 505                 touch_softlockup_watchdog();
 506         } while (time_before(jiffies, timeo));
 507         led_trigger_event(nand_led_trigger, LED_OFF);
 508 }
 509 EXPORT_SYMBOL_GPL(nand_wait_ready);
 510 #else
 511 void nand_wait_ready(struct mtd_info *mtd)
 512 {
 513         struct nand_chip *chip = mtd->priv;
 514         u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
 515
 516         reset_timer();
 517
 518         /* wait until command is processed or timeout occures */
 519         while (get_timer(0) < timeo) {
 520                 if (chip->dev_ready)
 521                         if (chip->dev_ready(mtd))
 522                                 break;
 523         }
 524 }
 525 #endif
 526
 527 /**
 528  * nand_command - [DEFAULT] Send command to NAND device
 529  * @mtd:        MTD device structure
 530  * @command:    the command to be sent
 531  * @column:     the column address for this command, -1 if none
 532  * @page_addr:  the page address for this command, -1 if none
 533  *
 534  * Send command to NAND device. This function is used for small page
 535  * devices (256/512 Bytes per page)
 536  */
 537 static void nand_command(struct mtd_info *mtd, unsigned int command,
 538                          int column, int page_addr)
 539 {
 540         register struct nand_chip *chip = mtd->priv;
 541         int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
 542         uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
 543
 544         /*
 545          * Write out the command to the device.
 546          */
 547         if (command == NAND_CMD_SEQIN) {
 548                 int readcmd;
 549
 550                 if (column >= mtd->writesize) {
 551                         /* OOB area */
 552                         column -= mtd->writesize;
 553                         readcmd = NAND_CMD_READOOB;
 554                 } else if (column < 256) {
 555                         /* First 256 bytes --> READ0 */
 556                         readcmd = NAND_CMD_READ0;
 557                 } else {
 558                         column -= 256;
 559                         readcmd = NAND_CMD_READ1;
 560                 }
 561                 chip->cmd_ctrl(mtd, readcmd, ctrl);
 562                 ctrl &= ~NAND_CTRL_CHANGE;
 563         }
 564         chip->cmd_ctrl(mtd, command, ctrl);
 565
 566         /*
 567          * Address cycle, when necessary
 568          */
 569         ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
 570         /* Serially input address */
 571         if (column != -1) {
 572                 /* Adjust columns for 16 bit buswidth */
 573                 if (chip->options & NAND_BUSWIDTH_16)
 574                         column >>= 1;
 575                 chip->cmd_ctrl(mtd, column, ctrl);
 576                 ctrl &= ~NAND_CTRL_CHANGE;
 577         }
 578         if (page_addr != -1) {
 579                 chip->cmd_ctrl(mtd, page_addr, ctrl);
 580                 ctrl &= ~NAND_CTRL_CHANGE;
 581                 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
 582                 /* One more address cycle for devices > 32MiB */
 583                 if (chip->chipsize > (32 << 20))
 584                         chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
 585         }
 586         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 587
 588         /*
 589          * program and erase have their own busy handlers
 590          * status and sequential in needs no delay
 591          */
 592         switch (command) {
 593
 594         case NAND_CMD_PAGEPROG:
 595         case NAND_CMD_ERASE1:
 596         case NAND_CMD_ERASE2:
 597         case NAND_CMD_SEQIN:
 598         case NAND_CMD_STATUS:
 599                 return;
 600
 601         case NAND_CMD_RESET:
 602                 if (chip->dev_ready)
 603                         break;
 604                 udelay(chip->chip_delay);
 605                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 606                                NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 607                 chip->cmd_ctrl(mtd,
 608                                NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 609                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
 610                         (rst_sts_cnt--));
 611                 return;
 612
 613                 /* This applies to read commands */
 614         default:
 615                 /*
 616                  * If we don't have access to the busy pin, we apply the given
 617                  * command delay
 618                  */
 619                 if (!chip->dev_ready) {
 620                         udelay(chip->chip_delay);
 621                         return;
 622                 }
 623         }
 624         /* Apply this short delay always to ensure that we do wait tWB in
 625          * any case on any machine. */
 626         ndelay(100);
 627
 628         nand_wait_ready(mtd);
 629 }
 630
 631 /**
 632  * nand_command_lp - [DEFAULT] Send command to NAND large page device
 633  * @mtd:        MTD device structure
 634  * @command:    the command to be sent
 635  * @column:     the column address for this command, -1 if none
 636  * @page_addr:  the page address for this command, -1 if none
 637  *
 638  * Send command to NAND device. This is the version for the new large page
 639  * devices We dont have the separate regions as we have in the small page
 640  * devices.  We must emulate NAND_CMD_READOOB to keep the code compatible.
 641  */
 642 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
 643                             int column, int page_addr)
 644 {
 645         register struct nand_chip *chip = mtd->priv;
 646         uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
 647
 648         /* Emulate NAND_CMD_READOOB */
 649         if (command == NAND_CMD_READOOB) {
 650                 column += mtd->writesize;
 651                 command = NAND_CMD_READ0;
 652         }
 653
 654         /* Command latch cycle */
 655         chip->cmd_ctrl(mtd, command & 0xff,
 656                        NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 657
 658         if (column != -1 || page_addr != -1) {
 659                 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
 660
 661                 /* Serially input address */
 662                 if (column != -1) {
 663                         /* Adjust columns for 16 bit buswidth */
 664                         if (chip->options & NAND_BUSWIDTH_16)
 665                                 column >>= 1;
 666                         chip->cmd_ctrl(mtd, column, ctrl);
 667                         ctrl &= ~NAND_CTRL_CHANGE;
 668                         chip->cmd_ctrl(mtd, column >> 8, ctrl);
 669                 }
 670                 if (page_addr != -1) {
 671                         chip->cmd_ctrl(mtd, page_addr, ctrl);
 672                         chip->cmd_ctrl(mtd, page_addr >> 8,
 673                                        NAND_NCE | NAND_ALE);
 674                         /* One more address cycle for devices > 128MiB */
 675                         if (chip->chipsize > (128 << 20))
 676                                 chip->cmd_ctrl(mtd, page_addr >> 16,
 677                                                NAND_NCE | NAND_ALE);
 678                 }
 679         }
 680         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 681
 682         /*
 683          * program and erase have their own busy handlers
 684          * status, sequential in, and deplete1 need no delay
 685          */
 686         switch (command) {
 687
 688         case NAND_CMD_CACHEDPROG:
 689         case NAND_CMD_PAGEPROG:
 690         case NAND_CMD_ERASE1:
 691         case NAND_CMD_ERASE2:
 692         case NAND_CMD_SEQIN:
 693         case NAND_CMD_RNDIN:
 694         case NAND_CMD_STATUS:
 695         case NAND_CMD_DEPLETE1:
 696                 return;
 697
 698                 /*
 699                  * read error status commands require only a short delay
 700                  */
 701         case NAND_CMD_STATUS_ERROR:
 702         case NAND_CMD_STATUS_ERROR0:
 703         case NAND_CMD_STATUS_ERROR1:
 704         case NAND_CMD_STATUS_ERROR2:
 705         case NAND_CMD_STATUS_ERROR3:
 706                 udelay(chip->chip_delay);
 707                 return;
 708
 709         case NAND_CMD_RESET:
 710                 if (chip->dev_ready)
 711                         break;
 712                 udelay(chip->chip_delay);
 713                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 714                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 715                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 716                                NAND_NCE | NAND_CTRL_CHANGE);
 717                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
 718                         (rst_sts_cnt--));
 719                 return;
 720
 721         case NAND_CMD_RNDOUT:
 722                 /* No ready / busy check necessary */
 723                 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
 724                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 725                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 726                                NAND_NCE | NAND_CTRL_CHANGE);
 727                 return;
 728
 729         case NAND_CMD_READ0:
 730                 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
 731                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 732                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 733                                NAND_NCE | NAND_CTRL_CHANGE);
 734
 735                 /* This applies to read commands */
 736         default:
 737                 /*
 738                  * If we don't have access to the busy pin, we apply the given
 739                  * command delay
 740                  */
 741                 if (!chip->dev_ready) {
 742                         udelay(chip->chip_delay);
 743                         return;
 744                 }
 745         }
 746
 747         /* Apply this short delay always to ensure that we do wait tWB in
 748          * any case on any machine. */
 749         ndelay(100);
 750
 751         nand_wait_ready(mtd);
 752 }
 753
 754 /**
 755  * nand_get_device - [GENERIC] Get chip for selected access
 756  * @chip:       the nand chip descriptor
 757  * @mtd:        MTD device structure
 758  * @new_state:  the state which is requested
 759  *
 760  * Get the device and lock it for exclusive access
 761  */
 762 /* XXX U-BOOT XXX */
 763 #if 0
 764 static int
 765 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
 766 {
 767         spinlock_t *lock = &chip->controller->lock;
 768         wait_queue_head_t *wq = &chip->controller->wq;
 769         DECLARE_WAITQUEUE(wait, current);
 770  retry:
 771         spin_lock(lock);
 772
 773         /* Hardware controller shared among independend devices */
 774         /* Hardware controller shared among independend devices */
 775         if (!chip->controller->active)
 776                 chip->controller->active = chip;
 777
 778         if (chip->controller->active == chip && chip->state == FL_READY) {
 779                 chip->state = new_state;
 780                 spin_unlock(lock);
 781                 return 0;
 782         }
 783         if (new_state == FL_PM_SUSPENDED) {
 784                 spin_unlock(lock);
 785                 return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN;
 786         }
 787         set_current_state(TASK_UNINTERRUPTIBLE);
 788         add_wait_queue(wq, &wait);
 789         spin_unlock(lock);
 790         schedule();
 791         remove_wait_queue(wq, &wait);
 792         goto retry;
 793 }
 794 #else
 795 static int nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state)
 796 {
 797         this->state = new_state;
 798         return 0;
 799 }
 800 #endif
 801
 802 /**
 803  * nand_wait - [DEFAULT]  wait until the command is done
 804  * @mtd:        MTD device structure
 805  * @chip:       NAND chip structure
 806  *
 807  * Wait for command done. This applies to erase and program only
 808  * Erase can take up to 400ms and program up to 20ms according to
 809  * general NAND and SmartMedia specs
 810  */
 811 /* XXX U-BOOT XXX */
 812 #if 0
 813 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
 814 {
 815
 816         unsigned long timeo = jiffies;
 817         int status, state = chip->state;
 818
 819         if (state == FL_ERASING)
 820                 timeo += (HZ * 400) / 1000;
 821         else
 822                 timeo += (HZ * 20) / 1000;
 823
 824         led_trigger_event(nand_led_trigger, LED_FULL);
 825
 826         /* Apply this short delay always to ensure that we do wait tWB in
 827          * any case on any machine. */
 828         ndelay(100);
 829
 830         if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
 831                 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
 832         else
 833                 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 834
 835         while (time_before(jiffies, timeo)) {
 836                 if (chip->dev_ready) {
 837                         if (chip->dev_ready(mtd))
 838                                 break;
 839                 } else {
 840                         if (chip->read_byte(mtd) & NAND_STATUS_READY)
 841                                 break;
 842                 }
 843                 cond_resched();
 844         }
 845         led_trigger_event(nand_led_trigger, LED_OFF);
 846
 847         status = (int)chip->read_byte(mtd);
 848         return status;
 849 }
 850 #else
 851 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this)
 852 {
 853         unsigned long   timeo;
 854         int state = this->state;
 855
 856         if (state == FL_ERASING)
 857                 timeo = (CONFIG_SYS_HZ * 400) / 1000;
 858         else
 859                 timeo = (CONFIG_SYS_HZ * 20) / 1000;
 860
 861         if ((state == FL_ERASING) && (this->options & NAND_IS_AND))
 862                 this->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
 863         else
 864                 this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 865
 866         reset_timer();
 867
 868         while (1) {
 869                 if (get_timer(0) > timeo) {
 870                         printf("Timeout!");
 871                         return 0x01;
 872                 }
 873
 874                 if (this->dev_ready) {
 875                         if (this->dev_ready(mtd))
 876                                 break;
 877                 } else {
 878                         if (this->read_byte(mtd) & NAND_STATUS_READY)
 879                                 break;
 880                 }
 881         }
 882 #ifdef PPCHAMELON_NAND_TIMER_HACK
 883         reset_timer();
 884         while (get_timer(0) < 10);
 885 #endif /*  PPCHAMELON_NAND_TIMER_HACK */
 886
 887         return this->read_byte(mtd);
 888 }
 889 #endif
 890
 891 /**
 892  * nand_read_page_raw - [Intern] read raw page data without ecc
 893  * @mtd:        mtd info structure
 894  * @chip:       nand chip info structure
 895  * @buf:        buffer to store read data
 896  */
 897 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
 898                               uint8_t *buf, int page)
 899 {
 900         chip->read_buf(mtd, buf, mtd->writesize);
 901         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 902         return 0;
 903 }
 904
 905 /**
 906  * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
 907  * @mtd:        mtd info structure
 908  * @chip:       nand chip info structure
 909  * @buf:        buffer to store read data
 910  */
 911 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
 912                                 uint8_t *buf, int page)
 913 {
 914         int i, eccsize = chip->ecc.size;
 915         int eccbytes = chip->ecc.bytes;
 916         int eccsteps = chip->ecc.steps;
 917         uint8_t *p = buf;
 918         uint8_t *ecc_calc = chip->buffers->ecccalc;
 919         uint8_t *ecc_code = chip->buffers->ecccode;
 920         uint32_t *eccpos = chip->ecc.layout->eccpos;
 921
 922         chip->ecc.read_page_raw(mtd, chip, buf, page);
 923
 924         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
 925                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 926
 927         for (i = 0; i < chip->ecc.total; i++)
 928                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 929
 930         eccsteps = chip->ecc.steps;
 931         p = buf;
 932
 933         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 934                 int stat;
 935
 936                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 937                 if (stat < 0)
 938                         mtd->ecc_stats.failed++;
 939                 else
 940                         mtd->ecc_stats.corrected += stat;
 941         }
 942         return 0;
 943 }
 944
 945 /**
 946  * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
 947  * @mtd:        mtd info structure
 948  * @chip:       nand chip info structure
 949  * @dataofs     offset of requested data within the page
 950  * @readlen     data length
 951  * @buf:        buffer to store read data
 952  */
 953 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
 954 {
 955         int start_step, end_step, num_steps;
 956         uint32_t *eccpos = chip->ecc.layout->eccpos;
 957         uint8_t *p;
 958         int data_col_addr, i, gaps = 0;
 959         int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
 960         int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
 961
 962         /* Column address wihin the page aligned to ECC size (256bytes). */
 963         start_step = data_offs / chip->ecc.size;
 964         end_step = (data_offs + readlen - 1) / chip->ecc.size;
 965         num_steps = end_step - start_step + 1;
 966
 967         /* Data size aligned to ECC ecc.size*/
 968         datafrag_len = num_steps * chip->ecc.size;
 969         eccfrag_len = num_steps * chip->ecc.bytes;
 970
 971         data_col_addr = start_step * chip->ecc.size;
 972         /* If we read not a page aligned data */
 973         if (data_col_addr != 0)
 974                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
 975
 976         p = bufpoi + data_col_addr;
 977         chip->read_buf(mtd, p, datafrag_len);
 978
 979         /* Calculate  ECC */
 980         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
 981                 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
 982
 983         /* The performance is faster if to position offsets
 984            according to ecc.pos. Let make sure here that
 985            there are no gaps in ecc positions */
 986         for (i = 0; i < eccfrag_len - 1; i++) {
 987                 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
 988                         eccpos[i + start_step * chip->ecc.bytes + 1]) {
 989                         gaps = 1;
 990                         break;
 991                 }
 992         }
 993         if (gaps) {
 994                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
 995                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 996         } else {
 997                 /* send the command to read the particular ecc bytes */
 998                 /* take care about buswidth alignment in read_buf */
 999                 aligned_pos = eccpos[start_step * chip->ecc.bytes] & ~(busw - 1);
1000                 aligned_len = eccfrag_len;
1001                 if (eccpos[start_step * chip->ecc.bytes] & (busw - 1))
1002                         aligned_len++;
1003                 if (eccpos[(start_step + num_steps) * chip->ecc.bytes] & (busw - 1))
1004                         aligned_len++;
1005
1006                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize + aligned_pos, -1);
1007                 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1008         }
1009
1010         for (i = 0; i < eccfrag_len; i++)
1011                 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + start_step * chip->ecc.bytes]];
1012
1013         p = bufpoi + data_col_addr;
1014         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1015                 int stat;
1016
1017                 stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1018                 if (stat < 0)
1019                         mtd->ecc_stats.failed++;
1020                 else
1021                         mtd->ecc_stats.corrected += stat;
1022         }
1023         return 0;
1024 }
1025
1026 /**
1027  * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
1028  * @mtd:        mtd info structure
1029  * @chip:       nand chip info structure
1030  * @buf:        buffer to store read data
1031  *
1032  * Not for syndrome calculating ecc controllers which need a special oob layout
1033  */
1034 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1035                                 uint8_t *buf, int page)
1036 {
1037         int i, eccsize = chip->ecc.size;
1038         int eccbytes = chip->ecc.bytes;
1039         int eccsteps = chip->ecc.steps;
1040         uint8_t *p = buf;
1041         uint8_t *ecc_calc = chip->buffers->ecccalc;
1042         uint8_t *ecc_code = chip->buffers->ecccode;
1043         uint32_t *eccpos = chip->ecc.layout->eccpos;
1044
1045         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1046                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1047                 chip->read_buf(mtd, p, eccsize);
1048                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1049         }
1050         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1051
1052         for (i = 0; i < chip->ecc.total; i++)
1053                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1054
1055         eccsteps = chip->ecc.steps;
1056         p = buf;
1057
1058         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1059                 int stat;
1060
1061                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1062                 if (stat == -1)
1063                         mtd->ecc_stats.failed++;
1064                 else
1065                         mtd->ecc_stats.corrected += stat;
1066         }
1067         return 0;
1068 }
1069
1070 /**
1071  * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
1072  * @mtd:        mtd info structure
1073  * @chip:       nand chip info structure
1074  * @buf:        buffer to store read data
1075  *
1076  * Hardware ECC for large page chips, require OOB to be read first.
1077  * For this ECC mode, the write_page method is re-used from ECC_HW.
1078  * These methods read/write ECC from the OOB area, unlike the
1079  * ECC_HW_SYNDROME support with multiple ECC steps, follows the
1080  * "infix ECC" scheme and reads/writes ECC from the data area, by
1081  * overwriting the NAND manufacturer bad block markings.
1082  */
1083 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1084         struct nand_chip *chip, uint8_t *buf, int page)
1085 {
1086         int i, eccsize = chip->ecc.size;
1087         int eccbytes = chip->ecc.bytes;
1088         int eccsteps = chip->ecc.steps;
1089         uint8_t *p = buf;
1090         uint8_t *ecc_code = chip->buffers->ecccode;
1091         uint32_t *eccpos = chip->ecc.layout->eccpos;
1092         uint8_t *ecc_calc = chip->buffers->ecccalc;
1093
1094         /* Read the OOB area first */
1095         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1096         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1097         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1098
1099         for (i = 0; i < chip->ecc.total; i++)
1100                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1101
1102         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1103                 int stat;
1104
1105                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1106                 chip->read_buf(mtd, p, eccsize);
1107                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1108
1109                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1110                 if (stat < 0)
1111                         mtd->ecc_stats.failed++;
1112                 else
1113                         mtd->ecc_stats.corrected += stat;
1114         }
1115         return 0;
1116 }
1117
1118 /**
1119  * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
1120  * @mtd:        mtd info structure
1121  * @chip:       nand chip info structure
1122  * @buf:        buffer to store read data
1123  *
1124  * The hw generator calculates the error syndrome automatically. Therefor
1125  * we need a special oob layout and handling.
1126  */
1127 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1128                                    uint8_t *buf, int page)
1129 {
1130         int i, eccsize = chip->ecc.size;
1131         int eccbytes = chip->ecc.bytes;
1132         int eccsteps = chip->ecc.steps;
1133         uint8_t *p = buf;
1134         uint8_t *oob = chip->oob_poi;
1135
1136         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1137                 int stat;
1138
1139                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1140                 chip->read_buf(mtd, p, eccsize);
1141
1142                 if (chip->ecc.prepad) {
1143                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1144                         oob += chip->ecc.prepad;
1145                 }
1146
1147                 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1148                 chip->read_buf(mtd, oob, eccbytes);
1149                 stat = chip->ecc.correct(mtd, p, oob, NULL);
1150
1151                 if (stat < 0)
1152                         mtd->ecc_stats.failed++;
1153                 else
1154                         mtd->ecc_stats.corrected += stat;
1155
1156                 oob += eccbytes;
1157
1158                 if (chip->ecc.postpad) {
1159                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1160                         oob += chip->ecc.postpad;
1161                 }
1162         }
1163
1164         /* Calculate remaining oob bytes */
1165         i = mtd->oobsize - (oob - chip->oob_poi);
1166         if (i)
1167                 chip->read_buf(mtd, oob, i);
1168
1169         return 0;
1170 }
1171
1172 /**
1173  * nand_transfer_oob - [Internal] Transfer oob to client buffer
1174  * @chip:       nand chip structure
1175  * @oob:        oob destination address
1176  * @ops:        oob ops structure
1177  * @len:        size of oob to transfer
1178  */
1179 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1180                                   struct mtd_oob_ops *ops, size_t len)
1181 {
1182         switch(ops->mode) {
1183
1184         case MTD_OOB_PLACE:
1185         case MTD_OOB_RAW:
1186                 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1187                 return oob + len;
1188
1189         case MTD_OOB_AUTO: {
1190                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1191                 uint32_t boffs = 0, roffs = ops->ooboffs;
1192                 size_t bytes = 0;
1193
1194                 for(; free->length && len; free++, len -= bytes) {
1195                         /* Read request not from offset 0 ? */
1196                         if (unlikely(roffs)) {
1197                                 if (roffs >= free->length) {
1198                                         roffs -= free->length;
1199                                         continue;
1200                                 }
1201                                 boffs = free->offset + roffs;
1202                                 bytes = min_t(size_t, len,
1203                                               (free->length - roffs));
1204                                 roffs = 0;
1205                         } else {
1206                                 bytes = min_t(size_t, len, free->length);
1207                                 boffs = free->offset;
1208                         }
1209                         memcpy(oob, chip->oob_poi + boffs, bytes);
1210                         oob += bytes;
1211                 }
1212                 return oob;
1213         }
1214         default:
1215                 BUG();
1216         }
1217         return NULL;
1218 }
1219
1220 /**
1221  * nand_do_read_ops - [Internal] Read data with ECC
1222  *
1223  * @mtd:        MTD device structure
1224  * @from:       offset to read from
1225  * @ops:        oob ops structure
1226  *
1227  * Internal function. Called with chip held.
1228  */
1229 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1230                             struct mtd_oob_ops *ops)
1231 {
1232         int chipnr, page, realpage, col, bytes, aligned;
1233         struct nand_chip *chip = mtd->priv;
1234         struct mtd_ecc_stats stats;
1235         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1236         int sndcmd = 1;
1237         int ret = 0;
1238         uint32_t readlen = ops->len;
1239         uint32_t oobreadlen = ops->ooblen;
1240         uint8_t *bufpoi, *oob, *buf;
1241
1242         stats = mtd->ecc_stats;
1243
1244         chipnr = (int)(from >> chip->chip_shift);
1245         chip->select_chip(mtd, chipnr);
1246
1247         realpage = (int)(from >> chip->page_shift);
1248         page = realpage & chip->pagemask;
1249
1250         col = (int)(from & (mtd->writesize - 1));
1251
1252         buf = ops->datbuf;
1253         oob = ops->oobbuf;
1254
1255         while(1) {
1256                 bytes = min(mtd->writesize - col, readlen);
1257                 aligned = (bytes == mtd->writesize);
1258
1259                 /* Is the current page in the buffer ? */
1260                 if (realpage != chip->pagebuf || oob) {
1261                         bufpoi = aligned ? buf : chip->buffers->databuf;
1262
1263                         if (likely(sndcmd)) {
1264                                 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1265                                 sndcmd = 0;
1266                         }
1267
1268                         /* Now read the page into the buffer */
1269                         if (unlikely(ops->mode == MTD_OOB_RAW))
1270                                 ret = chip->ecc.read_page_raw(mtd, chip,
1271                                                 bufpoi, page);
1272                         else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1273                                 ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi);
1274                         else
1275                                 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1276                                                 page);
1277                         if (ret < 0)
1278                                 break;
1279
1280                         /* Transfer not aligned data */
1281                         if (!aligned) {
1282                                 if (!NAND_SUBPAGE_READ(chip) && !oob)
1283                                         chip->pagebuf = realpage;
1284                                 memcpy(buf, chip->buffers->databuf + col, bytes);
1285                         }
1286
1287                         buf += bytes;
1288
1289                         if (unlikely(oob)) {
1290                                 /* Raw mode does data:oob:data:oob */
1291                                 if (ops->mode != MTD_OOB_RAW) {
1292                                         int toread = min(oobreadlen,
1293                                                 chip->ecc.layout->oobavail);
1294                                         if (toread) {
1295                                                 oob = nand_transfer_oob(chip,
1296                                                         oob, ops, toread);
1297                                                 oobreadlen -= toread;
1298                                         }
1299                                 } else
1300                                         buf = nand_transfer_oob(chip,
1301                                                 buf, ops, mtd->oobsize);
1302                         }
1303
1304                         if (!(chip->options & NAND_NO_READRDY)) {
1305                                 /*
1306                                  * Apply delay or wait for ready/busy pin. Do
1307                                  * this before the AUTOINCR check, so no
1308                                  * problems arise if a chip which does auto
1309                                  * increment is marked as NOAUTOINCR by the
1310                                  * board driver.
1311                                  */
1312                                 if (!chip->dev_ready)
1313                                         udelay(chip->chip_delay);
1314                                 else
1315                                         nand_wait_ready(mtd);
1316                         }
1317                 } else {
1318                         memcpy(buf, chip->buffers->databuf + col, bytes);
1319                         buf += bytes;
1320                 }
1321
1322                 readlen -= bytes;
1323
1324                 if (!readlen)
1325                         break;
1326
1327                 /* For subsequent reads align to page boundary. */
1328                 col = 0;
1329                 /* Increment page address */
1330                 realpage++;
1331
1332                 page = realpage & chip->pagemask;
1333                 /* Check, if we cross a chip boundary */
1334                 if (!page) {
1335                         chipnr++;
1336                         chip->select_chip(mtd, -1);
1337                         chip->select_chip(mtd, chipnr);
1338                 }
1339
1340                 /* Check, if the chip supports auto page increment
1341                  * or if we have hit a block boundary.
1342                  */
1343                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1344                         sndcmd = 1;
1345         }
1346
1347         ops->retlen = ops->len - (size_t) readlen;
1348         if (oob)
1349                 ops->oobretlen = ops->ooblen - oobreadlen;
1350
1351         if (ret)
1352                 return ret;
1353
1354         if (mtd->ecc_stats.failed - stats.failed)
1355                 return -EBADMSG;
1356
1357         return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1358 }
1359
1360 /**
1361  * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1362  * @mtd:        MTD device structure
1363  * @from:       offset to read from
1364  * @len:        number of bytes to read
1365  * @retlen:     pointer to variable to store the number of read bytes
1366  * @buf:        the databuffer to put data
1367  *
1368  * Get hold of the chip and call nand_do_read
1369  */
1370 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1371                      size_t *retlen, uint8_t *buf)
1372 {
1373         struct nand_chip *chip = mtd->priv;
1374         int ret;
1375
1376         /* Do not allow reads past end of device */
1377         if ((from + len) > mtd->size)
1378                 return -EINVAL;
1379         if (!len)
1380                 return 0;
1381
1382         nand_get_device(chip, mtd, FL_READING);
1383
1384         chip->ops.len = len;
1385         chip->ops.datbuf = buf;
1386         chip->ops.oobbuf = NULL;
1387
1388         ret = nand_do_read_ops(mtd, from, &chip->ops);
1389
1390         *retlen = chip->ops.retlen;
1391
1392         nand_release_device(mtd);
1393
1394         return ret;
1395 }
1396
1397 /**
1398  * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1399  * @mtd:        mtd info structure
1400  * @chip:       nand chip info structure
1401  * @page:       page number to read
1402  * @sndcmd:     flag whether to issue read command or not
1403  */
1404 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1405                              int page, int sndcmd)
1406 {
1407         if (sndcmd) {
1408                 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1409                 sndcmd = 0;
1410         }
1411         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1412         return sndcmd;
1413 }
1414
1415 /**
1416  * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1417  *                          with syndromes
1418  * @mtd:        mtd info structure
1419  * @chip:       nand chip info structure
1420  * @page:       page number to read
1421  * @sndcmd:     flag whether to issue read command or not
1422  */
1423 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1424                                   int page, int sndcmd)
1425 {
1426         uint8_t *buf = chip->oob_poi;
1427         int length = mtd->oobsize;
1428         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1429         int eccsize = chip->ecc.size;
1430         uint8_t *bufpoi = buf;
1431         int i, toread, sndrnd = 0, pos;
1432
1433         chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1434         for (i = 0; i < chip->ecc.steps; i++) {
1435                 if (sndrnd) {
1436                         pos = eccsize + i * (eccsize + chunk);
1437                         if (mtd->writesize > 512)
1438                                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1439                         else
1440                                 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1441                 } else
1442                         sndrnd = 1;
1443                 toread = min_t(int, length, chunk);
1444                 chip->read_buf(mtd, bufpoi, toread);
1445                 bufpoi += toread;
1446                 length -= toread;
1447         }
1448         if (length > 0)
1449                 chip->read_buf(mtd, bufpoi, length);
1450
1451         return 1;
1452 }
1453
1454 /**
1455  * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1456  * @mtd:        mtd info structure
1457  * @chip:       nand chip info structure
1458  * @page:       page number to write
1459  */
1460 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1461                               int page)
1462 {
1463         int status = 0;
1464         const uint8_t *buf = chip->oob_poi;
1465         int length = mtd->oobsize;
1466
1467         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1468         chip->write_buf(mtd, buf, length);
1469         /* Send command to program the OOB data */
1470         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1471
1472         status = chip->waitfunc(mtd, chip);
1473
1474         return status & NAND_STATUS_FAIL ? -EIO : 0;
1475 }
1476
1477 /**
1478  * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1479  *                           with syndrome - only for large page flash !
1480  * @mtd:        mtd info structure
1481  * @chip:       nand chip info structure
1482  * @page:       page number to write
1483  */
1484 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1485                                    struct nand_chip *chip, int page)
1486 {
1487         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1488         int eccsize = chip->ecc.size, length = mtd->oobsize;
1489         int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1490         const uint8_t *bufpoi = chip->oob_poi;
1491
1492         /*
1493          * data-ecc-data-ecc ... ecc-oob
1494          * or
1495          * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1496          */
1497         if (!chip->ecc.prepad && !chip->ecc.postpad) {
1498                 pos = steps * (eccsize + chunk);
1499                 steps = 0;
1500         } else
1501                 pos = eccsize;
1502
1503         chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1504         for (i = 0; i < steps; i++) {
1505                 if (sndcmd) {
1506                         if (mtd->writesize <= 512) {
1507                                 uint32_t fill = 0xFFFFFFFF;
1508
1509                                 len = eccsize;
1510                                 while (len > 0) {
1511                                         int num = min_t(int, len, 4);
1512                                         chip->write_buf(mtd, (uint8_t *)&fill,
1513                                                         num);
1514                                         len -= num;
1515                                 }
1516                         } else {
1517                                 pos = eccsize + i * (eccsize + chunk);
1518                                 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1519                         }
1520                 } else
1521                         sndcmd = 1;
1522                 len = min_t(int, length, chunk);
1523                 chip->write_buf(mtd, bufpoi, len);
1524                 bufpoi += len;
1525                 length -= len;
1526         }
1527         if (length > 0)
1528                 chip->write_buf(mtd, bufpoi, length);
1529
1530         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1531         status = chip->waitfunc(mtd, chip);
1532
1533         return status & NAND_STATUS_FAIL ? -EIO : 0;
1534 }
1535
1536 /**
1537  * nand_do_read_oob - [Intern] NAND read out-of-band
1538  * @mtd:        MTD device structure
1539  * @from:       offset to read from
1540  * @ops:        oob operations description structure
1541  *
1542  * NAND read out-of-band data from the spare area
1543  */
1544 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1545                             struct mtd_oob_ops *ops)
1546 {
1547         int page, realpage, chipnr, sndcmd = 1;
1548         struct nand_chip *chip = mtd->priv;
1549         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1550         int readlen = ops->ooblen;
1551         int len;
1552         uint8_t *buf = ops->oobbuf;
1553
1554         MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n",
1555                   (unsigned long long)from, readlen);
1556
1557         if (ops->mode == MTD_OOB_AUTO)
1558                 len = chip->ecc.layout->oobavail;
1559         else
1560                 len = mtd->oobsize;
1561
1562         if (unlikely(ops->ooboffs >= len)) {
1563                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1564                           "Attempt to start read outside oob\n");
1565                 return -EINVAL;
1566         }
1567
1568         /* Do not allow reads past end of device */
1569         if (unlikely(from >= mtd->size ||
1570                      ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1571                                         (from >> chip->page_shift)) * len)) {
1572                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1573                           "Attempt read beyond end of device\n");
1574                 return -EINVAL;
1575         }
1576
1577         chipnr = (int)(from >> chip->chip_shift);
1578         chip->select_chip(mtd, chipnr);
1579
1580         /* Shift to get page */
1581         realpage = (int)(from >> chip->page_shift);
1582         page = realpage & chip->pagemask;
1583
1584         while(1) {
1585                 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1586
1587                 len = min(len, readlen);
1588                 buf = nand_transfer_oob(chip, buf, ops, len);
1589
1590                 if (!(chip->options & NAND_NO_READRDY)) {
1591                         /*
1592                          * Apply delay or wait for ready/busy pin. Do this
1593                          * before the AUTOINCR check, so no problems arise if a
1594                          * chip which does auto increment is marked as
1595                          * NOAUTOINCR by the board driver.
1596                          */
1597                         if (!chip->dev_ready)
1598                                 udelay(chip->chip_delay);
1599                         else
1600                                 nand_wait_ready(mtd);
1601                 }
1602
1603                 readlen -= len;
1604                 if (!readlen)
1605                         break;
1606
1607                 /* Increment page address */
1608                 realpage++;
1609
1610                 page = realpage & chip->pagemask;
1611                 /* Check, if we cross a chip boundary */
1612                 if (!page) {
1613                         chipnr++;
1614                         chip->select_chip(mtd, -1);
1615                         chip->select_chip(mtd, chipnr);
1616                 }
1617
1618                 /* Check, if the chip supports auto page increment
1619                  * or if we have hit a block boundary.
1620                  */
1621                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1622                         sndcmd = 1;
1623         }
1624
1625         ops->oobretlen = ops->ooblen;
1626         return 0;
1627 }
1628
1629 /**
1630  * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1631  * @mtd:        MTD device structure
1632  * @from:       offset to read from
1633  * @ops:        oob operation description structure
1634  *
1635  * NAND read data and/or out-of-band data
1636  */
1637 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1638                          struct mtd_oob_ops *ops)
1639 {
1640         struct nand_chip *chip = mtd->priv;
1641         int ret = -ENOTSUPP;
1642
1643         ops->retlen = 0;
1644
1645         /* Do not allow reads past end of device */
1646         if (ops->datbuf && (from + ops->len) > mtd->size) {
1647                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1648                           "Attempt read beyond end of device\n");
1649                 return -EINVAL;
1650         }
1651
1652         nand_get_device(chip, mtd, FL_READING);
1653
1654         switch(ops->mode) {
1655         case MTD_OOB_PLACE:
1656         case MTD_OOB_AUTO:
1657         case MTD_OOB_RAW:
1658                 break;
1659
1660         default:
1661                 goto out;
1662         }
1663
1664         if (!ops->datbuf)
1665                 ret = nand_do_read_oob(mtd, from, ops);
1666         else
1667                 ret = nand_do_read_ops(mtd, from, ops);
1668
1669  out:
1670         nand_release_device(mtd);
1671         return ret;
1672 }
1673
1674
1675 /**
1676  * nand_write_page_raw - [Intern] raw page write function
1677  * @mtd:        mtd info structure
1678  * @chip:       nand chip info structure
1679  * @buf:        data buffer
1680  */
1681 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1682                                 const uint8_t *buf)
1683 {
1684         chip->write_buf(mtd, buf, mtd->writesize);
1685         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1686 }
1687
1688 /**
1689  * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1690  * @mtd:        mtd info structure
1691  * @chip:       nand chip info structure
1692  * @buf:        data buffer
1693  */
1694 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1695                                   const uint8_t *buf)
1696 {
1697         int i, eccsize = chip->ecc.size;
1698         int eccbytes = chip->ecc.bytes;
1699         int eccsteps = chip->ecc.steps;
1700         uint8_t *ecc_calc = chip->buffers->ecccalc;
1701         const uint8_t *p = buf;
1702         uint32_t *eccpos = chip->ecc.layout->eccpos;
1703
1704         /* Software ecc calculation */
1705         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1706                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1707
1708         for (i = 0; i < chip->ecc.total; i++)
1709                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1710
1711         chip->ecc.write_page_raw(mtd, chip, buf);
1712 }
1713
1714 /**
1715  * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1716  * @mtd:        mtd info structure
1717  * @chip:       nand chip info structure
1718  * @buf:        data buffer
1719  */
1720 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1721                                   const uint8_t *buf)
1722 {
1723         int i, eccsize = chip->ecc.size;
1724         int eccbytes = chip->ecc.bytes;
1725         int eccsteps = chip->ecc.steps;
1726         uint8_t *ecc_calc = chip->buffers->ecccalc;
1727         const uint8_t *p = buf;
1728         uint32_t *eccpos = chip->ecc.layout->eccpos;
1729
1730         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1731                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1732                 chip->write_buf(mtd, p, eccsize);
1733                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1734         }
1735
1736         for (i = 0; i < chip->ecc.total; i++)
1737                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1738
1739         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1740 }
1741
1742 /**
1743  * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1744  * @mtd:        mtd info structure
1745  * @chip:       nand chip info structure
1746  * @buf:        data buffer
1747  *
1748  * The hw generator calculates the error syndrome automatically. Therefor
1749  * we need a special oob layout and handling.
1750  */
1751 static void nand_write_page_syndrome(struct mtd_info *mtd,
1752                                     struct nand_chip *chip, const uint8_t *buf)
1753 {
1754         int i, eccsize = chip->ecc.size;
1755         int eccbytes = chip->ecc.bytes;
1756         int eccsteps = chip->ecc.steps;
1757         const uint8_t *p = buf;
1758         uint8_t *oob = chip->oob_poi;
1759
1760         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1761
1762                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1763                 chip->write_buf(mtd, p, eccsize);
1764
1765                 if (chip->ecc.prepad) {
1766                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1767                         oob += chip->ecc.prepad;
1768                 }
1769
1770                 chip->ecc.calculate(mtd, p, oob);
1771                 chip->write_buf(mtd, oob, eccbytes);
1772                 oob += eccbytes;
1773
1774                 if (chip->ecc.postpad) {
1775                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1776                         oob += chip->ecc.postpad;
1777                 }
1778         }
1779
1780         /* Calculate remaining oob bytes */
1781         i = mtd->oobsize - (oob - chip->oob_poi);
1782         if (i)
1783                 chip->write_buf(mtd, oob, i);
1784 }
1785
1786 /**
1787  * nand_write_page - [REPLACEABLE] write one page
1788  * @mtd:        MTD device structure
1789  * @chip:       NAND chip descriptor
1790  * @buf:        the data to write
1791  * @page:       page number to write
1792  * @cached:     cached programming
1793  * @raw:        use _raw version of write_page
1794  */
1795 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1796                            const uint8_t *buf, int page, int cached, int raw)
1797 {
1798         int status;
1799
1800         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1801
1802         if (unlikely(raw))
1803                 chip->ecc.write_page_raw(mtd, chip, buf);
1804         else
1805                 chip->ecc.write_page(mtd, chip, buf);
1806
1807         /*
1808          * Cached progamming disabled for now, Not sure if its worth the
1809          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1810          */
1811         cached = 0;
1812
1813         if (!cached || !(chip->options & NAND_CACHEPRG)) {
1814
1815                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1816                 status = chip->waitfunc(mtd, chip);
1817                 /*
1818                  * See if operation failed and additional status checks are
1819                  * available
1820                  */
1821                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1822                         status = chip->errstat(mtd, chip, FL_WRITING, status,
1823                                                page);
1824
1825                 if (status & NAND_STATUS_FAIL)
1826                         return -EIO;
1827         } else {
1828                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1829                 status = chip->waitfunc(mtd, chip);
1830         }
1831
1832 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1833         /* Send command to read back the data */
1834         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1835
1836         if (chip->verify_buf(mtd, buf, mtd->writesize))
1837                 return -EIO;
1838 #endif
1839         return 0;
1840 }
1841
1842 /**
1843  * nand_fill_oob - [Internal] Transfer client buffer to oob
1844  * @chip:       nand chip structure
1845  * @oob:        oob data buffer
1846  * @ops:        oob ops structure
1847  */
1848 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
1849                                   struct mtd_oob_ops *ops)
1850 {
1851         size_t len = ops->ooblen;
1852
1853         switch(ops->mode) {
1854
1855         case MTD_OOB_PLACE:
1856         case MTD_OOB_RAW:
1857                 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1858                 return oob + len;
1859
1860         case MTD_OOB_AUTO: {
1861                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1862                 uint32_t boffs = 0, woffs = ops->ooboffs;
1863                 size_t bytes = 0;
1864
1865                 for(; free->length && len; free++, len -= bytes) {
1866                         /* Write request not from offset 0 ? */
1867                         if (unlikely(woffs)) {
1868                                 if (woffs >= free->length) {
1869                                         woffs -= free->length;
1870                                         continue;
1871                                 }
1872                                 boffs = free->offset + woffs;
1873                                 bytes = min_t(size_t, len,
1874                                               (free->length - woffs));
1875                                 woffs = 0;
1876                         } else {
1877                                 bytes = min_t(size_t, len, free->length);
1878                                 boffs = free->offset;
1879                         }
1880                         memcpy(chip->oob_poi + boffs, oob, bytes);
1881                         oob += bytes;
1882                 }
1883                 return oob;
1884         }
1885         default:
1886                 BUG();
1887         }
1888         return NULL;
1889 }
1890
1891 #define NOTALIGNED(x)   (x & (chip->subpagesize - 1)) != 0
1892
1893 /**
1894  * nand_do_write_ops - [Internal] NAND write with ECC
1895  * @mtd:        MTD device structure
1896  * @to:         offset to write to
1897  * @ops:        oob operations description structure
1898  *
1899  * NAND write with ECC
1900  */
1901 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1902                              struct mtd_oob_ops *ops)
1903 {
1904         int chipnr, realpage, page, blockmask, column;
1905         struct nand_chip *chip = mtd->priv;
1906         uint32_t writelen = ops->len;
1907         uint8_t *oob = ops->oobbuf;
1908         uint8_t *buf = ops->datbuf;
1909         int ret, subpage;
1910
1911         ops->retlen = 0;
1912         if (!writelen)
1913                 return 0;
1914
1915         /* reject writes, which are not page aligned */
1916         if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
1917                 printk(KERN_NOTICE "nand_write: "
1918                        "Attempt to write not page aligned data\n");
1919                 return -EINVAL;
1920         }
1921
1922         column = to & (mtd->writesize - 1);
1923         subpage = column || (writelen & (mtd->writesize - 1));
1924
1925         if (subpage && oob)
1926                 return -EINVAL;
1927
1928         chipnr = (int)(to >> chip->chip_shift);
1929         chip->select_chip(mtd, chipnr);
1930
1931         /* Check, if it is write protected */
1932         if (nand_check_wp(mtd)) {
1933                 printk (KERN_NOTICE "nand_do_write_ops: Device is write protected\n");
1934                 return -EIO;
1935         }
1936
1937         realpage = (int)(to >> chip->page_shift);
1938         page = realpage & chip->pagemask;
1939         blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1940
1941         /* Invalidate the page cache, when we write to the cached page */
1942         if (to <= (chip->pagebuf << chip->page_shift) &&
1943             (chip->pagebuf << chip->page_shift) < (to + ops->len))
1944                 chip->pagebuf = -1;
1945
1946         /* If we're not given explicit OOB data, let it be 0xFF */
1947         if (likely(!oob))
1948                 memset(chip->oob_poi, 0xff, mtd->oobsize);
1949
1950         while(1) {
1951                 int bytes = mtd->writesize;
1952                 int cached = writelen > bytes && page != blockmask;
1953                 uint8_t *wbuf = buf;
1954
1955                 /* Partial page write ? */
1956                 if (unlikely(column || writelen < (mtd->writesize - 1))) {
1957                         cached = 0;
1958                         bytes = min_t(int, bytes - column, (int) writelen);
1959                         chip->pagebuf = -1;
1960                         memset(chip->buffers->databuf, 0xff, mtd->writesize);
1961                         memcpy(&chip->buffers->databuf[column], buf, bytes);
1962                         wbuf = chip->buffers->databuf;
1963                 }
1964
1965                 if (unlikely(oob))
1966                         oob = nand_fill_oob(chip, oob, ops);
1967
1968                 ret = chip->write_page(mtd, chip, wbuf, page, cached,
1969                                        (ops->mode == MTD_OOB_RAW));
1970                 if (ret)
1971                         break;
1972
1973                 writelen -= bytes;
1974                 if (!writelen)
1975                         break;
1976
1977                 column = 0;
1978                 buf += bytes;
1979                 realpage++;
1980
1981                 page = realpage & chip->pagemask;
1982                 /* Check, if we cross a chip boundary */
1983                 if (!page) {
1984                         chipnr++;
1985                         chip->select_chip(mtd, -1);
1986                         chip->select_chip(mtd, chipnr);
1987                 }
1988         }
1989
1990         ops->retlen = ops->len - writelen;
1991         if (unlikely(oob))
1992                 ops->oobretlen = ops->ooblen;
1993         return ret;
1994 }
1995
1996 /**
1997  * nand_write - [MTD Interface] NAND write with ECC
1998  * @mtd:        MTD device structure
1999  * @to:         offset to write to
2000  * @len:        number of bytes to write
2001  * @retlen:     pointer to variable to store the number of written bytes
2002  * @buf:        the data to write
2003  *
2004  * NAND write with ECC
2005  */
2006 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2007                           size_t *retlen, const uint8_t *buf)
2008 {
2009         struct nand_chip *chip = mtd->priv;
2010         int ret;
2011
2012         /* Do not allow reads past end of device */
2013         if ((to + len) > mtd->size)
2014                 return -EINVAL;
2015         if (!len)
2016                 return 0;
2017
2018         nand_get_device(chip, mtd, FL_WRITING);
2019
2020         chip->ops.len = len;
2021         chip->ops.datbuf = (uint8_t *)buf;
2022         chip->ops.oobbuf = NULL;
2023
2024         ret = nand_do_write_ops(mtd, to, &chip->ops);
2025
2026         *retlen = chip->ops.retlen;
2027
2028         nand_release_device(mtd);
2029
2030         return ret;
2031 }
2032
2033 /**
2034  * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2035  * @mtd:        MTD device structure
2036  * @to:         offset to write to
2037  * @ops:        oob operation description structure
2038  *
2039  * NAND write out-of-band
2040  */
2041 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2042                              struct mtd_oob_ops *ops)
2043 {
2044         int chipnr, page, status, len;
2045         struct nand_chip *chip = mtd->priv;
2046
2047         MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n",
2048                   (unsigned int)to, (int)ops->ooblen);
2049
2050         if (ops->mode == MTD_OOB_AUTO)
2051                 len = chip->ecc.layout->oobavail;
2052         else
2053                 len = mtd->oobsize;
2054
2055         /* Do not allow write past end of page */
2056         if ((ops->ooboffs + ops->ooblen) > len) {
2057                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: "
2058                           "Attempt to write past end of page\n");
2059                 return -EINVAL;
2060         }
2061
2062         if (unlikely(ops->ooboffs >= len)) {
2063                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2064                           "Attempt to start write outside oob\n");
2065                 return -EINVAL;
2066         }
2067
2068         /* Do not allow reads past end of device */
2069         if (unlikely(to >= mtd->size ||
2070                      ops->ooboffs + ops->ooblen >
2071                         ((mtd->size >> chip->page_shift) -
2072                          (to >> chip->page_shift)) * len)) {
2073                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2074                           "Attempt write beyond end of device\n");
2075                 return -EINVAL;
2076         }
2077
2078         chipnr = (int)(to >> chip->chip_shift);
2079         chip->select_chip(mtd, chipnr);
2080
2081         /* Shift to get page */
2082         page = (int)(to >> chip->page_shift);
2083
2084         /*
2085          * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2086          * of my DiskOnChip 2000 test units) will clear the whole data page too
2087          * if we don't do this. I have no clue why, but I seem to have 'fixed'
2088          * it in the doc2000 driver in August 1999.  dwmw2.
2089          */
2090         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2091
2092         /* Check, if it is write protected */
2093         if (nand_check_wp(mtd))
2094                 return -EROFS;
2095
2096         /* Invalidate the page cache, if we write to the cached page */
2097         if (page == chip->pagebuf)
2098                 chip->pagebuf = -1;
2099
2100         memset(chip->oob_poi, 0xff, mtd->oobsize);
2101         nand_fill_oob(chip, ops->oobbuf, ops);
2102         status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2103         memset(chip->oob_poi, 0xff, mtd->oobsize);
2104
2105         if (status)
2106                 return status;
2107
2108         ops->oobretlen = ops->ooblen;
2109
2110         return 0;
2111 }
2112
2113 /**
2114  * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2115  * @mtd:        MTD device structure
2116  * @to:         offset to write to
2117  * @ops:        oob operation description structure
2118  */
2119 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2120                           struct mtd_oob_ops *ops)
2121 {
2122         struct nand_chip *chip = mtd->priv;
2123         int ret = -ENOTSUPP;
2124
2125         ops->retlen = 0;
2126
2127         /* Do not allow writes past end of device */
2128         if (ops->datbuf && (to + ops->len) > mtd->size) {
2129                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2130                           "Attempt read beyond end of device\n");
2131                 return -EINVAL;
2132         }
2133
2134         nand_get_device(chip, mtd, FL_WRITING);
2135
2136         switch(ops->mode) {
2137         case MTD_OOB_PLACE:
2138         case MTD_OOB_AUTO:
2139         case MTD_OOB_RAW:
2140                 break;
2141
2142         default:
2143                 goto out;
2144         }
2145
2146         if (!ops->datbuf)
2147                 ret = nand_do_write_oob(mtd, to, ops);
2148         else
2149                 ret = nand_do_write_ops(mtd, to, ops);
2150
2151  out:
2152         nand_release_device(mtd);
2153         return ret;
2154 }
2155
2156 /**
2157  * single_erease_cmd - [GENERIC] NAND standard block erase command function
2158  * @mtd:        MTD device structure
2159  * @page:       the page address of the block which will be erased
2160  *
2161  * Standard erase command for NAND chips
2162  */
2163 static void single_erase_cmd(struct mtd_info *mtd, int page)
2164 {
2165         struct nand_chip *chip = mtd->priv;
2166         /* Send commands to erase a block */
2167         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2168         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2169 }
2170
2171 /**
2172  * multi_erease_cmd - [GENERIC] AND specific block erase command function
2173  * @mtd:        MTD device structure
2174  * @page:       the page address of the block which will be erased
2175  *
2176  * AND multi block erase command function
2177  * Erase 4 consecutive blocks
2178  */
2179 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2180 {
2181         struct nand_chip *chip = mtd->priv;
2182         /* Send commands to erase a block */
2183         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2184         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2185         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2186         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2187         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2188 }
2189
2190 /**
2191  * nand_erase - [MTD Interface] erase block(s)
2192  * @mtd:        MTD device structure
2193  * @instr:      erase instruction
2194  *
2195  * Erase one ore more blocks
2196  */
2197 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2198 {
2199         return nand_erase_nand(mtd, instr, 0);
2200 }
2201
2202 #define BBT_PAGE_MASK   0xffffff3f
2203 /**
2204  * nand_erase_nand - [Internal] erase block(s)
2205  * @mtd:        MTD device structure
2206  * @instr:      erase instruction
2207  * @allowbbt:   allow erasing the bbt area
2208  *
2209  * Erase one ore more blocks
2210  */
2211 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2212                     int allowbbt)
2213 {
2214         int page, len, status, pages_per_block, ret, chipnr;
2215         struct nand_chip *chip = mtd->priv;
2216         int rewrite_bbt[CONFIG_SYS_NAND_MAX_CHIPS]={0};
2217         unsigned int bbt_masked_page = 0xffffffff;
2218
2219         MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n",
2220                   (unsigned int) instr->addr, (unsigned int) instr->len);
2221
2222         /* Start address must align on block boundary */
2223         if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
2224                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
2225                 return -EINVAL;
2226         }
2227
2228         /* Length must align on block boundary */
2229         if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
2230                 MTDDEBUG (MTD_DEBUG_LEVEL0,
2231                           "nand_erase: Length not block aligned\n");
2232                 return -EINVAL;
2233         }
2234
2235         /* Do not allow erase past end of device */
2236         if ((instr->len + instr->addr) > mtd->size) {
2237                 MTDDEBUG (MTD_DEBUG_LEVEL0,
2238                           "nand_erase: Erase past end of device\n");
2239                 return -EINVAL;
2240         }
2241
2242         instr->fail_addr = 0xffffffff;
2243
2244         /* Grab the lock and see if the device is available */
2245         nand_get_device(chip, mtd, FL_ERASING);
2246
2247         /* Shift to get first page */
2248         page = (int)(instr->addr >> chip->page_shift);
2249         chipnr = (int)(instr->addr >> chip->chip_shift);
2250
2251         /* Calculate pages in each block */
2252         pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2253
2254         /* Select the NAND device */
2255         chip->select_chip(mtd, chipnr);
2256
2257         /* Check, if it is write protected */
2258         if (nand_check_wp(mtd)) {
2259                 MTDDEBUG (MTD_DEBUG_LEVEL0,
2260                           "nand_erase: Device is write protected!!!\n");
2261                 instr->state = MTD_ERASE_FAILED;
2262                 goto erase_exit;
2263         }
2264
2265         /*
2266          * If BBT requires refresh, set the BBT page mask to see if the BBT
2267          * should be rewritten. Otherwise the mask is set to 0xffffffff which
2268          * can not be matched. This is also done when the bbt is actually
2269          * erased to avoid recusrsive updates
2270          */
2271         if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2272                 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2273
2274         /* Loop through the pages */
2275         len = instr->len;
2276
2277         instr->state = MTD_ERASING;
2278
2279         while (len) {
2280                 /*
2281                  * heck if we have a bad block, we do not erase bad blocks !
2282                  */
2283                 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2284                                         chip->page_shift, 0, allowbbt)) {
2285                         printk(KERN_WARNING "nand_erase: attempt to erase a "
2286                                "bad block at page 0x%08x\n", page);
2287                         instr->state = MTD_ERASE_FAILED;
2288                         goto erase_exit;
2289                 }
2290
2291                 /*
2292                  * Invalidate the page cache, if we erase the block which
2293                  * contains the current cached page
2294                  */
2295                 if (page <= chip->pagebuf && chip->pagebuf <
2296                     (page + pages_per_block))
2297                         chip->pagebuf = -1;
2298
2299                 chip->erase_cmd(mtd, page & chip->pagemask);
2300
2301                 status = chip->waitfunc(mtd, chip);
2302
2303                 /*
2304                  * See if operation failed and additional status checks are
2305                  * available
2306                  */
2307                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2308                         status = chip->errstat(mtd, chip, FL_ERASING,
2309                                                status, page);
2310
2311                 /* See if block erase succeeded */
2312                 if (status & NAND_STATUS_FAIL) {
2313                         MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: "
2314                                   "Failed erase, page 0x%08x\n", page);
2315                         instr->state = MTD_ERASE_FAILED;
2316                         instr->fail_addr = (page << chip->page_shift);
2317                         goto erase_exit;
2318                 }
2319
2320                 /*
2321                  * If BBT requires refresh, set the BBT rewrite flag to the
2322                  * page being erased
2323                  */
2324                 if (bbt_masked_page != 0xffffffff &&
2325                     (page & BBT_PAGE_MASK) == bbt_masked_page)
2326                             rewrite_bbt[chipnr] = (page << chip->page_shift);
2327
2328                 /* Increment page address and decrement length */
2329                 len -= (1 << chip->phys_erase_shift);
2330                 page += pages_per_block;
2331
2332                 /* Check, if we cross a chip boundary */
2333                 if (len && !(page & chip->pagemask)) {
2334                         chipnr++;
2335                         chip->select_chip(mtd, -1);
2336                         chip->select_chip(mtd, chipnr);
2337
2338                         /*
2339                          * If BBT requires refresh and BBT-PERCHIP, set the BBT
2340                          * page mask to see if this BBT should be rewritten
2341                          */
2342                         if (bbt_masked_page != 0xffffffff &&
2343                             (chip->bbt_td->options & NAND_BBT_PERCHIP))
2344                                 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2345                                         BBT_PAGE_MASK;
2346                 }
2347         }
2348         instr->state = MTD_ERASE_DONE;
2349
2350  erase_exit:
2351
2352         ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2353
2354         /* Deselect and wake up anyone waiting on the device */
2355         nand_release_device(mtd);
2356
2357         /* Do call back function */
2358         if (!ret)
2359                 mtd_erase_callback(instr);
2360
2361         /*
2362          * If BBT requires refresh and erase was successful, rewrite any
2363          * selected bad block tables
2364          */
2365         if (bbt_masked_page == 0xffffffff || ret)
2366                 return ret;
2367
2368         for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2369                 if (!rewrite_bbt[chipnr])
2370                         continue;
2371                 /* update the BBT for chip */
2372                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
2373                           "(%d:0x%0x 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
2374                           chip->bbt_td->pages[chipnr]);
2375                 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2376         }
2377
2378         /* Return more or less happy */
2379         return ret;
2380 }
2381
2382 /**
2383  * nand_sync - [MTD Interface] sync
2384  * @mtd:        MTD device structure
2385  *
2386  * Sync is actually a wait for chip ready function
2387  */
2388 static void nand_sync(struct mtd_info *mtd)
2389 {
2390         struct nand_chip *chip = mtd->priv;
2391
2392         MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_sync: called\n");
2393
2394         /* Grab the lock and see if the device is available */
2395         nand_get_device(chip, mtd, FL_SYNCING);
2396         /* Release it and go back */
2397         nand_release_device(mtd);
2398 }
2399
2400 /**
2401  * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2402  * @mtd:        MTD device structure
2403  * @offs:       offset relative to mtd start
2404  */
2405 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2406 {
2407         /* Check for invalid offset */
2408         if (offs > mtd->size)
2409                 return -EINVAL;
2410
2411         return nand_block_checkbad(mtd, offs, 1, 0);
2412 }
2413
2414 /**
2415  * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2416  * @mtd:        MTD device structure
2417  * @ofs:        offset relative to mtd start
2418  */
2419 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2420 {
2421         struct nand_chip *chip = mtd->priv;
2422         int ret;
2423
2424         if ((ret = nand_block_isbad(mtd, ofs))) {
2425                 /* If it was bad already, return success and do nothing. */
2426                 if (ret > 0)
2427                         return 0;
2428                 return ret;
2429         }
2430
2431         return chip->block_markbad(mtd, ofs);
2432 }
2433
2434 /**
2435  * nand_suspend - [MTD Interface] Suspend the NAND flash
2436  * @mtd:        MTD device structure
2437  */
2438 static int nand_suspend(struct mtd_info *mtd)
2439 {
2440         struct nand_chip *chip = mtd->priv;
2441
2442         return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2443 }
2444
2445 /**
2446  * nand_resume - [MTD Interface] Resume the NAND flash
2447  * @mtd:        MTD device structure
2448  */
2449 static void nand_resume(struct mtd_info *mtd)
2450 {
2451         struct nand_chip *chip = mtd->priv;
2452
2453         if (chip->state == FL_PM_SUSPENDED)
2454                 nand_release_device(mtd);
2455         else
2456                 printk(KERN_ERR "nand_resume() called for a chip which is not "
2457                        "in suspended state\n");
2458 }
2459
2460 /*
2461  * Set default functions
2462  */
2463 static void nand_set_defaults(struct nand_chip *chip, int busw)
2464 {
2465         /* check for proper chip_delay setup, set 20us if not */
2466         if (!chip->chip_delay)
2467                 chip->chip_delay = 20;
2468
2469         /* check, if a user supplied command function given */
2470         if (chip->cmdfunc == NULL)
2471                 chip->cmdfunc = nand_command;
2472
2473         /* check, if a user supplied wait function given */
2474         if (chip->waitfunc == NULL)
2475                 chip->waitfunc = nand_wait;
2476
2477         if (!chip->select_chip)
2478                 chip->select_chip = nand_select_chip;
2479         if (!chip->read_byte)
2480                 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2481         if (!chip->read_word)
2482                 chip->read_word = nand_read_word;
2483         if (!chip->block_bad)
2484                 chip->block_bad = nand_block_bad;
2485         if (!chip->block_markbad)
2486                 chip->block_markbad = nand_default_block_markbad;
2487         if (!chip->write_buf)
2488                 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2489         if (!chip->read_buf)
2490                 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2491         if (!chip->verify_buf)
2492                 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2493         if (!chip->scan_bbt)
2494                 chip->scan_bbt = nand_default_bbt;
2495
2496         if (!chip->controller) {
2497                 chip->controller = &chip->hwcontrol;
2498
2499                 /* XXX U-BOOT XXX */
2500 #if 0
2501                 spin_lock_init(&chip->controller->lock);
2502                 init_waitqueue_head(&chip->controller->wq);
2503 #endif
2504         }
2505
2506 }
2507
2508 /*
2509  * Get the flash and manufacturer id and lookup if the type is supported
2510  */
2511 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2512                                                   struct nand_chip *chip,
2513                                                   int busw, int *maf_id)
2514 {
2515         struct nand_flash_dev *type = NULL;
2516         int i, dev_id, maf_idx;
2517         int tmp_id, tmp_manf;
2518
2519         /* Select the device */
2520         chip->select_chip(mtd, 0);
2521
2522         /*
2523          * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2524          * after power-up
2525          */
2526         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2527
2528         /* Send the command for reading device ID */
2529         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2530
2531         /* Read manufacturer and device IDs */
2532         *maf_id = chip->read_byte(mtd);
2533         dev_id = chip->read_byte(mtd);
2534
2535         /* Try again to make sure, as some systems the bus-hold or other
2536          * interface concerns can cause random data which looks like a
2537          * possibly credible NAND flash to appear. If the two results do
2538          * not match, ignore the device completely.
2539          */
2540
2541         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2542
2543         /* Read manufacturer and device IDs */
2544
2545         tmp_manf = chip->read_byte(mtd);
2546         tmp_id = chip->read_byte(mtd);
2547
2548         if (tmp_manf != *maf_id || tmp_id != dev_id) {
2549                 printk(KERN_INFO "%s: second ID read did not match "
2550                        "%02x,%02x against %02x,%02x\n", __func__,
2551                        *maf_id, dev_id, tmp_manf, tmp_id);
2552                 return ERR_PTR(-ENODEV);
2553         }
2554
2555         /* Lookup the flash id */
2556         for (i = 0; nand_flash_ids[i].name != NULL; i++) {
2557                 if (dev_id == nand_flash_ids[i].id) {
2558                         type =  &nand_flash_ids[i];
2559                         break;
2560                 }
2561         }
2562
2563         if (!type)
2564                 return ERR_PTR(-ENODEV);
2565
2566         if (!mtd->name)
2567                 mtd->name = type->name;
2568
2569         chip->chipsize = type->chipsize << 20;
2570
2571         /* Newer devices have all the information in additional id bytes */
2572         if (!type->pagesize) {
2573                 int extid;
2574                 /* The 3rd id byte holds MLC / multichip data */
2575                 chip->cellinfo = chip->read_byte(mtd);
2576                 /* The 4th id byte is the important one */
2577                 extid = chip->read_byte(mtd);
2578                 /* Calc pagesize */
2579                 mtd->writesize = 1024 << (extid & 0x3);
2580                 extid >>= 2;
2581                 /* Calc oobsize */
2582                 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
2583                 extid >>= 2;
2584                 /* Calc blocksize. Blocksize is multiples of 64KiB */
2585                 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2586                 extid >>= 2;
2587                 /* Get buswidth information */
2588                 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2589
2590         } else {
2591                 /*
2592                  * Old devices have chip data hardcoded in the device id table
2593                  */
2594                 mtd->erasesize = type->erasesize;
2595                 mtd->writesize = type->pagesize;
2596                 mtd->oobsize = mtd->writesize / 32;
2597                 busw = type->options & NAND_BUSWIDTH_16;
2598         }
2599
2600         /* Try to identify manufacturer */
2601         for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2602                 if (nand_manuf_ids[maf_idx].id == *maf_id)
2603                         break;
2604         }
2605
2606         /*
2607          * Check, if buswidth is correct. Hardware drivers should set
2608          * chip correct !
2609          */
2610         if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2611                 printk(KERN_INFO "NAND device: Manufacturer ID:"
2612                        " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2613                        dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2614                 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2615                        (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2616                        busw ? 16 : 8);
2617                 return ERR_PTR(-EINVAL);
2618         }
2619
2620         /* Calculate the address shift from the page size */
2621         chip->page_shift = ffs(mtd->writesize) - 1;
2622         /* Convert chipsize to number of pages per chip -1. */
2623         chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2624
2625         chip->bbt_erase_shift = chip->phys_erase_shift =
2626                 ffs(mtd->erasesize) - 1;
2627         chip->chip_shift = ffs(chip->chipsize) - 1;
2628
2629         /* Set the bad block position */
2630         chip->badblockpos = mtd->writesize > 512 ?
2631                 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2632
2633         /* Get chip options, preserve non chip based options */
2634         chip->options &= ~NAND_CHIPOPTIONS_MSK;
2635         chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
2636
2637         /*
2638          * Set chip as a default. Board drivers can override it, if necessary
2639          */
2640         chip->options |= NAND_NO_AUTOINCR;
2641
2642         /* Check if chip is a not a samsung device. Do not clear the
2643          * options for chips which are not having an extended id.
2644          */
2645         if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2646                 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2647
2648         /* Check for AND chips with 4 page planes */
2649         if (chip->options & NAND_4PAGE_ARRAY)
2650                 chip->erase_cmd = multi_erase_cmd;
2651         else
2652                 chip->erase_cmd = single_erase_cmd;
2653
2654         /* Do not replace user supplied command function ! */
2655         if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2656                 chip->cmdfunc = nand_command_lp;
2657
2658         MTDDEBUG (MTD_DEBUG_LEVEL0, "NAND device: Manufacturer ID:"
2659                   " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2660                   nand_manuf_ids[maf_idx].name, type->name);
2661
2662         return type;
2663 }
2664
2665 /**
2666  * nand_scan_ident - [NAND Interface] Scan for the NAND device
2667  * @mtd:             MTD device structure
2668  * @maxchips:        Number of chips to scan for
2669  *
2670  * This is the first phase of the normal nand_scan() function. It
2671  * reads the flash ID and sets up MTD fields accordingly.
2672  *
2673  * The mtd->owner field must be set to the module of the caller.
2674  */
2675 int nand_scan_ident(struct mtd_info *mtd, int maxchips)
2676 {
2677         int i, busw, nand_maf_id;
2678         struct nand_chip *chip = mtd->priv;
2679         struct nand_flash_dev *type;
2680
2681         /* Get buswidth to select the correct functions */
2682         busw = chip->options & NAND_BUSWIDTH_16;
2683         /* Set the default functions */
2684         nand_set_defaults(chip, busw);
2685
2686         /* Read the flash type */
2687         type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
2688
2689         if (IS_ERR(type)) {
2690 #ifndef CONFIG_SYS_NAND_QUIET_TEST
2691                 printk(KERN_WARNING "No NAND device found!!!\n");
2692 #endif
2693                 chip->select_chip(mtd, -1);
2694                 return PTR_ERR(type);
2695         }
2696
2697         /* Check for a chip array */
2698         for (i = 1; i < maxchips; i++) {
2699                 chip->select_chip(mtd, i);
2700                 /* See comment in nand_get_flash_type for reset */
2701                 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2702                 /* Send the command for reading device ID */
2703                 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2704                 /* Read manufacturer and device IDs */
2705                 if (nand_maf_id != chip->read_byte(mtd) ||
2706                     type->id != chip->read_byte(mtd))
2707                         break;
2708         }
2709 #ifdef DEBUG
2710         if (i > 1)
2711                 printk(KERN_INFO "%d NAND chips detected\n", i);
2712 #endif
2713
2714         /* Store the number of chips and calc total size for mtd */
2715         chip->numchips = i;
2716         mtd->size = i * chip->chipsize;
2717
2718         return 0;
2719 }
2720
2721
2722 /**
2723  * nand_scan_tail - [NAND Interface] Scan for the NAND device
2724  * @mtd:            MTD device structure
2725  * @maxchips:       Number of chips to scan for
2726  *
2727  * This is the second phase of the normal nand_scan() function. It
2728  * fills out all the uninitialized function pointers with the defaults
2729  * and scans for a bad block table if appropriate.
2730  */
2731 int nand_scan_tail(struct mtd_info *mtd)
2732 {
2733         int i;
2734         struct nand_chip *chip = mtd->priv;
2735
2736         if (!(chip->options & NAND_OWN_BUFFERS))
2737                 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2738         if (!chip->buffers)
2739                 return -ENOMEM;
2740
2741         /* Set the internal oob buffer location, just after the page data */
2742         chip->oob_poi = chip->buffers->databuf + mtd->writesize;
2743
2744         /*
2745          * If no default placement scheme is given, select an appropriate one
2746          */
2747         if (!chip->ecc.layout) {
2748                 switch (mtd->oobsize) {
2749                 case 8:
2750                         chip->ecc.layout = &nand_oob_8;
2751                         break;
2752                 case 16:
2753                         chip->ecc.layout = &nand_oob_16;
2754                         break;
2755                 case 64:
2756                         chip->ecc.layout = &nand_oob_64;
2757                         break;
2758                 case 128:
2759                         chip->ecc.layout = &nand_oob_128;
2760                         break;
2761                 default:
2762                         printk(KERN_WARNING "No oob scheme defined for "
2763                                "oobsize %d\n", mtd->oobsize);
2764 /*                      BUG(); */
2765                 }
2766         }
2767
2768         if (!chip->write_page)
2769                 chip->write_page = nand_write_page;
2770
2771         /*
2772          * check ECC mode, default to software if 3byte/512byte hardware ECC is
2773          * selected and we have 256 byte pagesize fallback to software ECC
2774          */
2775         if (!chip->ecc.read_page_raw)
2776                 chip->ecc.read_page_raw = nand_read_page_raw;
2777         if (!chip->ecc.write_page_raw)
2778                 chip->ecc.write_page_raw = nand_write_page_raw;
2779
2780         switch (chip->ecc.mode) {
2781         case NAND_ECC_HW_OOB_FIRST:
2782                 /* Similar to NAND_ECC_HW, but a separate read_page handle */
2783                 if (!chip->ecc.calculate || !chip->ecc.correct ||
2784                      !chip->ecc.hwctl) {
2785                         printk(KERN_WARNING "No ECC functions supplied, "
2786                                "Hardware ECC not possible\n");
2787                         BUG();
2788                 }
2789                 if (!chip->ecc.read_page)
2790                         chip->ecc.read_page = nand_read_page_hwecc_oob_first;
2791
2792         case NAND_ECC_HW:
2793                 /* Use standard hwecc read page function ? */
2794                 if (!chip->ecc.read_page)
2795                         chip->ecc.read_page = nand_read_page_hwecc;
2796                 if (!chip->ecc.write_page)
2797                         chip->ecc.write_page = nand_write_page_hwecc;
2798                 if (!chip->ecc.read_oob)
2799                         chip->ecc.read_oob = nand_read_oob_std;
2800                 if (!chip->ecc.write_oob)
2801                         chip->ecc.write_oob = nand_write_oob_std;
2802
2803         case NAND_ECC_HW_SYNDROME:
2804                 if ((!chip->ecc.calculate || !chip->ecc.correct ||
2805                      !chip->ecc.hwctl) &&
2806                     (!chip->ecc.read_page ||
2807                      chip->ecc.read_page == nand_read_page_hwecc ||
2808                      !chip->ecc.write_page ||
2809                      chip->ecc.write_page == nand_write_page_hwecc)) {
2810                         printk(KERN_WARNING "No ECC functions supplied, "
2811                                "Hardware ECC not possible\n");
2812                         BUG();
2813                 }
2814                 /* Use standard syndrome read/write page function ? */
2815                 if (!chip->ecc.read_page)
2816                         chip->ecc.read_page = nand_read_page_syndrome;
2817                 if (!chip->ecc.write_page)
2818                         chip->ecc.write_page = nand_write_page_syndrome;
2819                 if (!chip->ecc.read_oob)
2820                         chip->ecc.read_oob = nand_read_oob_syndrome;
2821                 if (!chip->ecc.write_oob)
2822                         chip->ecc.write_oob = nand_write_oob_syndrome;
2823
2824                 if (mtd->writesize >= chip->ecc.size)
2825                         break;
2826                 printk(KERN_WARNING "%d byte HW ECC not possible on "
2827                        "%d byte page size, fallback to SW ECC\n",
2828                        chip->ecc.size, mtd->writesize);
2829                 chip->ecc.mode = NAND_ECC_SOFT;
2830
2831         case NAND_ECC_SOFT:
2832                 chip->ecc.calculate = nand_calculate_ecc;
2833                 chip->ecc.correct = nand_correct_data;
2834                 chip->ecc.read_page = nand_read_page_swecc;
2835                 chip->ecc.read_subpage = nand_read_subpage;
2836                 chip->ecc.write_page = nand_write_page_swecc;
2837                 chip->ecc.read_oob = nand_read_oob_std;
2838                 chip->ecc.write_oob = nand_write_oob_std;
2839                 chip->ecc.size = 256;
2840                 chip->ecc.bytes = 3;
2841                 break;
2842
2843         case NAND_ECC_NONE:
2844                 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2845                        "This is not recommended !!\n");
2846                 chip->ecc.read_page = nand_read_page_raw;
2847                 chip->ecc.write_page = nand_write_page_raw;
2848                 chip->ecc.read_oob = nand_read_oob_std;
2849                 chip->ecc.write_oob = nand_write_oob_std;
2850                 chip->ecc.size = mtd->writesize;
2851                 chip->ecc.bytes = 0;
2852                 break;
2853
2854         default:
2855                 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
2856                        chip->ecc.mode);
2857                 BUG();
2858         }
2859
2860         /*
2861          * The number of bytes available for a client to place data into
2862          * the out of band area
2863          */
2864         chip->ecc.layout->oobavail = 0;
2865         for (i = 0; chip->ecc.layout->oobfree[i].length; i++)
2866                 chip->ecc.layout->oobavail +=
2867                         chip->ecc.layout->oobfree[i].length;
2868         mtd->oobavail = chip->ecc.layout->oobavail;
2869
2870         /*
2871          * Set the number of read / write steps for one page depending on ECC
2872          * mode
2873          */
2874         chip->ecc.steps = mtd->writesize / chip->ecc.size;
2875         if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
2876                 printk(KERN_WARNING "Invalid ecc parameters\n");
2877                 BUG();
2878         }
2879         chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
2880
2881         /*
2882          * Allow subpage writes up to ecc.steps. Not possible for MLC
2883          * FLASH.
2884          */
2885         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2886             !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
2887                 switch(chip->ecc.steps) {
2888                 case 2:
2889                         mtd->subpage_sft = 1;
2890                         break;
2891                 case 4:
2892                 case 8:
2893                         mtd->subpage_sft = 2;
2894                         break;
2895                 }
2896         }
2897         chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
2898
2899         /* Initialize state */
2900         chip->state = FL_READY;
2901
2902         /* De-select the device */
2903         chip->select_chip(mtd, -1);
2904
2905         /* Invalidate the pagebuffer reference */
2906         chip->pagebuf = -1;
2907
2908         /* Fill in remaining MTD driver data */
2909         mtd->type = MTD_NANDFLASH;
2910         mtd->flags = MTD_CAP_NANDFLASH;
2911         mtd->erase = nand_erase;
2912         mtd->point = NULL;
2913         mtd->unpoint = NULL;
2914         mtd->read = nand_read;
2915         mtd->write = nand_write;
2916         mtd->read_oob = nand_read_oob;
2917         mtd->write_oob = nand_write_oob;
2918         mtd->sync = nand_sync;
2919         mtd->lock = NULL;
2920         mtd->unlock = NULL;
2921         mtd->suspend = nand_suspend;
2922         mtd->resume = nand_resume;
2923         mtd->block_isbad = nand_block_isbad;
2924         mtd->block_markbad = nand_block_markbad;
2925
2926         /* propagate ecc.layout to mtd_info */
2927         mtd->ecclayout = chip->ecc.layout;
2928
2929         /* Check, if we should skip the bad block table scan */
2930         if (chip->options & NAND_SKIP_BBTSCAN)
2931                 chip->options |= NAND_BBT_SCANNED;
2932
2933         return 0;
2934 }
2935
2936 /* module_text_address() isn't exported, and it's mostly a pointless
2937    test if this is a module _anyway_ -- they'd have to try _really_ hard
2938    to call us from in-kernel code if the core NAND support is modular. */
2939 #ifdef MODULE
2940 #define caller_is_module() (1)
2941 #else
2942 #define caller_is_module() \
2943         module_text_address((unsigned long)__builtin_return_address(0))
2944 #endif
2945
2946 /**
2947  * nand_scan - [NAND Interface] Scan for the NAND device
2948  * @mtd:        MTD device structure
2949  * @maxchips:   Number of chips to scan for
2950  *
2951  * This fills out all the uninitialized function pointers
2952  * with the defaults.
2953  * The flash ID is read and the mtd/chip structures are
2954  * filled with the appropriate values.
2955  * The mtd->owner field must be set to the module of the caller
2956  *
2957  */
2958 int nand_scan(struct mtd_info *mtd, int maxchips)
2959 {
2960         int ret;
2961
2962         /* Many callers got this wrong, so check for it for a while... */
2963         /* XXX U-BOOT XXX */
2964 #if 0
2965         if (!mtd->owner && caller_is_module()) {
2966                 printk(KERN_CRIT "nand_scan() called with NULL mtd->owner!\n");
2967                 BUG();
2968         }
2969 #endif
2970
2971         ret = nand_scan_ident(mtd, maxchips);
2972         if (!ret)
2973                 ret = nand_scan_tail(mtd);
2974         return ret;
2975 }
2976
2977 /**
2978  * nand_release - [NAND Interface] Free resources held by the NAND device
2979  * @mtd:        MTD device structure
2980 */
2981 void nand_release(struct mtd_info *mtd)
2982 {
2983         struct nand_chip *chip = mtd->priv;
2984
2985 #ifdef CONFIG_MTD_PARTITIONS
2986         /* Deregister partitions */
2987         del_mtd_partitions(mtd);
2988 #endif
2989         /* Deregister the device */
2990         /* XXX U-BOOT XXX */
2991 #if 0
2992         del_mtd_device(mtd);
2993 #endif
2994
2995         /* Free bad block table memory */
2996         kfree(chip->bbt);
2997         if (!(chip->options & NAND_OWN_BUFFERS))
2998                 kfree(chip->buffers);
2999 }
3000
3001 /* XXX U-BOOT XXX */
3002 #if 0
3003 EXPORT_SYMBOL_GPL(nand_scan);
3004 EXPORT_SYMBOL_GPL(nand_scan_ident);
3005 EXPORT_SYMBOL_GPL(nand_scan_tail);
3006 EXPORT_SYMBOL_GPL(nand_release);
3007
3008 static int __init nand_base_init(void)
3009 {
3010         led_trigger_register_simple("nand-disk", &nand_led_trigger);
3011         return 0;
3012 }
3013
3014 static void __exit nand_base_exit(void)
3015 {
3016         led_trigger_unregister_simple(nand_led_trigger);
3017 }
3018
3019 module_init(nand_base_init);
3020 module_exit(nand_base_exit);
3021
3022 MODULE_LICENSE("GPL");
3023 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
3024 MODULE_DESCRIPTION("Generic NAND flash driver code");
3025 #endif