2 * Copyright 2004-2007 Freescale Semiconductor, Inc.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 * Copyright 2009 Ilya Yanok, <yanok@emcraft.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
23 #include <linux/err.h>
25 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35)
26 #include <asm/arch/imx-regs.h>
30 #define DRIVER_NAME "mxc_nand"
32 typedef enum {false, true} bool;
34 struct mxc_nand_host {
36 struct nand_chip *nand;
38 struct fsl_nfc_regs __iomem *regs;
44 unsigned int page_addr;
47 static struct mxc_nand_host mxc_host;
48 static struct mxc_nand_host *host = &mxc_host;
50 /* Define delays in microsec for NAND device operations */
51 #define TROP_US_DELAY 2000
52 /* Macros to get byte and bit positions of ECC */
53 #define COLPOS(x) ((x) >> 3)
54 #define BITPOS(x) ((x) & 0xf)
56 /* Define single bit Error positions in Main & Spare area */
57 #define MAIN_SINGLEBIT_ERROR 0x4
58 #define SPARE_SINGLEBIT_ERROR 0x1
60 /* OOB placement block for use with hardware ecc generation */
61 #if defined(MXC_NFC_V1)
62 #ifndef CONFIG_SYS_NAND_LARGEPAGE
63 static struct nand_ecclayout nand_hw_eccoob = {
65 .eccpos = {6, 7, 8, 9, 10},
66 .oobfree = { {0, 5}, {11, 5}, }
69 static struct nand_ecclayout nand_hw_eccoob2k = {
77 .oobfree = { {2, 4}, {11, 11}, {27, 11}, {43, 11}, {59, 5} },
80 #elif defined(MXC_NFC_V2_1)
81 #ifndef CONFIG_SYS_NAND_LARGEPAGE
82 static struct nand_ecclayout nand_hw_eccoob = {
84 .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15},
88 static struct nand_ecclayout nand_hw_eccoob2k = {
91 7, 8, 9, 10, 11, 12, 13, 14, 15,
92 23, 24, 25, 26, 27, 28, 29, 30, 31,
93 39, 40, 41, 42, 43, 44, 45, 46, 47,
94 55, 56, 57, 58, 59, 60, 61, 62, 63,
96 .oobfree = { {2, 5}, {16, 7}, {32, 7}, {48, 7} },
101 static int is_16bit_nand(void)
103 #if defined(CONFIG_SYS_NAND_BUSWIDTH_16BIT)
110 static uint32_t *mxc_nand_memcpy32(uint32_t *dest, uint32_t *source, size_t size)
116 __raw_writel(__raw_readl(source++), d++);
121 * This function polls the NANDFC to wait for the basic operation to
122 * complete by checking the INT bit of config2 register.
124 static void wait_op_done(struct mxc_nand_host *host, int max_retries,
129 while (max_retries-- > 0) {
130 if (readw(&host->regs->config2) & NFC_INT) {
131 tmp = readw(&host->regs->config2);
133 writew(tmp, &host->regs->config2);
138 if (max_retries < 0) {
139 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s(%d): INT not set\n",
145 * This function issues the specified command to the NAND device and
146 * waits for completion.
148 static void send_cmd(struct mxc_nand_host *host, uint16_t cmd)
150 MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x)\n", cmd);
152 writew(cmd, &host->regs->flash_cmd);
153 writew(NFC_CMD, &host->regs->config2);
155 /* Wait for operation to complete */
156 wait_op_done(host, TROP_US_DELAY, cmd);
160 * This function sends an address (or partial address) to the
161 * NAND device. The address is used to select the source/destination for
164 static void send_addr(struct mxc_nand_host *host, uint16_t addr)
166 MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x)\n", addr);
168 writew(addr, &host->regs->flash_addr);
169 writew(NFC_ADDR, &host->regs->config2);
171 /* Wait for operation to complete */
172 wait_op_done(host, TROP_US_DELAY, addr);
176 * This function requests the NANDFC to initiate the transfer
177 * of data currently in the NANDFC RAM buffer to the NAND device.
179 static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id,
183 MTDDEBUG(MTD_DEBUG_LEVEL1, "send_prog_page (%d)\n", spare_only);
185 if (is_mxc_nfc_21()) {
188 * The controller copies the 64 bytes of spare data from
189 * the first 16 bytes of each of the 4 64 byte spare buffers.
190 * Copy the contiguous data starting in spare_area[0] to
191 * the four spare area buffers.
193 for (i = 1; i < 4; i++) {
194 void __iomem *src = &host->regs->spare_area[0][i * 16];
195 void __iomem *dst = &host->regs->spare_area[i][0];
197 mxc_nand_memcpy32(dst, src, 16);
201 writew(buf_id, &host->regs->buf_addr);
203 /* Configure spare or page+spare access */
204 if (!host->pagesize_2k) {
205 uint16_t config1 = readw(&host->regs->config1);
207 config1 |= NFC_SP_EN;
209 config1 &= ~NFC_SP_EN;
210 writew(config1, &host->regs->config1);
213 writew(NFC_INPUT, &host->regs->config2);
215 /* Wait for operation to complete */
216 wait_op_done(host, TROP_US_DELAY, spare_only);
220 * Requests NANDFC to initiate the transfer of data from the
221 * NAND device into in the NANDFC ram buffer.
223 static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id,
226 MTDDEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only);
228 writew(buf_id, &host->regs->buf_addr);
230 /* Configure spare or page+spare access */
231 if (!host->pagesize_2k) {
232 uint32_t config1 = readw(&host->regs->config1);
234 config1 |= NFC_SP_EN;
236 config1 &= ~NFC_SP_EN;
237 writew(config1, &host->regs->config1);
240 writew(NFC_OUTPUT, &host->regs->config2);
242 /* Wait for operation to complete */
243 wait_op_done(host, TROP_US_DELAY, spare_only);
245 if (is_mxc_nfc_21()) {
249 * The controller copies the 64 bytes of spare data to
250 * the first 16 bytes of each of the 4 spare buffers.
251 * Make the data contiguous starting in spare_area[0].
253 for (i = 1; i < 4; i++) {
254 void __iomem *src = &host->regs->spare_area[i][0];
255 void __iomem *dst = &host->regs->spare_area[0][i * 16];
257 mxc_nand_memcpy32(dst, src, 16);
262 /* Request the NANDFC to perform a read of the NAND device ID. */
263 static void send_read_id(struct mxc_nand_host *host)
267 /* NANDFC buffer 0 is used for device ID output */
268 writew(0x0, &host->regs->buf_addr);
270 /* Read ID into main buffer */
271 tmp = readw(&host->regs->config1);
273 writew(tmp, &host->regs->config1);
275 writew(NFC_ID, &host->regs->config2);
277 /* Wait for operation to complete */
278 wait_op_done(host, TROP_US_DELAY, 0);
282 * This function requests the NANDFC to perform a read of the
283 * NAND device status and returns the current status.
285 static uint16_t get_dev_status(struct mxc_nand_host *host)
287 void __iomem *main_buf = host->regs->main_area[1];
290 /* Issue status request to NAND device */
292 /* store the main area1 first word, later do recovery */
293 store = readl(main_buf);
294 /* NANDFC buffer 1 is used for device status */
295 writew(1, &host->regs->buf_addr);
297 /* Read status into main buffer */
298 tmp = readw(&host->regs->config1);
300 writew(tmp, &host->regs->config1);
302 writew(NFC_STATUS, &host->regs->config2);
304 /* Wait for operation to complete */
305 wait_op_done(host, TROP_US_DELAY, 0);
308 * Status is placed in first word of main buffer
309 * get status, then recovery area 1 data
311 ret = readw(main_buf);
312 writel(store, main_buf);
317 /* This function is used by upper layer to checks if device is ready */
318 static int mxc_nand_dev_ready(struct mtd_info *mtd)
321 * NFC handles R/B internally. Therefore, this function
322 * always returns status as ready.
327 static void _mxc_nand_enable_hwecc(struct mtd_info *mtd, int on)
329 struct nand_chip *nand_chip = mtd->priv;
330 struct mxc_nand_host *host = nand_chip->priv;
331 uint16_t tmp = readw(&host->regs->config1);
337 writew(tmp, &host->regs->config1);
340 #ifdef CONFIG_MXC_NAND_HWECC
341 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
344 * If HW ECC is enabled, we turn it on during init. There is
345 * no need to enable again here.
350 static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd,
351 struct nand_chip *chip,
352 int page, int sndcmd)
354 struct mxc_nand_host *host = chip->priv;
355 uint8_t *buf = chip->oob_poi;
356 int length = mtd->oobsize;
357 int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
358 uint8_t *bufpoi = buf;
361 MTDDEBUG(MTD_DEBUG_LEVEL0,
362 "%s: Reading OOB area of page %u to oob %p\n",
363 __FUNCTION__, host->page_addr, buf);
365 chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page);
366 for (i = 0; i < chip->ecc.steps; i++) {
367 toread = min_t(int, length, chip->ecc.prepad);
369 chip->read_buf(mtd, bufpoi, toread);
373 bufpoi += chip->ecc.bytes;
374 host->col_addr += chip->ecc.bytes;
375 length -= chip->ecc.bytes;
377 toread = min_t(int, length, chip->ecc.postpad);
379 chip->read_buf(mtd, bufpoi, toread);
385 chip->read_buf(mtd, bufpoi, length);
387 _mxc_nand_enable_hwecc(mtd, 0);
388 chip->cmdfunc(mtd, NAND_CMD_READOOB,
389 mtd->writesize + chip->ecc.prepad, page);
390 bufpoi = buf + chip->ecc.prepad;
391 length = mtd->oobsize - chip->ecc.prepad;
392 for (i = 0; i < chip->ecc.steps; i++) {
393 toread = min_t(int, length, chip->ecc.bytes);
394 chip->read_buf(mtd, bufpoi, toread);
397 host->col_addr += chip->ecc.postpad + chip->ecc.prepad;
399 _mxc_nand_enable_hwecc(mtd, 1);
403 static int mxc_nand_read_page_raw_syndrome(struct mtd_info *mtd,
404 struct nand_chip *chip,
408 struct mxc_nand_host *host = chip->priv;
409 int eccsize = chip->ecc.size;
410 int eccbytes = chip->ecc.bytes;
411 int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
412 uint8_t *oob = chip->oob_poi;
416 _mxc_nand_enable_hwecc(mtd, 0);
417 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, host->page_addr);
419 for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
420 host->col_addr = n * eccsize;
421 chip->read_buf(mtd, buf, eccsize);
424 host->col_addr = mtd->writesize + n * eccpitch;
425 if (chip->ecc.prepad) {
426 chip->read_buf(mtd, oob, chip->ecc.prepad);
427 oob += chip->ecc.prepad;
430 chip->read_buf(mtd, oob, eccbytes);
433 if (chip->ecc.postpad) {
434 chip->read_buf(mtd, oob, chip->ecc.postpad);
435 oob += chip->ecc.postpad;
439 size = mtd->oobsize - (oob - chip->oob_poi);
441 chip->read_buf(mtd, oob, size);
442 _mxc_nand_enable_hwecc(mtd, 1);
447 static int mxc_nand_read_page_syndrome(struct mtd_info *mtd,
448 struct nand_chip *chip,
452 struct mxc_nand_host *host = chip->priv;
453 int n, eccsize = chip->ecc.size;
454 int eccbytes = chip->ecc.bytes;
455 int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
456 int eccsteps = chip->ecc.steps;
458 uint8_t *oob = chip->oob_poi;
460 MTDDEBUG(MTD_DEBUG_LEVEL1, "Reading page %u to buf %p oob %p\n",
461 host->page_addr, buf, oob);
463 /* first read the data area and the available portion of OOB */
464 for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
467 host->col_addr = n * eccsize;
469 chip->read_buf(mtd, p, eccsize);
471 host->col_addr = mtd->writesize + n * eccpitch;
473 if (chip->ecc.prepad) {
474 chip->read_buf(mtd, oob, chip->ecc.prepad);
475 oob += chip->ecc.prepad;
478 stat = chip->ecc.correct(mtd, p, oob, NULL);
481 mtd->ecc_stats.failed++;
483 mtd->ecc_stats.corrected += stat;
486 if (chip->ecc.postpad) {
487 chip->read_buf(mtd, oob, chip->ecc.postpad);
488 oob += chip->ecc.postpad;
492 /* Calculate remaining oob bytes */
493 n = mtd->oobsize - (oob - chip->oob_poi);
495 chip->read_buf(mtd, oob, n);
497 /* Then switch ECC off and read the OOB area to get the ECC code */
498 _mxc_nand_enable_hwecc(mtd, 0);
499 chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, host->page_addr);
500 eccsteps = chip->ecc.steps;
501 oob = chip->oob_poi + chip->ecc.prepad;
502 for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
503 host->col_addr = mtd->writesize +
506 chip->read_buf(mtd, oob, eccbytes);
507 oob += eccbytes + chip->ecc.postpad;
509 _mxc_nand_enable_hwecc(mtd, 1);
513 static int mxc_nand_write_oob_syndrome(struct mtd_info *mtd,
514 struct nand_chip *chip, int page)
516 struct mxc_nand_host *host = chip->priv;
517 int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
518 int length = mtd->oobsize;
519 int i, len, status, steps = chip->ecc.steps;
520 const uint8_t *bufpoi = chip->oob_poi;
522 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
523 for (i = 0; i < steps; i++) {
524 len = min_t(int, length, eccpitch);
526 chip->write_buf(mtd, bufpoi, len);
529 host->col_addr += chip->ecc.prepad + chip->ecc.postpad;
532 chip->write_buf(mtd, bufpoi, length);
534 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
535 status = chip->waitfunc(mtd, chip);
536 return status & NAND_STATUS_FAIL ? -EIO : 0;
539 static void mxc_nand_write_page_raw_syndrome(struct mtd_info *mtd,
540 struct nand_chip *chip,
543 struct mxc_nand_host *host = chip->priv;
544 int eccsize = chip->ecc.size;
545 int eccbytes = chip->ecc.bytes;
546 int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
547 uint8_t *oob = chip->oob_poi;
551 for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
552 host->col_addr = n * eccsize;
553 chip->write_buf(mtd, buf, eccsize);
556 host->col_addr = mtd->writesize + n * eccpitch;
558 if (chip->ecc.prepad) {
559 chip->write_buf(mtd, oob, chip->ecc.prepad);
560 oob += chip->ecc.prepad;
563 host->col_addr += eccbytes;
566 if (chip->ecc.postpad) {
567 chip->write_buf(mtd, oob, chip->ecc.postpad);
568 oob += chip->ecc.postpad;
572 size = mtd->oobsize - (oob - chip->oob_poi);
574 chip->write_buf(mtd, oob, size);
577 static void mxc_nand_write_page_syndrome(struct mtd_info *mtd,
578 struct nand_chip *chip,
581 struct mxc_nand_host *host = chip->priv;
582 int i, n, eccsize = chip->ecc.size;
583 int eccbytes = chip->ecc.bytes;
584 int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
585 int eccsteps = chip->ecc.steps;
586 const uint8_t *p = buf;
587 uint8_t *oob = chip->oob_poi;
589 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
593 n++, eccsteps--, i += eccbytes, p += eccsize) {
594 host->col_addr = n * eccsize;
596 chip->write_buf(mtd, p, eccsize);
598 host->col_addr = mtd->writesize + n * eccpitch;
600 if (chip->ecc.prepad) {
601 chip->write_buf(mtd, oob, chip->ecc.prepad);
602 oob += chip->ecc.prepad;
605 chip->write_buf(mtd, oob, eccbytes);
608 if (chip->ecc.postpad) {
609 chip->write_buf(mtd, oob, chip->ecc.postpad);
610 oob += chip->ecc.postpad;
614 /* Calculate remaining oob bytes */
615 i = mtd->oobsize - (oob - chip->oob_poi);
617 chip->write_buf(mtd, oob, i);
620 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
621 u_char *read_ecc, u_char *calc_ecc)
623 struct nand_chip *nand_chip = mtd->priv;
624 struct mxc_nand_host *host = nand_chip->priv;
625 uint32_t ecc_status = readl(&host->regs->ecc_status_result);
626 int subpages = mtd->writesize / nand_chip->subpagesize;
627 int pg2blk_shift = nand_chip->phys_erase_shift -
628 nand_chip->page_shift;
631 if ((ecc_status & 0xf) > 4) {
632 static int last_bad = -1;
634 if (last_bad != host->page_addr >> pg2blk_shift) {
635 last_bad = host->page_addr >> pg2blk_shift;
637 "MXC_NAND: HWECC uncorrectable ECC error"
638 " in block %u page %u subpage %d\n",
639 last_bad, host->page_addr,
640 mtd->writesize / nand_chip->subpagesize
647 } while (subpages > 0);
652 #define mxc_nand_read_page_syndrome NULL
653 #define mxc_nand_read_page_raw_syndrome NULL
654 #define mxc_nand_read_oob_syndrome NULL
655 #define mxc_nand_write_page_syndrome NULL
656 #define mxc_nand_write_page_raw_syndrome NULL
657 #define mxc_nand_write_oob_syndrome NULL
659 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
660 u_char *read_ecc, u_char *calc_ecc)
662 struct nand_chip *nand_chip = mtd->priv;
663 struct mxc_nand_host *host = nand_chip->priv;
666 * 1-Bit errors are automatically corrected in HW. No need for
667 * additional correction. 2-Bit errors cannot be corrected by
668 * HW ECC, so we need to return failure
670 uint16_t ecc_status = readw(&host->regs->ecc_status_result);
672 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
673 MTDDEBUG(MTD_DEBUG_LEVEL0,
674 "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
682 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
689 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
691 struct nand_chip *nand_chip = mtd->priv;
692 struct mxc_nand_host *host = nand_chip->priv;
695 uint16_t __iomem *main_buf =
696 (uint16_t __iomem *)host->regs->main_area[0];
697 uint16_t __iomem *spare_buf =
698 (uint16_t __iomem *)host->regs->spare_area[0];
704 /* Check for status request */
705 if (host->status_request)
706 return get_dev_status(host) & 0xFF;
708 /* Get column for 16-bit access */
709 col = host->col_addr >> 1;
711 /* If we are accessing the spare region */
712 if (host->spare_only)
713 nfc_word.word = readw(&spare_buf[col]);
715 nfc_word.word = readw(&main_buf[col]);
717 /* Pick upper/lower byte of word from RAM buffer */
718 ret = nfc_word.bytes[host->col_addr & 0x1];
720 /* Update saved column address */
721 if (nand_chip->options & NAND_BUSWIDTH_16)
729 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
731 struct nand_chip *nand_chip = mtd->priv;
732 struct mxc_nand_host *host = nand_chip->priv;
736 MTDDEBUG(MTD_DEBUG_LEVEL3,
737 "mxc_nand_read_word(col = %d)\n", host->col_addr);
739 col = host->col_addr;
740 /* Adjust saved column address */
741 if (col < mtd->writesize && host->spare_only)
742 col += mtd->writesize;
744 if (col < mtd->writesize) {
745 p = (uint16_t __iomem *)(host->regs->main_area[0] +
748 p = (uint16_t __iomem *)(host->regs->spare_area[0] +
749 ((col - mtd->writesize) >> 1));
758 nfc_word[0].word = readw(p);
759 nfc_word[1].word = readw(p + 1);
761 nfc_word[2].bytes[0] = nfc_word[0].bytes[1];
762 nfc_word[2].bytes[1] = nfc_word[1].bytes[0];
764 ret = nfc_word[2].word;
769 /* Update saved column address */
770 host->col_addr = col + 2;
776 * Write data of length len to buffer buf. The data to be
777 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
778 * Operation by the NFC, the data is written to NAND Flash
780 static void mxc_nand_write_buf(struct mtd_info *mtd,
781 const u_char *buf, int len)
783 struct nand_chip *nand_chip = mtd->priv;
784 struct mxc_nand_host *host = nand_chip->priv;
787 MTDDEBUG(MTD_DEBUG_LEVEL3,
788 "mxc_nand_write_buf(col = %d, len = %d)\n", host->col_addr,
791 col = host->col_addr;
793 /* Adjust saved column address */
794 if (col < mtd->writesize && host->spare_only)
795 col += mtd->writesize;
797 n = mtd->writesize + mtd->oobsize - col;
800 MTDDEBUG(MTD_DEBUG_LEVEL3,
801 "%s:%d: col = %d, n = %d\n", __func__, __LINE__, col, n);
806 if (col < mtd->writesize) {
807 p = host->regs->main_area[0] + (col & ~3);
809 p = host->regs->spare_area[0] -
810 mtd->writesize + (col & ~3);
813 MTDDEBUG(MTD_DEBUG_LEVEL3, "%s:%d: p = %p\n", __func__,
816 if (((col | (unsigned long)&buf[i]) & 3) || n < 4) {
822 nfc_word.word = readl(p);
823 nfc_word.bytes[col & 3] = buf[i++];
827 writel(nfc_word.word, p);
829 int m = mtd->writesize - col;
831 if (col >= mtd->writesize)
836 MTDDEBUG(MTD_DEBUG_LEVEL3,
837 "%s:%d: n = %d, m = %d, i = %d, col = %d\n",
838 __func__, __LINE__, n, m, i, col);
840 mxc_nand_memcpy32(p, (uint32_t *)&buf[i], m);
846 /* Update saved column address */
847 host->col_addr = col;
851 * Read the data buffer from the NAND Flash. To read the data from NAND
852 * Flash first the data output cycle is initiated by the NFC, which copies
853 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
855 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
857 struct nand_chip *nand_chip = mtd->priv;
858 struct mxc_nand_host *host = nand_chip->priv;
861 MTDDEBUG(MTD_DEBUG_LEVEL3,
862 "mxc_nand_read_buf(col = %d, len = %d)\n", host->col_addr, len);
864 col = host->col_addr;
866 /* Adjust saved column address */
867 if (col < mtd->writesize && host->spare_only)
868 col += mtd->writesize;
870 n = mtd->writesize + mtd->oobsize - col;
876 if (col < mtd->writesize) {
877 p = host->regs->main_area[0] + (col & ~3);
879 p = host->regs->spare_area[0] -
880 mtd->writesize + (col & ~3);
883 if (((col | (int)&buf[i]) & 3) || n < 4) {
889 nfc_word.word = readl(p);
890 buf[i++] = nfc_word.bytes[col & 3];
894 int m = mtd->writesize - col;
896 if (col >= mtd->writesize)
900 mxc_nand_memcpy32((uint32_t *)&buf[i], p, m);
907 /* Update saved column address */
908 host->col_addr = col;
912 * Used by the upper layer to verify the data in NAND Flash
913 * with the data in the buf.
915 static int mxc_nand_verify_buf(struct mtd_info *mtd,
916 const u_char *buf, int len)
922 bsize = min(len, 256);
923 mxc_nand_read_buf(mtd, tmp, bsize);
925 if (memcmp(buf, tmp, bsize))
936 * This function is used by upper layer for select and
937 * deselect of the NAND chip
939 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
941 struct nand_chip *nand_chip = mtd->priv;
942 struct mxc_nand_host *host = nand_chip->priv;
946 /* TODO: Disable the NFC clock */
951 /* TODO: Enable the NFC clock */
962 * Used by the upper layer to write command to NAND Flash for
963 * different operations to be carried out on NAND Flash
965 void mxc_nand_command(struct mtd_info *mtd, unsigned command,
966 int column, int page_addr)
968 struct nand_chip *nand_chip = mtd->priv;
969 struct mxc_nand_host *host = nand_chip->priv;
971 MTDDEBUG(MTD_DEBUG_LEVEL3,
972 "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
973 command, column, page_addr);
975 /* Reset command state information */
976 host->status_request = false;
978 /* Command pre-processing step */
981 case NAND_CMD_STATUS:
983 host->status_request = true;
987 host->page_addr = page_addr;
988 host->col_addr = column;
989 host->spare_only = false;
992 case NAND_CMD_READOOB:
993 host->col_addr = column;
994 host->spare_only = true;
995 if (host->pagesize_2k)
996 command = NAND_CMD_READ0; /* only READ0 is valid */
1000 if (column >= mtd->writesize) {
1002 * before sending SEQIN command for partial write,
1003 * we need read one page out. FSL NFC does not support
1004 * partial write. It always sends out 512+ecc+512+ecc
1005 * for large page nand flash. But for small page nand
1006 * flash, it does support SPARE ONLY operation.
1008 if (host->pagesize_2k) {
1009 /* call ourself to read a page */
1010 mxc_nand_command(mtd, NAND_CMD_READ0, 0,
1014 host->col_addr = column - mtd->writesize;
1015 host->spare_only = true;
1017 /* Set program pointer to spare region */
1018 if (!host->pagesize_2k)
1019 send_cmd(host, NAND_CMD_READOOB);
1021 host->spare_only = false;
1022 host->col_addr = column;
1024 /* Set program pointer to page start */
1025 if (!host->pagesize_2k)
1026 send_cmd(host, NAND_CMD_READ0);
1030 case NAND_CMD_PAGEPROG:
1031 send_prog_page(host, 0, host->spare_only);
1033 if (host->pagesize_2k && is_mxc_nfc_1()) {
1034 /* data in 4 areas */
1035 send_prog_page(host, 1, host->spare_only);
1036 send_prog_page(host, 2, host->spare_only);
1037 send_prog_page(host, 3, host->spare_only);
1043 /* Write out the command to the device. */
1044 send_cmd(host, command);
1046 /* Write out column address, if necessary */
1049 * MXC NANDFC can only perform full page+spare or
1050 * spare-only read/write. When the upper layers perform
1051 * a read/write buffer operation, we will use the saved
1052 * column address to index into the full page.
1055 if (host->pagesize_2k)
1056 /* another col addr cycle for 2k page */
1060 /* Write out page address, if necessary */
1061 if (page_addr != -1) {
1062 u32 page_mask = nand_chip->pagemask;
1064 send_addr(host, page_addr & 0xFF);
1067 } while (page_mask);
1070 /* Command post-processing step */
1073 case NAND_CMD_RESET:
1076 case NAND_CMD_READOOB:
1077 case NAND_CMD_READ0:
1078 if (host->pagesize_2k) {
1079 /* send read confirm command */
1080 send_cmd(host, NAND_CMD_READSTART);
1081 /* read for each AREA */
1082 send_read_page(host, 0, host->spare_only);
1083 if (is_mxc_nfc_1()) {
1084 send_read_page(host, 1, host->spare_only);
1085 send_read_page(host, 2, host->spare_only);
1086 send_read_page(host, 3, host->spare_only);
1089 send_read_page(host, 0, host->spare_only);
1093 case NAND_CMD_READID:
1098 case NAND_CMD_PAGEPROG:
1101 case NAND_CMD_STATUS:
1104 case NAND_CMD_ERASE2:
1109 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1111 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
1112 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
1114 static struct nand_bbt_descr bbt_main_descr = {
1115 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
1116 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1121 .pattern = bbt_pattern,
1124 static struct nand_bbt_descr bbt_mirror_descr = {
1125 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
1126 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1131 .pattern = mirror_pattern,
1136 int board_nand_init(struct nand_chip *this)
1138 struct mtd_info *mtd;
1143 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1144 this->options |= NAND_USE_FLASH_BBT;
1145 this->bbt_td = &bbt_main_descr;
1146 this->bbt_md = &bbt_mirror_descr;
1149 /* structures must be linked */
1154 /* 5 us command delay time */
1155 this->chip_delay = 5;
1158 this->dev_ready = mxc_nand_dev_ready;
1159 this->cmdfunc = mxc_nand_command;
1160 this->select_chip = mxc_nand_select_chip;
1161 this->read_byte = mxc_nand_read_byte;
1162 this->read_word = mxc_nand_read_word;
1163 this->write_buf = mxc_nand_write_buf;
1164 this->read_buf = mxc_nand_read_buf;
1165 this->verify_buf = mxc_nand_verify_buf;
1167 host->regs = (struct fsl_nfc_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
1170 #ifdef CONFIG_MXC_NAND_HWECC
1171 this->ecc.calculate = mxc_nand_calculate_ecc;
1172 this->ecc.hwctl = mxc_nand_enable_hwecc;
1173 this->ecc.correct = mxc_nand_correct_data;
1174 if (is_mxc_nfc_21()) {
1175 this->ecc.mode = NAND_ECC_HW_SYNDROME;
1176 this->ecc.read_page = mxc_nand_read_page_syndrome;
1177 this->ecc.read_page_raw = mxc_nand_read_page_raw_syndrome;
1178 this->ecc.read_oob = mxc_nand_read_oob_syndrome;
1179 this->ecc.write_page = mxc_nand_write_page_syndrome;
1180 this->ecc.write_page_raw = mxc_nand_write_page_raw_syndrome;
1181 this->ecc.write_oob = mxc_nand_write_oob_syndrome;
1182 this->ecc.bytes = 9;
1183 this->ecc.prepad = 7;
1185 this->ecc.mode = NAND_ECC_HW;
1188 host->pagesize_2k = 0;
1190 this->ecc.size = 512;
1191 _mxc_nand_enable_hwecc(mtd, 1);
1193 this->ecc.layout = &nand_soft_eccoob;
1194 this->ecc.mode = NAND_ECC_SOFT;
1195 _mxc_nand_enable_hwecc(mtd, 0);
1198 this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1200 /* NAND bus width determines access functions used by upper layer */
1201 if (is_16bit_nand())
1202 this->options |= NAND_BUSWIDTH_16;
1204 #ifdef CONFIG_SYS_NAND_LARGEPAGE
1205 host->pagesize_2k = 1;
1206 this->ecc.layout = &nand_hw_eccoob2k;
1208 host->pagesize_2k = 0;
1209 this->ecc.layout = &nand_hw_eccoob;
1213 tmp = readw(&host->regs->config1);
1214 tmp |= NFC_ONE_CYCLE;
1215 tmp |= NFC_4_8N_ECC;
1216 writew(tmp, &host->regs->config1);
1217 if (host->pagesize_2k)
1218 writew(64/2, &host->regs->spare_area_size);
1220 writew(16/2, &host->regs->spare_area_size);
1225 * Unlock the internal RAM Buffer
1227 writew(0x2, &host->regs->config);
1229 /* Blocks to be unlocked */
1230 writew(0x0, &host->regs->unlockstart_blkaddr);
1231 /* Originally (Freescale LTIB 2.6.21) 0x4000 was written to the
1232 * unlockend_blkaddr, but the magic 0x4000 does not always work
1233 * when writing more than some 32 megabytes (on 2k page nands)
1234 * However 0xFFFF doesn't seem to have this kind
1235 * of limitation (tried it back and forth several times).
1236 * The linux kernel driver sets this to 0xFFFF for the v2 controller
1237 * only, but probably this was not tested there for v1.
1238 * The very same limitation seems to apply to this kernel driver.
1239 * This might be NAND chip specific and the i.MX31 datasheet is
1240 * extremely vague about the semantics of this register.
1242 writew(0xFFFF, &host->regs->unlockend_blkaddr);
1244 /* Unlock Block Command for given address range */
1245 writew(0x4, &host->regs->wrprot);