2 * Freescale GPMI NAND Flash Driver
4 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
5 * Copyright (C) 2008 Embedded Alley Solutions, Inc.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 #ifndef __DRIVERS_MTD_NAND_GPMI_NAND_H
18 #define __DRIVERS_MTD_NAND_GPMI_NAND_H
20 #include <linux/mtd/nand.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/dmaengine.h>
25 #define GPMI_CLK_MAX 5 /* MX6Q needs five clocks */
27 void __iomem *gpmi_regs;
28 void __iomem *bch_regs;
29 unsigned int dma_low_channel;
30 unsigned int dma_high_channel;
31 struct clk *clock[GPMI_CLK_MAX];
35 * struct bch_geometry - BCH geometry description.
36 * @gf_len: The length of Galois Field. (e.g., 13 or 14)
37 * @ecc_strength: A number that describes the strength of the ECC
39 * @page_size: The size, in bytes, of a physical page, including
41 * @metadata_size: The size, in bytes, of the metadata.
42 * @ecc_chunk_size: The size, in bytes, of a single ECC chunk. Note
43 * the first chunk in the page includes both data and
44 * metadata, so it's a bit larger than this value.
45 * @ecc_chunk_count: The number of ECC chunks in the page,
46 * @payload_size: The size, in bytes, of the payload buffer.
47 * @auxiliary_size: The size, in bytes, of the auxiliary buffer.
48 * @auxiliary_status_offset: The offset into the auxiliary buffer at which
49 * the ECC status appears.
50 * @block_mark_byte_offset: The byte offset in the ECC-based page view at
51 * which the underlying physical block mark appears.
52 * @block_mark_bit_offset: The bit offset into the ECC-based page view at
53 * which the underlying physical block mark appears.
57 unsigned int ecc_strength;
58 unsigned int page_size;
59 unsigned int metadata_size;
60 unsigned int ecc_chunk_size;
61 unsigned int ecc_chunk_count;
62 unsigned int payload_size;
63 unsigned int auxiliary_size;
64 unsigned int auxiliary_status_offset;
65 unsigned int block_mark_byte_offset;
66 unsigned int block_mark_bit_offset;
70 * struct boot_rom_geometry - Boot ROM geometry description.
71 * @stride_size_in_pages: The size of a boot block stride, in pages.
72 * @search_area_stride_exponent: The logarithm to base 2 of the size of a
73 * search area in boot block strides.
75 struct boot_rom_geometry {
76 unsigned int stride_size_in_pages;
77 unsigned int search_area_stride_exponent;
80 /* DMA operations types */
85 DMA_FOR_READ_ECC_PAGE,
86 DMA_FOR_WRITE_ECC_PAGE
90 * struct nand_timing - Fundamental timing attributes for NAND.
91 * @data_setup_in_ns: The data setup time, in nanoseconds. Usually the
92 * maximum of tDS and tWP. A negative value
93 * indicates this characteristic isn't known.
94 * @data_hold_in_ns: The data hold time, in nanoseconds. Usually the
95 * maximum of tDH, tWH and tREH. A negative value
96 * indicates this characteristic isn't known.
97 * @address_setup_in_ns: The address setup time, in nanoseconds. Usually
98 * the maximum of tCLS, tCS and tALS. A negative
99 * value indicates this characteristic isn't known.
100 * @gpmi_sample_delay_in_ns: A GPMI-specific timing parameter. A negative value
101 * indicates this characteristic isn't known.
102 * @tREA_in_ns: tREA, in nanoseconds, from the data sheet. A
103 * negative value indicates this characteristic isn't
105 * @tRLOH_in_ns: tRLOH, in nanoseconds, from the data sheet. A
106 * negative value indicates this characteristic isn't
108 * @tRHOH_in_ns: tRHOH, in nanoseconds, from the data sheet. A
109 * negative value indicates this characteristic isn't
113 int8_t data_setup_in_ns;
114 int8_t data_hold_in_ns;
115 int8_t address_setup_in_ns;
116 int8_t gpmi_sample_delay_in_ns;
130 struct gpmi_devdata {
132 int bch_max_ecc_strength;
133 int max_chain_delay; /* See the async EDO mode */
134 const char * const *clks;
135 const int clks_count;
138 struct gpmi_nand_data {
140 #define GPMI_ASYNC_EDO_ENABLED (1 << 0)
141 #define GPMI_TIMING_INIT_OK (1 << 1)
143 const struct gpmi_devdata *devdata;
145 /* System Interface */
147 struct platform_device *pdev;
150 struct resources resources;
153 struct nand_timing timing;
157 struct bch_geometry bch_geometry;
158 struct completion bch_done;
160 /* NAND Boot issue */
161 bool swap_block_mark;
162 struct boot_rom_geometry rom_geometry;
165 struct nand_chip nand;
167 /* General-use Variables */
169 unsigned int command_length;
171 /* passed from upper layer */
175 /* for DMA operations */
176 bool direct_dma_map_ok;
178 struct scatterlist cmd_sgl;
181 struct scatterlist data_sgl;
182 char *data_buffer_dma;
184 void *page_buffer_virt;
185 dma_addr_t page_buffer_phys;
186 unsigned int page_buffer_size;
189 dma_addr_t payload_phys;
191 void *auxiliary_virt;
192 dma_addr_t auxiliary_phys;
198 struct dma_chan *dma_chans[DMA_CHANS];
199 enum dma_ops_type last_dma_type;
200 enum dma_ops_type dma_type;
201 struct completion dma_done;
208 * struct gpmi_nfc_hardware_timing - GPMI hardware timing parameters.
209 * @data_setup_in_cycles: The data setup time, in cycles.
210 * @data_hold_in_cycles: The data hold time, in cycles.
211 * @address_setup_in_cycles: The address setup time, in cycles.
212 * @device_busy_timeout: The timeout waiting for NAND Ready/Busy,
213 * this value is the number of cycles multiplied
215 * @use_half_periods: Indicates the clock is running slowly, so the
216 * NFC DLL should use half-periods.
217 * @sample_delay_factor: The sample delay factor.
218 * @wrn_dly_sel: The delay on the GPMI write strobe.
220 struct gpmi_nfc_hardware_timing {
221 /* for HW_GPMI_TIMING0 */
222 uint8_t data_setup_in_cycles;
223 uint8_t data_hold_in_cycles;
224 uint8_t address_setup_in_cycles;
226 /* for HW_GPMI_TIMING1 */
227 uint16_t device_busy_timeout;
228 #define GPMI_DEFAULT_BUSY_TIMEOUT 0x500 /* default busy timeout value.*/
230 /* for HW_GPMI_CTRL1 */
231 bool use_half_periods;
232 uint8_t sample_delay_factor;
237 * struct timing_threshold - Timing threshold
238 * @max_data_setup_cycles: The maximum number of data setup cycles that
239 * can be expressed in the hardware.
240 * @internal_data_setup_in_ns: The time, in ns, that the NFC hardware requires
241 * for data read internal setup. In the Reference
242 * Manual, see the chapter "High-Speed NAND
243 * Timing" for more details.
244 * @max_sample_delay_factor: The maximum sample delay factor that can be
245 * expressed in the hardware.
246 * @max_dll_clock_period_in_ns: The maximum period of the GPMI clock that the
247 * sample delay DLL hardware can possibly work
248 * with (the DLL is unusable with longer periods).
249 * If the full-cycle period is greater than HALF
250 * this value, the DLL must be configured to use
252 * @max_dll_delay_in_ns: The maximum amount of delay, in ns, that the
254 * @clock_frequency_in_hz: The clock frequency, in Hz, during the current
255 * I/O transaction. If no I/O transaction is in
256 * progress, this is the clock frequency during
257 * the most recent I/O transaction.
259 struct timing_threshold {
260 const unsigned int max_chip_count;
261 const unsigned int max_data_setup_cycles;
262 const unsigned int internal_data_setup_in_ns;
263 const unsigned int max_sample_delay_factor;
264 const unsigned int max_dll_clock_period_in_ns;
265 const unsigned int max_dll_delay_in_ns;
266 unsigned long clock_frequency_in_hz;
270 /* Common Services */
271 extern int common_nfc_set_geometry(struct gpmi_nand_data *);
272 extern struct dma_chan *get_dma_chan(struct gpmi_nand_data *);
273 extern void prepare_data_dma(struct gpmi_nand_data *,
274 enum dma_data_direction dr);
275 extern int start_dma_without_bch_irq(struct gpmi_nand_data *,
276 struct dma_async_tx_descriptor *);
277 extern int start_dma_with_bch_irq(struct gpmi_nand_data *,
278 struct dma_async_tx_descriptor *);
280 /* GPMI-NAND helper function library */
281 extern int gpmi_init(struct gpmi_nand_data *);
282 extern int gpmi_extra_init(struct gpmi_nand_data *);
283 extern void gpmi_clear_bch(struct gpmi_nand_data *);
284 extern void gpmi_dump_info(struct gpmi_nand_data *);
285 extern int bch_set_geometry(struct gpmi_nand_data *);
286 extern int gpmi_is_ready(struct gpmi_nand_data *, unsigned chip);
287 extern int gpmi_send_command(struct gpmi_nand_data *);
288 extern void gpmi_begin(struct gpmi_nand_data *);
289 extern void gpmi_end(struct gpmi_nand_data *);
290 extern int gpmi_read_data(struct gpmi_nand_data *);
291 extern int gpmi_send_data(struct gpmi_nand_data *);
292 extern int gpmi_send_page(struct gpmi_nand_data *,
293 dma_addr_t payload, dma_addr_t auxiliary);
294 extern int gpmi_read_page(struct gpmi_nand_data *,
295 dma_addr_t payload, dma_addr_t auxiliary);
297 void gpmi_copy_bits(u8 *dst, size_t dst_bit_off,
298 const u8 *src, size_t src_bit_off,
301 /* BCH : Status Block Completion Codes */
302 #define STATUS_GOOD 0x00
303 #define STATUS_ERASED 0xff
304 #define STATUS_UNCORRECTABLE 0xfe
306 /* Use the devdata to distinguish different Archs. */
307 #define GPMI_IS_MX23(x) ((x)->devdata->type == IS_MX23)
308 #define GPMI_IS_MX28(x) ((x)->devdata->type == IS_MX28)
309 #define GPMI_IS_MX6Q(x) ((x)->devdata->type == IS_MX6Q)
310 #define GPMI_IS_MX6SX(x) ((x)->devdata->type == IS_MX6SX)
311 #define GPMI_IS_MX7D(x) ((x)->devdata->type == IS_MX7D)
313 #define GPMI_IS_MX6(x) (GPMI_IS_MX6Q(x) || GPMI_IS_MX6SX(x) || \