2 * drivers/mtd/nand/fsmc_nand.c
5 * Flexible Static Memory Controller (FSMC)
6 * Driver for NAND portions
8 * Copyright © 2010 ST Microelectronics
9 * Vipin Kumar <vipin.kumar@st.com>
12 * Based on drivers/mtd/nand/nomadik_nand.c
14 * This file is licensed under the terms of the GNU General Public
15 * License version 2. This program is licensed "as is" without any
16 * warranty of any kind, whether express or implied.
19 #include <linux/clk.h>
20 #include <linux/completion.h>
21 #include <linux/dmaengine.h>
22 #include <linux/dma-direction.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/err.h>
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/resource.h>
28 #include <linux/sched.h>
29 #include <linux/types.h>
30 #include <linux/mtd/mtd.h>
31 #include <linux/mtd/nand.h>
32 #include <linux/mtd/nand_ecc.h>
33 #include <linux/platform_device.h>
35 #include <linux/mtd/partitions.h>
37 #include <linux/slab.h>
38 #include <linux/mtd/fsmc.h>
39 #include <linux/amba/bus.h>
40 #include <mtd/mtd-abi.h>
42 static struct nand_ecclayout fsmc_ecc1_128_layout = {
44 .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52,
45 66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116},
47 {.offset = 8, .length = 8},
48 {.offset = 24, .length = 8},
49 {.offset = 40, .length = 8},
50 {.offset = 56, .length = 8},
51 {.offset = 72, .length = 8},
52 {.offset = 88, .length = 8},
53 {.offset = 104, .length = 8},
54 {.offset = 120, .length = 8}
58 static struct nand_ecclayout fsmc_ecc1_64_layout = {
60 .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52},
62 {.offset = 8, .length = 8},
63 {.offset = 24, .length = 8},
64 {.offset = 40, .length = 8},
65 {.offset = 56, .length = 8},
69 static struct nand_ecclayout fsmc_ecc1_16_layout = {
73 {.offset = 8, .length = 8},
78 * ECC4 layout for NAND of pagesize 8192 bytes & OOBsize 256 bytes. 13*16 bytes
79 * of OB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block and 46
80 * bytes are free for use.
82 static struct nand_ecclayout fsmc_ecc4_256_layout = {
84 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
85 9, 10, 11, 12, 13, 14,
86 18, 19, 20, 21, 22, 23, 24,
87 25, 26, 27, 28, 29, 30,
88 34, 35, 36, 37, 38, 39, 40,
89 41, 42, 43, 44, 45, 46,
90 50, 51, 52, 53, 54, 55, 56,
91 57, 58, 59, 60, 61, 62,
92 66, 67, 68, 69, 70, 71, 72,
93 73, 74, 75, 76, 77, 78,
94 82, 83, 84, 85, 86, 87, 88,
95 89, 90, 91, 92, 93, 94,
96 98, 99, 100, 101, 102, 103, 104,
97 105, 106, 107, 108, 109, 110,
98 114, 115, 116, 117, 118, 119, 120,
99 121, 122, 123, 124, 125, 126,
100 130, 131, 132, 133, 134, 135, 136,
101 137, 138, 139, 140, 141, 142,
102 146, 147, 148, 149, 150, 151, 152,
103 153, 154, 155, 156, 157, 158,
104 162, 163, 164, 165, 166, 167, 168,
105 169, 170, 171, 172, 173, 174,
106 178, 179, 180, 181, 182, 183, 184,
107 185, 186, 187, 188, 189, 190,
108 194, 195, 196, 197, 198, 199, 200,
109 201, 202, 203, 204, 205, 206,
110 210, 211, 212, 213, 214, 215, 216,
111 217, 218, 219, 220, 221, 222,
112 226, 227, 228, 229, 230, 231, 232,
113 233, 234, 235, 236, 237, 238,
114 242, 243, 244, 245, 246, 247, 248,
115 249, 250, 251, 252, 253, 254
118 {.offset = 15, .length = 3},
119 {.offset = 31, .length = 3},
120 {.offset = 47, .length = 3},
121 {.offset = 63, .length = 3},
122 {.offset = 79, .length = 3},
123 {.offset = 95, .length = 3},
124 {.offset = 111, .length = 3},
125 {.offset = 127, .length = 3},
126 {.offset = 143, .length = 3},
127 {.offset = 159, .length = 3},
128 {.offset = 175, .length = 3},
129 {.offset = 191, .length = 3},
130 {.offset = 207, .length = 3},
131 {.offset = 223, .length = 3},
132 {.offset = 239, .length = 3},
133 {.offset = 255, .length = 1}
138 * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 224 bytes. 13*8 bytes
139 * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 118
140 * bytes are free for use.
142 static struct nand_ecclayout fsmc_ecc4_224_layout = {
144 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
145 9, 10, 11, 12, 13, 14,
146 18, 19, 20, 21, 22, 23, 24,
147 25, 26, 27, 28, 29, 30,
148 34, 35, 36, 37, 38, 39, 40,
149 41, 42, 43, 44, 45, 46,
150 50, 51, 52, 53, 54, 55, 56,
151 57, 58, 59, 60, 61, 62,
152 66, 67, 68, 69, 70, 71, 72,
153 73, 74, 75, 76, 77, 78,
154 82, 83, 84, 85, 86, 87, 88,
155 89, 90, 91, 92, 93, 94,
156 98, 99, 100, 101, 102, 103, 104,
157 105, 106, 107, 108, 109, 110,
158 114, 115, 116, 117, 118, 119, 120,
159 121, 122, 123, 124, 125, 126
162 {.offset = 15, .length = 3},
163 {.offset = 31, .length = 3},
164 {.offset = 47, .length = 3},
165 {.offset = 63, .length = 3},
166 {.offset = 79, .length = 3},
167 {.offset = 95, .length = 3},
168 {.offset = 111, .length = 3},
169 {.offset = 127, .length = 97}
174 * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 128 bytes. 13*8 bytes
175 * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 22
176 * bytes are free for use.
178 static struct nand_ecclayout fsmc_ecc4_128_layout = {
180 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
181 9, 10, 11, 12, 13, 14,
182 18, 19, 20, 21, 22, 23, 24,
183 25, 26, 27, 28, 29, 30,
184 34, 35, 36, 37, 38, 39, 40,
185 41, 42, 43, 44, 45, 46,
186 50, 51, 52, 53, 54, 55, 56,
187 57, 58, 59, 60, 61, 62,
188 66, 67, 68, 69, 70, 71, 72,
189 73, 74, 75, 76, 77, 78,
190 82, 83, 84, 85, 86, 87, 88,
191 89, 90, 91, 92, 93, 94,
192 98, 99, 100, 101, 102, 103, 104,
193 105, 106, 107, 108, 109, 110,
194 114, 115, 116, 117, 118, 119, 120,
195 121, 122, 123, 124, 125, 126
198 {.offset = 15, .length = 3},
199 {.offset = 31, .length = 3},
200 {.offset = 47, .length = 3},
201 {.offset = 63, .length = 3},
202 {.offset = 79, .length = 3},
203 {.offset = 95, .length = 3},
204 {.offset = 111, .length = 3},
205 {.offset = 127, .length = 1}
210 * ECC4 layout for NAND of pagesize 2048 bytes & OOBsize 64 bytes. 13*4 bytes of
211 * OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block and 10
212 * bytes are free for use.
214 static struct nand_ecclayout fsmc_ecc4_64_layout = {
216 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
217 9, 10, 11, 12, 13, 14,
218 18, 19, 20, 21, 22, 23, 24,
219 25, 26, 27, 28, 29, 30,
220 34, 35, 36, 37, 38, 39, 40,
221 41, 42, 43, 44, 45, 46,
222 50, 51, 52, 53, 54, 55, 56,
223 57, 58, 59, 60, 61, 62,
226 {.offset = 15, .length = 3},
227 {.offset = 31, .length = 3},
228 {.offset = 47, .length = 3},
229 {.offset = 63, .length = 1},
234 * ECC4 layout for NAND of pagesize 512 bytes & OOBsize 16 bytes. 13 bytes of
235 * OOB size is reserved for ECC, Byte no. 4 & 5 reserved for bad block and One
236 * byte is free for use.
238 static struct nand_ecclayout fsmc_ecc4_16_layout = {
240 .eccpos = { 0, 1, 2, 3, 6, 7, 8,
241 9, 10, 11, 12, 13, 14
244 {.offset = 15, .length = 1},
249 * ECC placement definitions in oobfree type format.
250 * There are 13 bytes of ecc for every 512 byte block and it has to be read
251 * consecutively and immediately after the 512 byte data block for hardware to
252 * generate the error bit offsets in 512 byte data.
253 * Managing the ecc bytes in the following way makes it easier for software to
254 * read ecc bytes consecutive to data bytes. This way is similar to
255 * oobfree structure maintained already in generic nand driver
257 static struct fsmc_eccplace fsmc_ecc4_lp_place = {
259 {.offset = 2, .length = 13},
260 {.offset = 18, .length = 13},
261 {.offset = 34, .length = 13},
262 {.offset = 50, .length = 13},
263 {.offset = 66, .length = 13},
264 {.offset = 82, .length = 13},
265 {.offset = 98, .length = 13},
266 {.offset = 114, .length = 13}
270 static struct fsmc_eccplace fsmc_ecc4_sp_place = {
272 {.offset = 0, .length = 4},
273 {.offset = 6, .length = 9}
278 * struct fsmc_nand_data - structure for FSMC NAND device state
280 * @pid: Part ID on the AMBA PrimeCell format
281 * @mtd: MTD info for a NAND flash.
282 * @nand: Chip related info for a NAND flash.
283 * @partitions: Partition info for a NAND Flash.
284 * @nr_partitions: Total number of partition of a NAND flash.
286 * @ecc_place: ECC placing locations in oobfree type format.
287 * @bank: Bank number for probed device.
288 * @clk: Clock structure for FSMC.
290 * @read_dma_chan: DMA channel for read access
291 * @write_dma_chan: DMA channel for write access to NAND
292 * @dma_access_complete: Completion structure
294 * @data_pa: NAND Physical port for Data.
295 * @data_va: NAND port for Data.
296 * @cmd_va: NAND port for Command.
297 * @addr_va: NAND port for Address.
298 * @regs_va: FSMC regs base address.
300 struct fsmc_nand_data {
303 struct nand_chip nand;
304 struct mtd_partition *partitions;
305 unsigned int nr_partitions;
307 struct fsmc_eccplace *ecc_place;
310 enum access_mode mode;
313 /* DMA related objects */
314 struct dma_chan *read_dma_chan;
315 struct dma_chan *write_dma_chan;
316 struct completion dma_access_complete;
318 struct fsmc_nand_timings *dev_timings;
321 void __iomem *data_va;
322 void __iomem *cmd_va;
323 void __iomem *addr_va;
324 void __iomem *regs_va;
326 void (*select_chip)(uint32_t bank, uint32_t busw);
329 /* Assert CS signal based on chipnr */
330 static void fsmc_select_chip(struct mtd_info *mtd, int chipnr)
332 struct nand_chip *chip = mtd->priv;
333 struct fsmc_nand_data *host;
335 host = container_of(mtd, struct fsmc_nand_data, mtd);
339 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
345 if (host->select_chip)
346 host->select_chip(chipnr,
347 chip->options & NAND_BUSWIDTH_16);
356 * fsmc_cmd_ctrl - For facilitaing Hardware access
357 * This routine allows hardware specific access to control-lines(ALE,CLE)
359 static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
361 struct nand_chip *this = mtd->priv;
362 struct fsmc_nand_data *host = container_of(mtd,
363 struct fsmc_nand_data, mtd);
364 void __iomem *regs = host->regs_va;
365 unsigned int bank = host->bank;
367 if (ctrl & NAND_CTRL_CHANGE) {
370 if (ctrl & NAND_CLE) {
371 this->IO_ADDR_R = host->cmd_va;
372 this->IO_ADDR_W = host->cmd_va;
373 } else if (ctrl & NAND_ALE) {
374 this->IO_ADDR_R = host->addr_va;
375 this->IO_ADDR_W = host->addr_va;
377 this->IO_ADDR_R = host->data_va;
378 this->IO_ADDR_W = host->data_va;
381 pc = readl(FSMC_NAND_REG(regs, bank, PC));
386 writel_relaxed(pc, FSMC_NAND_REG(regs, bank, PC));
391 if (cmd != NAND_CMD_NONE)
392 writeb_relaxed(cmd, this->IO_ADDR_W);
396 * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
398 * This routine initializes timing parameters related to NAND memory access in
401 static void fsmc_nand_setup(void __iomem *regs, uint32_t bank,
402 uint32_t busw, struct fsmc_nand_timings *timings)
404 uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
405 uint32_t tclr, tar, thiz, thold, twait, tset;
406 struct fsmc_nand_timings *tims;
407 struct fsmc_nand_timings default_timings = {
411 .thold = FSMC_THOLD_4,
412 .twait = FSMC_TWAIT_6,
419 tims = &default_timings;
421 tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT;
422 tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT;
423 thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT;
424 thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT;
425 twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT;
426 tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
429 writel_relaxed(value | FSMC_DEVWID_16,
430 FSMC_NAND_REG(regs, bank, PC));
432 writel_relaxed(value | FSMC_DEVWID_8,
433 FSMC_NAND_REG(regs, bank, PC));
435 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | tclr | tar,
436 FSMC_NAND_REG(regs, bank, PC));
437 writel_relaxed(thiz | thold | twait | tset,
438 FSMC_NAND_REG(regs, bank, COMM));
439 writel_relaxed(thiz | thold | twait | tset,
440 FSMC_NAND_REG(regs, bank, ATTRIB));
444 * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
446 static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
448 struct fsmc_nand_data *host = container_of(mtd,
449 struct fsmc_nand_data, mtd);
450 void __iomem *regs = host->regs_va;
451 uint32_t bank = host->bank;
453 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCPLEN_256,
454 FSMC_NAND_REG(regs, bank, PC));
455 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCEN,
456 FSMC_NAND_REG(regs, bank, PC));
457 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | FSMC_ECCEN,
458 FSMC_NAND_REG(regs, bank, PC));
462 * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
463 * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
466 static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data,
469 struct fsmc_nand_data *host = container_of(mtd,
470 struct fsmc_nand_data, mtd);
471 void __iomem *regs = host->regs_va;
472 uint32_t bank = host->bank;
474 unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
477 if (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) & FSMC_CODE_RDY)
481 } while (!time_after_eq(jiffies, deadline));
483 if (time_after_eq(jiffies, deadline)) {
484 dev_err(host->dev, "calculate ecc timed out\n");
488 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
489 ecc[0] = (uint8_t) (ecc_tmp >> 0);
490 ecc[1] = (uint8_t) (ecc_tmp >> 8);
491 ecc[2] = (uint8_t) (ecc_tmp >> 16);
492 ecc[3] = (uint8_t) (ecc_tmp >> 24);
494 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
495 ecc[4] = (uint8_t) (ecc_tmp >> 0);
496 ecc[5] = (uint8_t) (ecc_tmp >> 8);
497 ecc[6] = (uint8_t) (ecc_tmp >> 16);
498 ecc[7] = (uint8_t) (ecc_tmp >> 24);
500 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
501 ecc[8] = (uint8_t) (ecc_tmp >> 0);
502 ecc[9] = (uint8_t) (ecc_tmp >> 8);
503 ecc[10] = (uint8_t) (ecc_tmp >> 16);
504 ecc[11] = (uint8_t) (ecc_tmp >> 24);
506 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
507 ecc[12] = (uint8_t) (ecc_tmp >> 16);
513 * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
514 * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
517 static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data,
520 struct fsmc_nand_data *host = container_of(mtd,
521 struct fsmc_nand_data, mtd);
522 void __iomem *regs = host->regs_va;
523 uint32_t bank = host->bank;
526 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
527 ecc[0] = (uint8_t) (ecc_tmp >> 0);
528 ecc[1] = (uint8_t) (ecc_tmp >> 8);
529 ecc[2] = (uint8_t) (ecc_tmp >> 16);
534 /* Count the number of 0's in buff upto a max of max_bits */
535 static int count_written_bits(uint8_t *buff, int size, int max_bits)
537 int k, written_bits = 0;
539 for (k = 0; k < size; k++) {
540 written_bits += hweight8(~buff[k]);
541 if (written_bits > max_bits)
548 static void dma_complete(void *param)
550 struct fsmc_nand_data *host = param;
552 complete(&host->dma_access_complete);
555 static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
556 enum dma_data_direction direction)
558 struct dma_chan *chan;
559 struct dma_device *dma_dev;
560 struct dma_async_tx_descriptor *tx;
561 dma_addr_t dma_dst, dma_src, dma_addr;
563 unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
566 if (direction == DMA_TO_DEVICE)
567 chan = host->write_dma_chan;
568 else if (direction == DMA_FROM_DEVICE)
569 chan = host->read_dma_chan;
573 dma_dev = chan->device;
574 dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction);
576 if (direction == DMA_TO_DEVICE) {
578 dma_dst = host->data_pa;
579 flags |= DMA_COMPL_SRC_UNMAP_SINGLE | DMA_COMPL_SKIP_DEST_UNMAP;
581 dma_src = host->data_pa;
583 flags |= DMA_COMPL_DEST_UNMAP_SINGLE | DMA_COMPL_SKIP_SRC_UNMAP;
586 tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src,
590 dev_err(host->dev, "device_prep_dma_memcpy error\n");
591 dma_unmap_single(dma_dev->dev, dma_addr, len, direction);
595 tx->callback = dma_complete;
596 tx->callback_param = host;
597 cookie = tx->tx_submit(tx);
599 ret = dma_submit_error(cookie);
601 dev_err(host->dev, "dma_submit_error %d\n", cookie);
605 dma_async_issue_pending(chan);
608 wait_for_completion_timeout(&host->dma_access_complete,
609 msecs_to_jiffies(3000));
611 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
612 dev_err(host->dev, "wait_for_completion_timeout\n");
613 return ret ? ret : -ETIMEDOUT;
620 * fsmc_write_buf - write buffer to chip
621 * @mtd: MTD device structure
623 * @len: number of bytes to write
625 static void fsmc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
628 struct nand_chip *chip = mtd->priv;
630 if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
631 IS_ALIGNED(len, sizeof(uint32_t))) {
632 uint32_t *p = (uint32_t *)buf;
634 for (i = 0; i < len; i++)
635 writel_relaxed(p[i], chip->IO_ADDR_W);
637 for (i = 0; i < len; i++)
638 writeb_relaxed(buf[i], chip->IO_ADDR_W);
643 * fsmc_read_buf - read chip data into buffer
644 * @mtd: MTD device structure
645 * @buf: buffer to store date
646 * @len: number of bytes to read
648 static void fsmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
651 struct nand_chip *chip = mtd->priv;
653 if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
654 IS_ALIGNED(len, sizeof(uint32_t))) {
655 uint32_t *p = (uint32_t *)buf;
657 for (i = 0; i < len; i++)
658 p[i] = readl_relaxed(chip->IO_ADDR_R);
660 for (i = 0; i < len; i++)
661 buf[i] = readb_relaxed(chip->IO_ADDR_R);
666 * fsmc_read_buf_dma - read chip data into buffer
667 * @mtd: MTD device structure
668 * @buf: buffer to store date
669 * @len: number of bytes to read
671 static void fsmc_read_buf_dma(struct mtd_info *mtd, uint8_t *buf, int len)
673 struct fsmc_nand_data *host;
675 host = container_of(mtd, struct fsmc_nand_data, mtd);
676 dma_xfer(host, buf, len, DMA_FROM_DEVICE);
680 * fsmc_write_buf_dma - write buffer to chip
681 * @mtd: MTD device structure
683 * @len: number of bytes to write
685 static void fsmc_write_buf_dma(struct mtd_info *mtd, const uint8_t *buf,
688 struct fsmc_nand_data *host;
690 host = container_of(mtd, struct fsmc_nand_data, mtd);
691 dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE);
695 * fsmc_read_page_hwecc
696 * @mtd: mtd info structure
697 * @chip: nand chip info structure
698 * @buf: buffer to store read data
699 * @oob_required: caller expects OOB data read to chip->oob_poi
700 * @page: page number to read
702 * This routine is needed for fsmc version 8 as reading from NAND chip has to be
703 * performed in a strict sequence as follows:
704 * data(512 byte) -> ecc(13 byte)
705 * After this read, fsmc hardware generates and reports error data bits(up to a
708 static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
709 uint8_t *buf, int oob_required, int page)
711 struct fsmc_nand_data *host = container_of(mtd,
712 struct fsmc_nand_data, mtd);
713 struct fsmc_eccplace *ecc_place = host->ecc_place;
714 int i, j, s, stat, eccsize = chip->ecc.size;
715 int eccbytes = chip->ecc.bytes;
716 int eccsteps = chip->ecc.steps;
718 uint8_t *ecc_calc = chip->buffers->ecccalc;
719 uint8_t *ecc_code = chip->buffers->ecccode;
720 int off, len, group = 0;
722 * ecc_oob is intentionally taken as uint16_t. In 16bit devices, we
723 * end up reading 14 bytes (7 words) from oob. The local array is
724 * to maintain word alignment
727 uint8_t *oob = (uint8_t *)&ecc_oob[0];
728 unsigned int max_bitflips = 0;
730 for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
731 chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page);
732 chip->ecc.hwctl(mtd, NAND_ECC_READ);
733 chip->read_buf(mtd, p, eccsize);
735 for (j = 0; j < eccbytes;) {
736 off = ecc_place->eccplace[group].offset;
737 len = ecc_place->eccplace[group].length;
741 * length is intentionally kept a higher multiple of 2
742 * to read at least 13 bytes even in case of 16 bit NAND
745 if (chip->options & NAND_BUSWIDTH_16)
746 len = roundup(len, 2);
748 chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page);
749 chip->read_buf(mtd, oob + j, len);
753 memcpy(&ecc_code[i], oob, chip->ecc.bytes);
754 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
756 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
758 mtd->ecc_stats.failed++;
760 mtd->ecc_stats.corrected += stat;
761 max_bitflips = max_t(unsigned int, max_bitflips, stat);
769 * fsmc_bch8_correct_data
770 * @mtd: mtd info structure
771 * @dat: buffer of read data
772 * @read_ecc: ecc read from device spare area
773 * @calc_ecc: ecc calculated from read data
775 * calc_ecc is a 104 bit information containing maximum of 8 error
776 * offset informations of 13 bits each in 512 bytes of read data.
778 static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat,
779 uint8_t *read_ecc, uint8_t *calc_ecc)
781 struct fsmc_nand_data *host = container_of(mtd,
782 struct fsmc_nand_data, mtd);
783 struct nand_chip *chip = mtd->priv;
784 void __iomem *regs = host->regs_va;
785 unsigned int bank = host->bank;
788 uint32_t ecc1, ecc2, ecc3, ecc4;
790 num_err = (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) >> 10) & 0xF;
792 /* no bit flipping */
793 if (likely(num_err == 0))
796 /* too many errors */
797 if (unlikely(num_err > 8)) {
799 * This is a temporary erase check. A newly erased page read
800 * would result in an ecc error because the oob data is also
801 * erased to FF and the calculated ecc for an FF data is not
803 * This is a workaround to skip performing correction in case
807 * For every page, each bit written as 0 is counted until these
808 * number of bits are greater than 8 (the maximum correction
809 * capability of FSMC for each 512 + 13 bytes)
812 int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8);
813 int bits_data = count_written_bits(dat, chip->ecc.size, 8);
815 if ((bits_ecc + bits_data) <= 8) {
817 memset(dat, 0xff, chip->ecc.size);
825 * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
826 * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
828 * calc_ecc is a 104 bit information containing maximum of 8 error
829 * offset informations of 13 bits each. calc_ecc is copied into a
830 * uint64_t array and error offset indexes are populated in err_idx
833 ecc1 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
834 ecc2 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
835 ecc3 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
836 ecc4 = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
838 err_idx[0] = (ecc1 >> 0) & 0x1FFF;
839 err_idx[1] = (ecc1 >> 13) & 0x1FFF;
840 err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
841 err_idx[3] = (ecc2 >> 7) & 0x1FFF;
842 err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
843 err_idx[5] = (ecc3 >> 1) & 0x1FFF;
844 err_idx[6] = (ecc3 >> 14) & 0x1FFF;
845 err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
849 change_bit(0, (unsigned long *)&err_idx[i]);
850 change_bit(1, (unsigned long *)&err_idx[i]);
852 if (err_idx[i] < chip->ecc.size * 8) {
853 change_bit(err_idx[i], (unsigned long *)dat);
860 static bool filter(struct dma_chan *chan, void *slave)
862 chan->private = slave;
867 static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
868 struct device_node *np)
870 struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
873 /* Set default NAND width to 8 bits */
875 if (!of_property_read_u32(np, "bank-width", &val)) {
878 } else if (val != 1) {
879 dev_err(&pdev->dev, "invalid bank-width %u\n", val);
883 if (of_get_property(np, "nand-skip-bbtscan", NULL))
884 pdata->options = NAND_SKIP_BBTSCAN;
889 static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
890 struct device_node *np)
897 * fsmc_nand_probe - Probe function
898 * @pdev: platform device structure
900 static int __init fsmc_nand_probe(struct platform_device *pdev)
902 struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
903 struct device_node __maybe_unused *np = pdev->dev.of_node;
904 struct mtd_part_parser_data ppdata = {};
905 struct fsmc_nand_data *host;
906 struct mtd_info *mtd;
907 struct nand_chip *nand;
908 struct resource *res;
915 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
916 pdev->dev.platform_data = pdata;
917 ret = fsmc_nand_probe_config_dt(pdev, np);
919 dev_err(&pdev->dev, "no platform data\n");
925 dev_err(&pdev->dev, "platform data is NULL\n");
929 /* Allocate memory for the device structure (and zero it) */
930 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
932 dev_err(&pdev->dev, "failed to allocate device structure\n");
936 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
940 host->data_va = devm_ioremap_resource(&pdev->dev, res);
941 if (IS_ERR(host->data_va))
942 return PTR_ERR(host->data_va);
944 host->data_pa = (dma_addr_t)res->start;
946 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr");
950 host->addr_va = devm_ioremap_resource(&pdev->dev, res);
951 if (IS_ERR(host->addr_va))
952 return PTR_ERR(host->addr_va);
954 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd");
958 host->cmd_va = devm_ioremap_resource(&pdev->dev, res);
959 if (IS_ERR(host->cmd_va))
960 return PTR_ERR(host->cmd_va);
962 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
966 host->regs_va = devm_ioremap_resource(&pdev->dev, res);
967 if (IS_ERR(host->regs_va))
968 return PTR_ERR(host->regs_va);
970 host->clk = clk_get(&pdev->dev, NULL);
971 if (IS_ERR(host->clk)) {
972 dev_err(&pdev->dev, "failed to fetch block clock\n");
973 return PTR_ERR(host->clk);
976 ret = clk_prepare_enable(host->clk);
978 goto err_clk_prepare_enable;
981 * This device ID is actually a common AMBA ID as used on the
982 * AMBA PrimeCell bus. However it is not a PrimeCell.
984 for (pid = 0, i = 0; i < 4; i++)
985 pid |= (readl(host->regs_va + resource_size(res) - 0x20 + 4 * i) & 255) << (i * 8);
987 dev_info(&pdev->dev, "FSMC device partno %03x, manufacturer %02x, "
988 "revision %02x, config %02x\n",
989 AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid),
990 AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
992 host->bank = pdata->bank;
993 host->select_chip = pdata->select_bank;
994 host->partitions = pdata->partitions;
995 host->nr_partitions = pdata->nr_partitions;
996 host->dev = &pdev->dev;
997 host->dev_timings = pdata->nand_timings;
998 host->mode = pdata->mode;
1000 if (host->mode == USE_DMA_ACCESS)
1001 init_completion(&host->dma_access_complete);
1003 /* Link all private pointers */
1009 host->mtd.owner = THIS_MODULE;
1010 nand->IO_ADDR_R = host->data_va;
1011 nand->IO_ADDR_W = host->data_va;
1012 nand->cmd_ctrl = fsmc_cmd_ctrl;
1013 nand->chip_delay = 30;
1015 nand->ecc.mode = NAND_ECC_HW;
1016 nand->ecc.hwctl = fsmc_enable_hwecc;
1017 nand->ecc.size = 512;
1018 nand->options = pdata->options;
1019 nand->select_chip = fsmc_select_chip;
1020 nand->badblockbits = 7;
1022 if (pdata->width == FSMC_NAND_BW16)
1023 nand->options |= NAND_BUSWIDTH_16;
1025 switch (host->mode) {
1026 case USE_DMA_ACCESS:
1028 dma_cap_set(DMA_MEMCPY, mask);
1029 host->read_dma_chan = dma_request_channel(mask, filter,
1030 pdata->read_dma_priv);
1031 if (!host->read_dma_chan) {
1032 dev_err(&pdev->dev, "Unable to get read dma channel\n");
1033 goto err_req_read_chnl;
1035 host->write_dma_chan = dma_request_channel(mask, filter,
1036 pdata->write_dma_priv);
1037 if (!host->write_dma_chan) {
1038 dev_err(&pdev->dev, "Unable to get write dma channel\n");
1039 goto err_req_write_chnl;
1041 nand->read_buf = fsmc_read_buf_dma;
1042 nand->write_buf = fsmc_write_buf_dma;
1046 case USE_WORD_ACCESS:
1047 nand->read_buf = fsmc_read_buf;
1048 nand->write_buf = fsmc_write_buf;
1052 fsmc_nand_setup(host->regs_va, host->bank,
1053 nand->options & NAND_BUSWIDTH_16,
1056 if (AMBA_REV_BITS(host->pid) >= 8) {
1057 nand->ecc.read_page = fsmc_read_page_hwecc;
1058 nand->ecc.calculate = fsmc_read_hwecc_ecc4;
1059 nand->ecc.correct = fsmc_bch8_correct_data;
1060 nand->ecc.bytes = 13;
1061 nand->ecc.strength = 8;
1063 nand->ecc.calculate = fsmc_read_hwecc_ecc1;
1064 nand->ecc.correct = nand_correct_data;
1065 nand->ecc.bytes = 3;
1066 nand->ecc.strength = 1;
1070 * Scan to find existence of the device
1072 if (nand_scan_ident(&host->mtd, 1, NULL)) {
1074 dev_err(&pdev->dev, "No NAND Device found!\n");
1075 goto err_scan_ident;
1078 if (AMBA_REV_BITS(host->pid) >= 8) {
1079 switch (host->mtd.oobsize) {
1081 nand->ecc.layout = &fsmc_ecc4_16_layout;
1082 host->ecc_place = &fsmc_ecc4_sp_place;
1085 nand->ecc.layout = &fsmc_ecc4_64_layout;
1086 host->ecc_place = &fsmc_ecc4_lp_place;
1089 nand->ecc.layout = &fsmc_ecc4_128_layout;
1090 host->ecc_place = &fsmc_ecc4_lp_place;
1093 nand->ecc.layout = &fsmc_ecc4_224_layout;
1094 host->ecc_place = &fsmc_ecc4_lp_place;
1097 nand->ecc.layout = &fsmc_ecc4_256_layout;
1098 host->ecc_place = &fsmc_ecc4_lp_place;
1101 printk(KERN_WARNING "No oob scheme defined for "
1102 "oobsize %d\n", mtd->oobsize);
1106 switch (host->mtd.oobsize) {
1108 nand->ecc.layout = &fsmc_ecc1_16_layout;
1111 nand->ecc.layout = &fsmc_ecc1_64_layout;
1114 nand->ecc.layout = &fsmc_ecc1_128_layout;
1117 printk(KERN_WARNING "No oob scheme defined for "
1118 "oobsize %d\n", mtd->oobsize);
1123 /* Second stage of scan to fill MTD data-structures */
1124 if (nand_scan_tail(&host->mtd)) {
1130 * The partition information can is accessed by (in the same precedence)
1132 * command line through Bootloader,
1134 * default partition information present in driver.
1137 * Check for partition info passed
1139 host->mtd.name = "nand";
1140 ppdata.of_node = np;
1141 ret = mtd_device_parse_register(&host->mtd, NULL, &ppdata,
1142 host->partitions, host->nr_partitions);
1146 platform_set_drvdata(pdev, host);
1147 dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
1152 if (host->mode == USE_DMA_ACCESS)
1153 dma_release_channel(host->write_dma_chan);
1155 if (host->mode == USE_DMA_ACCESS)
1156 dma_release_channel(host->read_dma_chan);
1158 clk_disable_unprepare(host->clk);
1159 err_clk_prepare_enable:
1167 static int fsmc_nand_remove(struct platform_device *pdev)
1169 struct fsmc_nand_data *host = platform_get_drvdata(pdev);
1171 platform_set_drvdata(pdev, NULL);
1174 nand_release(&host->mtd);
1176 if (host->mode == USE_DMA_ACCESS) {
1177 dma_release_channel(host->write_dma_chan);
1178 dma_release_channel(host->read_dma_chan);
1180 clk_disable_unprepare(host->clk);
1188 static int fsmc_nand_suspend(struct device *dev)
1190 struct fsmc_nand_data *host = dev_get_drvdata(dev);
1192 clk_disable_unprepare(host->clk);
1196 static int fsmc_nand_resume(struct device *dev)
1198 struct fsmc_nand_data *host = dev_get_drvdata(dev);
1200 clk_prepare_enable(host->clk);
1201 fsmc_nand_setup(host->regs_va, host->bank,
1202 host->nand.options & NAND_BUSWIDTH_16,
1208 static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume);
1212 static const struct of_device_id fsmc_nand_id_table[] = {
1213 { .compatible = "st,spear600-fsmc-nand" },
1214 { .compatible = "stericsson,fsmc-nand" },
1217 MODULE_DEVICE_TABLE(of, fsmc_nand_id_table);
1220 static struct platform_driver fsmc_nand_driver = {
1221 .remove = fsmc_nand_remove,
1223 .owner = THIS_MODULE,
1224 .name = "fsmc-nand",
1225 .of_match_table = of_match_ptr(fsmc_nand_id_table),
1227 .pm = &fsmc_nand_pm_ops,
1232 static int __init fsmc_nand_init(void)
1234 return platform_driver_probe(&fsmc_nand_driver,
1237 module_init(fsmc_nand_init);
1239 static void __exit fsmc_nand_exit(void)
1241 platform_driver_unregister(&fsmc_nand_driver);
1243 module_exit(fsmc_nand_exit);
1245 MODULE_LICENSE("GPL");
1246 MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi");
1247 MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");