1 /* Integrated Flash Controller NAND Machine Driver
3 * Copyright (c) 2011 Freescale Semiconductor, Inc
5 * Authors: Dipen Dudhat <Dipen.Dudhat@freescale.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/mtd/mtd.h>
26 #include <linux/mtd/nand.h>
27 #include <linux/mtd/nand_ecc.h>
30 #include <asm/errno.h>
31 #include <asm/fsl_ifc.h>
34 #define ERR_BYTE 0xFF /* Value returned for read bytes
36 #define IFC_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for IFC
41 /* mtd information per set */
44 struct nand_chip chip;
45 struct fsl_ifc_ctrl *ctrl;
48 int bank; /* Chip select bank number */
49 unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
50 u8 __iomem *vbase; /* Chip select base virtual address */
53 /* overview of the fsl ifc controller */
55 struct nand_hw_control controller;
56 struct fsl_ifc_mtd *chips[MAX_BANKS];
60 uint8_t __iomem *addr; /* Address of assigned IFC buffer */
61 unsigned int cs_nand; /* On which chipsel NAND is connected */
62 unsigned int page; /* Last page written to / read from */
63 unsigned int read_bytes; /* Number of bytes read during command */
64 unsigned int column; /* Saved column from SEQIN */
65 unsigned int index; /* Pointer to next byte to 'read' */
66 unsigned int status; /* status read from NEESR after last op */
67 unsigned int oob; /* Non zero if operating on OOB data */
68 unsigned int eccread; /* Non zero for a full-page ECC read */
71 static struct fsl_ifc_ctrl *ifc_ctrl;
73 /* 512-byte page with 4-bit ECC, 8-bit */
74 static struct nand_ecclayout oob_512_8bit_ecc4 = {
76 .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
77 .oobfree = { {0, 5}, {6, 2} },
80 /* 512-byte page with 4-bit ECC, 16-bit */
81 static struct nand_ecclayout oob_512_16bit_ecc4 = {
83 .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
84 .oobfree = { {2, 6}, },
87 /* 2048-byte page size with 4-bit ECC */
88 static struct nand_ecclayout oob_2048_ecc4 = {
91 8, 9, 10, 11, 12, 13, 14, 15,
92 16, 17, 18, 19, 20, 21, 22, 23,
93 24, 25, 26, 27, 28, 29, 30, 31,
94 32, 33, 34, 35, 36, 37, 38, 39,
96 .oobfree = { {2, 6}, {40, 24} },
99 /* 4096-byte page size with 4-bit ECC */
100 static struct nand_ecclayout oob_4096_ecc4 = {
103 8, 9, 10, 11, 12, 13, 14, 15,
104 16, 17, 18, 19, 20, 21, 22, 23,
105 24, 25, 26, 27, 28, 29, 30, 31,
106 32, 33, 34, 35, 36, 37, 38, 39,
107 40, 41, 42, 43, 44, 45, 46, 47,
108 48, 49, 50, 51, 52, 53, 54, 55,
109 56, 57, 58, 59, 60, 61, 62, 63,
110 64, 65, 66, 67, 68, 69, 70, 71,
112 .oobfree = { {2, 6}, {72, 56} },
115 /* 4096-byte page size with 8-bit ECC -- requires 218-byte OOB */
116 static struct nand_ecclayout oob_4096_ecc8 = {
119 8, 9, 10, 11, 12, 13, 14, 15,
120 16, 17, 18, 19, 20, 21, 22, 23,
121 24, 25, 26, 27, 28, 29, 30, 31,
122 32, 33, 34, 35, 36, 37, 38, 39,
123 40, 41, 42, 43, 44, 45, 46, 47,
124 48, 49, 50, 51, 52, 53, 54, 55,
125 56, 57, 58, 59, 60, 61, 62, 63,
126 64, 65, 66, 67, 68, 69, 70, 71,
127 72, 73, 74, 75, 76, 77, 78, 79,
128 80, 81, 82, 83, 84, 85, 86, 87,
129 88, 89, 90, 91, 92, 93, 94, 95,
130 96, 97, 98, 99, 100, 101, 102, 103,
131 104, 105, 106, 107, 108, 109, 110, 111,
132 112, 113, 114, 115, 116, 117, 118, 119,
133 120, 121, 122, 123, 124, 125, 126, 127,
134 128, 129, 130, 131, 132, 133, 134, 135,
136 .oobfree = { {2, 6}, {136, 82} },
141 * Generic flash bbt descriptors
143 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
144 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
146 static struct nand_bbt_descr bbt_main_descr = {
147 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
148 NAND_BBT_2BIT | NAND_BBT_VERSION,
149 .offs = 2, /* 0 on 8-bit small page */
153 .pattern = bbt_pattern,
156 static struct nand_bbt_descr bbt_mirror_descr = {
157 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
158 NAND_BBT_2BIT | NAND_BBT_VERSION,
159 .offs = 2, /* 0 on 8-bit small page */
163 .pattern = mirror_pattern,
167 * Set up the IFC hardware block and page address fields, and the ifc nand
168 * structure addr field to point to the correct IFC buffer in memory
170 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
172 struct nand_chip *chip = mtd->priv;
173 struct fsl_ifc_mtd *priv = chip->priv;
174 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
175 struct fsl_ifc *ifc = ctrl->regs;
178 ctrl->page = page_addr;
180 /* Program ROW0/COL0 */
181 out_be32(&ifc->ifc_nand.row0, page_addr);
182 out_be32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column);
184 buf_num = page_addr & priv->bufnum_mask;
186 ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
187 ctrl->index = column;
189 /* for OOB data point to the second half of the buffer */
191 ctrl->index += mtd->writesize;
194 static int is_blank(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
197 struct nand_chip *chip = mtd->priv;
198 struct fsl_ifc_mtd *priv = chip->priv;
199 u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2);
200 u32 __iomem *main = (u32 *)addr;
201 u8 __iomem *oob = addr + mtd->writesize;
204 for (i = 0; i < mtd->writesize / 4; i++) {
205 if (__raw_readl(&main[i]) != 0xffffffff)
209 for (i = 0; i < chip->ecc.layout->eccbytes; i++) {
210 int pos = chip->ecc.layout->eccpos[i];
212 if (__raw_readb(&oob[pos]) != 0xff)
219 /* returns nonzero if entire page is blank */
220 static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
221 u32 *eccstat, unsigned int bufnum)
223 u32 reg = eccstat[bufnum / 4];
224 int errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
226 if (errors == 15) { /* uncorrectable */
227 /* Blank pages fail hw ECC checks */
228 if (is_blank(mtd, ctrl, bufnum))
232 * We disable ECCER reporting in hardware due to
233 * erratum IFC-A002770 -- so report it now if we
234 * see an uncorrectable error in ECCSTAT.
236 ctrl->status |= IFC_NAND_EVTER_STAT_ECCER;
237 } else if (errors > 0) {
238 mtd->ecc_stats.corrected += errors;
245 * execute IFC NAND command and wait for it to complete
247 static int fsl_ifc_run_command(struct mtd_info *mtd)
249 struct nand_chip *chip = mtd->priv;
250 struct fsl_ifc_mtd *priv = chip->priv;
251 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
252 struct fsl_ifc *ifc = ctrl->regs;
257 /* set the chip select for NAND Transaction */
258 out_be32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
260 /* start read/write seq */
261 out_be32(&ifc->ifc_nand.nandseq_strt,
262 IFC_NAND_SEQ_STRT_FIR_STRT);
264 /* wait for NAND Machine complete flag or timeout */
265 end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
267 while (end_tick > get_ticks()) {
268 ctrl->status = in_be32(&ifc->ifc_nand.nand_evter_stat);
270 if (ctrl->status & IFC_NAND_EVTER_STAT_OPC)
274 out_be32(&ifc->ifc_nand.nand_evter_stat, ctrl->status);
276 if (ctrl->status & IFC_NAND_EVTER_STAT_FTOER)
277 printf("%s: Flash Time Out Error\n", __func__);
278 if (ctrl->status & IFC_NAND_EVTER_STAT_WPER)
279 printf("%s: Write Protect Error\n", __func__);
282 int bufperpage = mtd->writesize / 512;
283 int bufnum = (ctrl->page & priv->bufnum_mask) * bufperpage;
284 int bufnum_end = bufnum + bufperpage - 1;
286 for (i = bufnum / 4; i <= bufnum_end / 4; i++)
287 eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]);
289 for (i = bufnum; i <= bufnum_end; i++) {
290 if (check_read_ecc(mtd, ctrl, eccstat, i))
297 /* returns 0 on success otherwise non-zero) */
298 return ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO;
301 static void fsl_ifc_do_read(struct nand_chip *chip,
303 struct mtd_info *mtd)
305 struct fsl_ifc_mtd *priv = chip->priv;
306 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
307 struct fsl_ifc *ifc = ctrl->regs;
309 /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
310 if (mtd->writesize > 512) {
311 out_be32(&ifc->ifc_nand.nand_fir0,
312 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
313 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
314 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
315 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
316 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT));
317 out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
319 out_be32(&ifc->ifc_nand.nand_fcr0,
320 (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
321 (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
323 out_be32(&ifc->ifc_nand.nand_fir0,
324 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
325 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
326 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
327 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT));
330 out_be32(&ifc->ifc_nand.nand_fcr0,
331 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT);
333 out_be32(&ifc->ifc_nand.nand_fcr0,
334 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
338 /* cmdfunc send commands to the IFC NAND Machine */
339 static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
340 int column, int page_addr)
342 struct nand_chip *chip = mtd->priv;
343 struct fsl_ifc_mtd *priv = chip->priv;
344 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
345 struct fsl_ifc *ifc = ctrl->regs;
347 /* clear the read buffer */
348 ctrl->read_bytes = 0;
349 if (command != NAND_CMD_PAGEPROG)
353 /* READ0 read the entire buffer to use hardware ECC. */
354 case NAND_CMD_READ0: {
355 out_be32(&ifc->ifc_nand.nand_fbcr, 0);
356 set_addr(mtd, 0, page_addr, 0);
358 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
359 ctrl->index += column;
361 if (chip->ecc.mode == NAND_ECC_HW)
364 fsl_ifc_do_read(chip, 0, mtd);
365 fsl_ifc_run_command(mtd);
369 /* READOOB reads only the OOB because no ECC is performed. */
370 case NAND_CMD_READOOB:
371 out_be32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column);
372 set_addr(mtd, column, page_addr, 1);
374 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
376 fsl_ifc_do_read(chip, 1, mtd);
377 fsl_ifc_run_command(mtd);
381 /* READID must read all possible bytes while CEB is active */
382 case NAND_CMD_READID:
383 out_be32(&ifc->ifc_nand.nand_fir0,
384 (IFC_FIR_OP_CMD0 << IFC_NAND_FIR0_OP0_SHIFT) |
385 (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
386 (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT));
387 out_be32(&ifc->ifc_nand.nand_fcr0,
388 NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT);
389 /* 4 bytes for manuf, device and exts */
390 out_be32(&ifc->ifc_nand.nand_fbcr, 4);
391 ctrl->read_bytes = 4;
393 set_addr(mtd, 0, 0, 0);
394 fsl_ifc_run_command(mtd);
397 /* ERASE1 stores the block and page address */
398 case NAND_CMD_ERASE1:
399 set_addr(mtd, 0, page_addr, 0);
402 /* ERASE2 uses the block and page address from ERASE1 */
403 case NAND_CMD_ERASE2:
404 out_be32(&ifc->ifc_nand.nand_fir0,
405 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
406 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
407 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT));
409 out_be32(&ifc->ifc_nand.nand_fcr0,
410 (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
411 (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT));
413 out_be32(&ifc->ifc_nand.nand_fbcr, 0);
414 ctrl->read_bytes = 0;
415 fsl_ifc_run_command(mtd);
418 /* SEQIN sets up the addr buffer and all registers except the length */
419 case NAND_CMD_SEQIN: {
421 ctrl->column = column;
424 if (mtd->writesize > 512) {
426 (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
427 (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD1_SHIFT);
429 out_be32(&ifc->ifc_nand.nand_fir0,
430 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
431 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
432 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
433 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) |
434 (IFC_FIR_OP_CW1 << IFC_NAND_FIR0_OP4_SHIFT));
435 out_be32(&ifc->ifc_nand.nand_fir1, 0);
437 nand_fcr0 = ((NAND_CMD_PAGEPROG <<
438 IFC_NAND_FCR0_CMD1_SHIFT) |
440 IFC_NAND_FCR0_CMD2_SHIFT));
442 out_be32(&ifc->ifc_nand.nand_fir0,
443 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
444 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
445 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
446 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
447 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT));
448 out_be32(&ifc->ifc_nand.nand_fir1,
449 (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT));
451 if (column >= mtd->writesize) {
452 /* OOB area --> READOOB */
453 column -= mtd->writesize;
454 nand_fcr0 |= NAND_CMD_READOOB <<
455 IFC_NAND_FCR0_CMD0_SHIFT;
457 } else if (column < 256) {
458 /* First 256 bytes --> READ0 */
459 nand_fcr0 |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
461 /* Second 256 bytes --> READ1 */
462 nand_fcr0 |= NAND_CMD_READ1 << FCR_CMD0_SHIFT;
466 out_be32(&ifc->ifc_nand.nand_fcr0, nand_fcr0);
467 set_addr(mtd, column, page_addr, ctrl->oob);
471 /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
472 case NAND_CMD_PAGEPROG:
474 out_be32(&ifc->ifc_nand.nand_fbcr, ctrl->index);
476 out_be32(&ifc->ifc_nand.nand_fbcr, 0);
478 fsl_ifc_run_command(mtd);
481 case NAND_CMD_STATUS:
482 out_be32(&ifc->ifc_nand.nand_fir0,
483 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
484 (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT));
485 out_be32(&ifc->ifc_nand.nand_fcr0,
486 NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT);
487 out_be32(&ifc->ifc_nand.nand_fbcr, 1);
488 set_addr(mtd, 0, 0, 0);
489 ctrl->read_bytes = 1;
491 fsl_ifc_run_command(mtd);
493 /* Chip sometimes reporting write protect even when it's not */
494 out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
498 out_be32(&ifc->ifc_nand.nand_fir0,
499 IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT);
500 out_be32(&ifc->ifc_nand.nand_fcr0,
501 NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT);
502 fsl_ifc_run_command(mtd);
506 printf("%s: error, unsupported command 0x%x.\n",
512 * Write buf to the IFC NAND Controller Data Buffer
514 static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
516 struct nand_chip *chip = mtd->priv;
517 struct fsl_ifc_mtd *priv = chip->priv;
518 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
519 unsigned int bufsize = mtd->writesize + mtd->oobsize;
522 printf("%s of %d bytes", __func__, len);
527 if ((unsigned int)len > bufsize - ctrl->index) {
528 printf("%s beyond end of buffer "
529 "(%d requested, %u available)\n",
530 __func__, len, bufsize - ctrl->index);
531 len = bufsize - ctrl->index;
534 memcpy_toio(&ctrl->addr[ctrl->index], buf, len);
539 * read a byte from either the IFC hardware buffer if it has any data left
540 * otherwise issue a command to read a single byte.
542 static u8 fsl_ifc_read_byte(struct mtd_info *mtd)
544 struct nand_chip *chip = mtd->priv;
545 struct fsl_ifc_mtd *priv = chip->priv;
546 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
548 /* If there are still bytes in the IFC buffer, then use the
550 if (ctrl->index < ctrl->read_bytes)
551 return in_8(&ctrl->addr[ctrl->index++]);
553 printf("%s beyond end of buffer\n", __func__);
558 * Read two bytes from the IFC hardware buffer
559 * read function for 16-bit buswith
561 static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
563 struct nand_chip *chip = mtd->priv;
564 struct fsl_ifc_mtd *priv = chip->priv;
565 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
569 * If there are still bytes in the IFC buffer, then use the
572 if (ctrl->index < ctrl->read_bytes) {
573 data = in_be16((uint16_t *)&ctrl->
576 return (uint8_t)data;
579 printf("%s beyond end of buffer\n", __func__);
584 * Read from the IFC Controller Data Buffer
586 static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
588 struct nand_chip *chip = mtd->priv;
589 struct fsl_ifc_mtd *priv = chip->priv;
590 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
596 avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
597 memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail);
598 ctrl->index += avail;
601 printf("%s beyond end of buffer "
602 "(%d requested, %d available)\n",
603 __func__, len, avail);
607 * Verify buffer against the IFC Controller Data Buffer
609 static int fsl_ifc_verify_buf(struct mtd_info *mtd,
610 const u_char *buf, int len)
612 struct nand_chip *chip = mtd->priv;
613 struct fsl_ifc_mtd *priv = chip->priv;
614 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
618 printf("%s of %d bytes", __func__, len);
622 if ((unsigned int)len > ctrl->read_bytes - ctrl->index) {
623 printf("%s beyond end of buffer "
624 "(%d requested, %u available)\n",
625 __func__, len, ctrl->read_bytes - ctrl->index);
627 ctrl->index = ctrl->read_bytes;
631 for (i = 0; i < len; i++)
632 if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i])
636 return i == len && ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO;
639 /* This function is called after Program and Erase Operations to
640 * check for success or failure.
642 static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
644 struct fsl_ifc_mtd *priv = chip->priv;
645 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
646 struct fsl_ifc *ifc = ctrl->regs;
649 if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
650 return NAND_STATUS_FAIL;
652 /* Use READ_STATUS command, but wait for the device to be ready */
653 out_be32(&ifc->ifc_nand.nand_fir0,
654 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
655 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT));
656 out_be32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS <<
657 IFC_NAND_FCR0_CMD0_SHIFT);
658 out_be32(&ifc->ifc_nand.nand_fbcr, 1);
659 set_addr(mtd, 0, 0, 0);
660 ctrl->read_bytes = 1;
662 fsl_ifc_run_command(mtd);
664 if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
665 return NAND_STATUS_FAIL;
667 nand_fsr = in_be32(&ifc->ifc_nand.nand_fsr);
669 /* Chip sometimes reporting write protect even when it's not */
670 nand_fsr = nand_fsr | NAND_STATUS_WP;
674 static int fsl_ifc_read_page(struct mtd_info *mtd,
675 struct nand_chip *chip,
676 uint8_t *buf, int page)
678 struct fsl_ifc_mtd *priv = chip->priv;
679 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
681 fsl_ifc_read_buf(mtd, buf, mtd->writesize);
682 fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
684 if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
685 mtd->ecc_stats.failed++;
690 /* ECC will be calculated automatically, and errors will be detected in
693 static void fsl_ifc_write_page(struct mtd_info *mtd,
694 struct nand_chip *chip,
697 fsl_ifc_write_buf(mtd, buf, mtd->writesize);
698 fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
701 static void fsl_ifc_ctrl_init(void)
703 ifc_ctrl = kzalloc(sizeof(*ifc_ctrl), GFP_KERNEL);
707 ifc_ctrl->regs = IFC_BASE_ADDR;
709 /* clear event registers */
710 out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_stat, ~0U);
711 out_be32(&ifc_ctrl->regs->ifc_nand.pgrdcmpl_evt_stat, ~0U);
713 /* Enable error and event for any detected errors */
714 out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_en,
715 IFC_NAND_EVTER_EN_OPC_EN |
716 IFC_NAND_EVTER_EN_PGRDCMPL_EN |
717 IFC_NAND_EVTER_EN_FTOER_EN |
718 IFC_NAND_EVTER_EN_WPER_EN);
720 out_be32(&ifc_ctrl->regs->ifc_nand.ncfgr, 0x0);
723 static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
727 int board_nand_init(struct nand_chip *nand)
729 struct fsl_ifc_mtd *priv;
730 struct nand_ecclayout *layout;
731 uint32_t cspr = 0, csor = 0;
739 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
743 priv->ctrl = ifc_ctrl;
744 priv->vbase = nand->IO_ADDR_R;
746 /* Find which chip select it is connected to.
748 for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
749 phys_addr_t base_addr = virt_to_phys(nand->IO_ADDR_R);
751 cspr = in_be32(&ifc_ctrl->regs->cspr_cs[priv->bank].cspr);
752 csor = in_be32(&ifc_ctrl->regs->csor_cs[priv->bank].csor);
754 if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND &&
755 (cspr & CSPR_BA) == CSPR_PHYS_ADDR(base_addr)) {
756 ifc_ctrl->cs_nand = priv->bank << IFC_NAND_CSEL_SHIFT;
761 if (priv->bank >= MAX_BANKS) {
762 printf("%s: address did not match any "
763 "chip selects\n", __func__);
767 ifc_ctrl->chips[priv->bank] = priv;
769 /* fill in nand_chip structure */
770 /* set up function call table */
772 nand->write_buf = fsl_ifc_write_buf;
773 nand->read_buf = fsl_ifc_read_buf;
774 nand->verify_buf = fsl_ifc_verify_buf;
775 nand->select_chip = fsl_ifc_select_chip;
776 nand->cmdfunc = fsl_ifc_cmdfunc;
777 nand->waitfunc = fsl_ifc_wait;
779 /* set up nand options */
780 nand->bbt_td = &bbt_main_descr;
781 nand->bbt_md = &bbt_mirror_descr;
783 /* set up nand options */
784 nand->options = NAND_NO_READRDY | NAND_NO_AUTOINCR |
787 if (cspr & CSPR_PORT_SIZE_16) {
788 nand->read_byte = fsl_ifc_read_byte16;
789 nand->options |= NAND_BUSWIDTH_16;
791 nand->read_byte = fsl_ifc_read_byte;
794 nand->controller = &ifc_ctrl->controller;
797 nand->ecc.read_page = fsl_ifc_read_page;
798 nand->ecc.write_page = fsl_ifc_write_page;
800 /* Hardware generates ECC per 512 Bytes */
801 nand->ecc.size = 512;
804 switch (csor & CSOR_NAND_PGS_MASK) {
805 case CSOR_NAND_PGS_512:
806 if (nand->options & NAND_BUSWIDTH_16) {
807 layout = &oob_512_16bit_ecc4;
809 layout = &oob_512_8bit_ecc4;
811 /* Avoid conflict with bad block marker */
812 bbt_main_descr.offs = 0;
813 bbt_mirror_descr.offs = 0;
816 priv->bufnum_mask = 15;
819 case CSOR_NAND_PGS_2K:
820 layout = &oob_2048_ecc4;
821 priv->bufnum_mask = 3;
824 case CSOR_NAND_PGS_4K:
825 if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
826 CSOR_NAND_ECC_MODE_4) {
827 layout = &oob_4096_ecc4;
829 layout = &oob_4096_ecc8;
830 nand->ecc.bytes = 16;
833 priv->bufnum_mask = 1;
837 printf("ifc nand: bad csor %#x: bad page size\n", csor);
841 /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
842 if (csor & CSOR_NAND_ECC_DEC_EN) {
843 nand->ecc.mode = NAND_ECC_HW;
844 nand->ecc.layout = layout;
846 nand->ecc.mode = NAND_ECC_SOFT;