drivers/mtd/nand/fsl_ifc_nand.c

   1 /* Integrated Flash Controller NAND Machine Driver
   2  *
   3  * Copyright (c) 2012 Freescale Semiconductor, Inc
   4  *
   5  * Authors: Dipen Dudhat <Dipen.Dudhat@freescale.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <malloc.h>
  12 #include <nand.h>
  13
  14 #include <linux/mtd/mtd.h>
  15 #include <linux/mtd/nand.h>
  16 #include <linux/mtd/nand_ecc.h>
  17
  18 #include <asm/io.h>
  19 #include <asm/errno.h>
  20 #include <fsl_ifc.h>
  21
  22 #ifndef CONFIG_SYS_FSL_IFC_BANK_COUNT
  23 #define CONFIG_SYS_FSL_IFC_BANK_COUNT   4
  24 #endif
  25
  26 #define MAX_BANKS       CONFIG_SYS_FSL_IFC_BANK_COUNT
  27 #define ERR_BYTE        0xFF /* Value returned for read bytes
  28                                 when read failed */
  29 #define IFC_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for IFC
  30                                 NAND Machine */
  31
  32 struct fsl_ifc_ctrl;
  33
  34 /* mtd information per set */
  35 struct fsl_ifc_mtd {
  36         struct nand_chip chip;
  37         struct fsl_ifc_ctrl *ctrl;
  38
  39         struct device *dev;
  40         int bank;               /* Chip select bank number                */
  41         unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
  42         u8 __iomem *vbase;      /* Chip select base virtual address       */
  43 };
  44
  45 /* overview of the fsl ifc controller */
  46 struct fsl_ifc_ctrl {
  47         struct nand_hw_control controller;
  48         struct fsl_ifc_mtd *chips[MAX_BANKS];
  49
  50         /* device info */
  51         struct fsl_ifc *regs;
  52         uint8_t __iomem *addr;   /* Address of assigned IFC buffer        */
  53         unsigned int cs_nand;    /* On which chipsel NAND is connected    */
  54         unsigned int page;       /* Last page written to / read from      */
  55         unsigned int read_bytes; /* Number of bytes read during command   */
  56         unsigned int column;     /* Saved column from SEQIN               */
  57         unsigned int index;      /* Pointer to next byte to 'read'        */
  58         unsigned int status;     /* status read from NEESR after last op  */
  59         unsigned int oob;        /* Non zero if operating on OOB data     */
  60         unsigned int eccread;    /* Non zero for a full-page ECC read     */
  61 };
  62
  63 static struct fsl_ifc_ctrl *ifc_ctrl;
  64
  65 /* 512-byte page with 4-bit ECC, 8-bit */
  66 static struct nand_ecclayout oob_512_8bit_ecc4 = {
  67         .eccbytes = 8,
  68         .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
  69         .oobfree = { {0, 5}, {6, 2} },
  70 };
  71
  72 /* 512-byte page with 4-bit ECC, 16-bit */
  73 static struct nand_ecclayout oob_512_16bit_ecc4 = {
  74         .eccbytes = 8,
  75         .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
  76         .oobfree = { {2, 6}, },
  77 };
  78
  79 /* 2048-byte page size with 4-bit ECC */
  80 static struct nand_ecclayout oob_2048_ecc4 = {
  81         .eccbytes = 32,
  82         .eccpos = {
  83                 8, 9, 10, 11, 12, 13, 14, 15,
  84                 16, 17, 18, 19, 20, 21, 22, 23,
  85                 24, 25, 26, 27, 28, 29, 30, 31,
  86                 32, 33, 34, 35, 36, 37, 38, 39,
  87         },
  88         .oobfree = { {2, 6}, {40, 24} },
  89 };
  90
  91 /* 4096-byte page size with 4-bit ECC */
  92 static struct nand_ecclayout oob_4096_ecc4 = {
  93         .eccbytes = 64,
  94         .eccpos = {
  95                 8, 9, 10, 11, 12, 13, 14, 15,
  96                 16, 17, 18, 19, 20, 21, 22, 23,
  97                 24, 25, 26, 27, 28, 29, 30, 31,
  98                 32, 33, 34, 35, 36, 37, 38, 39,
  99                 40, 41, 42, 43, 44, 45, 46, 47,
 100                 48, 49, 50, 51, 52, 53, 54, 55,
 101                 56, 57, 58, 59, 60, 61, 62, 63,
 102                 64, 65, 66, 67, 68, 69, 70, 71,
 103         },
 104         .oobfree = { {2, 6}, {72, 56} },
 105 };
 106
 107 /* 4096-byte page size with 8-bit ECC -- requires 218-byte OOB */
 108 static struct nand_ecclayout oob_4096_ecc8 = {
 109         .eccbytes = 128,
 110         .eccpos = {
 111                 8, 9, 10, 11, 12, 13, 14, 15,
 112                 16, 17, 18, 19, 20, 21, 22, 23,
 113                 24, 25, 26, 27, 28, 29, 30, 31,
 114                 32, 33, 34, 35, 36, 37, 38, 39,
 115                 40, 41, 42, 43, 44, 45, 46, 47,
 116                 48, 49, 50, 51, 52, 53, 54, 55,
 117                 56, 57, 58, 59, 60, 61, 62, 63,
 118                 64, 65, 66, 67, 68, 69, 70, 71,
 119                 72, 73, 74, 75, 76, 77, 78, 79,
 120                 80, 81, 82, 83, 84, 85, 86, 87,
 121                 88, 89, 90, 91, 92, 93, 94, 95,
 122                 96, 97, 98, 99, 100, 101, 102, 103,
 123                 104, 105, 106, 107, 108, 109, 110, 111,
 124                 112, 113, 114, 115, 116, 117, 118, 119,
 125                 120, 121, 122, 123, 124, 125, 126, 127,
 126                 128, 129, 130, 131, 132, 133, 134, 135,
 127         },
 128         .oobfree = { {2, 6}, {136, 82} },
 129 };
 130
 131 /* 8192-byte page size with 4-bit ECC */
 132 static struct nand_ecclayout oob_8192_ecc4 = {
 133         .eccbytes = 128,
 134         .eccpos = {
 135                 8, 9, 10, 11, 12, 13, 14, 15,
 136                 16, 17, 18, 19, 20, 21, 22, 23,
 137                 24, 25, 26, 27, 28, 29, 30, 31,
 138                 32, 33, 34, 35, 36, 37, 38, 39,
 139                 40, 41, 42, 43, 44, 45, 46, 47,
 140                 48, 49, 50, 51, 52, 53, 54, 55,
 141                 56, 57, 58, 59, 60, 61, 62, 63,
 142                 64, 65, 66, 67, 68, 69, 70, 71,
 143                 72, 73, 74, 75, 76, 77, 78, 79,
 144                 80, 81, 82, 83, 84, 85, 86, 87,
 145                 88, 89, 90, 91, 92, 93, 94, 95,
 146                 96, 97, 98, 99, 100, 101, 102, 103,
 147                 104, 105, 106, 107, 108, 109, 110, 111,
 148                 112, 113, 114, 115, 116, 117, 118, 119,
 149                 120, 121, 122, 123, 124, 125, 126, 127,
 150                 128, 129, 130, 131, 132, 133, 134, 135,
 151         },
 152         .oobfree = { {2, 6}, {136, 208} },
 153 };
 154
 155 /* 8192-byte page size with 8-bit ECC -- requires 218-byte OOB */
 156 static struct nand_ecclayout oob_8192_ecc8 = {
 157         .eccbytes = 256,
 158         .eccpos = {
 159                 8, 9, 10, 11, 12, 13, 14, 15,
 160                 16, 17, 18, 19, 20, 21, 22, 23,
 161                 24, 25, 26, 27, 28, 29, 30, 31,
 162                 32, 33, 34, 35, 36, 37, 38, 39,
 163                 40, 41, 42, 43, 44, 45, 46, 47,
 164                 48, 49, 50, 51, 52, 53, 54, 55,
 165                 56, 57, 58, 59, 60, 61, 62, 63,
 166                 64, 65, 66, 67, 68, 69, 70, 71,
 167                 72, 73, 74, 75, 76, 77, 78, 79,
 168                 80, 81, 82, 83, 84, 85, 86, 87,
 169                 88, 89, 90, 91, 92, 93, 94, 95,
 170                 96, 97, 98, 99, 100, 101, 102, 103,
 171                 104, 105, 106, 107, 108, 109, 110, 111,
 172                 112, 113, 114, 115, 116, 117, 118, 119,
 173                 120, 121, 122, 123, 124, 125, 126, 127,
 174                 128, 129, 130, 131, 132, 133, 134, 135,
 175                 136, 137, 138, 139, 140, 141, 142, 143,
 176                 144, 145, 146, 147, 148, 149, 150, 151,
 177                 152, 153, 154, 155, 156, 157, 158, 159,
 178                 160, 161, 162, 163, 164, 165, 166, 167,
 179                 168, 169, 170, 171, 172, 173, 174, 175,
 180                 176, 177, 178, 179, 180, 181, 182, 183,
 181                 184, 185, 186, 187, 188, 189, 190, 191,
 182                 192, 193, 194, 195, 196, 197, 198, 199,
 183                 200, 201, 202, 203, 204, 205, 206, 207,
 184                 208, 209, 210, 211, 212, 213, 214, 215,
 185                 216, 217, 218, 219, 220, 221, 222, 223,
 186                 224, 225, 226, 227, 228, 229, 230, 231,
 187                 232, 233, 234, 235, 236, 237, 238, 239,
 188                 240, 241, 242, 243, 244, 245, 246, 247,
 189                 248, 249, 250, 251, 252, 253, 254, 255,
 190                 256, 257, 258, 259, 260, 261, 262, 263,
 191         },
 192         .oobfree = { {2, 6}, {264, 80} },
 193 };
 194
 195 /*
 196  * Generic flash bbt descriptors
 197  */
 198 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
 199 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
 200
 201 static struct nand_bbt_descr bbt_main_descr = {
 202         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 203                    NAND_BBT_2BIT | NAND_BBT_VERSION,
 204         .offs = 2, /* 0 on 8-bit small page */
 205         .len = 4,
 206         .veroffs = 6,
 207         .maxblocks = 4,
 208         .pattern = bbt_pattern,
 209 };
 210
 211 static struct nand_bbt_descr bbt_mirror_descr = {
 212         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 213                    NAND_BBT_2BIT | NAND_BBT_VERSION,
 214         .offs = 2, /* 0 on 8-bit small page */
 215         .len = 4,
 216         .veroffs = 6,
 217         .maxblocks = 4,
 218         .pattern = mirror_pattern,
 219 };
 220
 221 /*
 222  * Set up the IFC hardware block and page address fields, and the ifc nand
 223  * structure addr field to point to the correct IFC buffer in memory
 224  */
 225 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 226 {
 227         struct nand_chip *chip = mtd->priv;
 228         struct fsl_ifc_mtd *priv = chip->priv;
 229         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 230         struct fsl_ifc *ifc = ctrl->regs;
 231         int buf_num;
 232
 233         ctrl->page = page_addr;
 234
 235         /* Program ROW0/COL0 */
 236         ifc_out32(&ifc->ifc_nand.row0, page_addr);
 237         ifc_out32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column);
 238
 239         buf_num = page_addr & priv->bufnum_mask;
 240
 241         ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
 242         ctrl->index = column;
 243
 244         /* for OOB data point to the second half of the buffer */
 245         if (oob)
 246                 ctrl->index += mtd->writesize;
 247 }
 248
 249 static int is_blank(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
 250                     unsigned int bufnum)
 251 {
 252         struct nand_chip *chip = mtd->priv;
 253         struct fsl_ifc_mtd *priv = chip->priv;
 254         u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2);
 255         u32 __iomem *main = (u32 *)addr;
 256         u8 __iomem *oob = addr + mtd->writesize;
 257         int i;
 258
 259         for (i = 0; i < mtd->writesize / 4; i++) {
 260                 if (__raw_readl(&main[i]) != 0xffffffff)
 261                         return 0;
 262         }
 263
 264         for (i = 0; i < chip->ecc.layout->eccbytes; i++) {
 265                 int pos = chip->ecc.layout->eccpos[i];
 266
 267                 if (__raw_readb(&oob[pos]) != 0xff)
 268                         return 0;
 269         }
 270
 271         return 1;
 272 }
 273
 274 /* returns nonzero if entire page is blank */
 275 static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
 276                           u32 *eccstat, unsigned int bufnum)
 277 {
 278         u32 reg = eccstat[bufnum / 4];
 279         int errors;
 280
 281         errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
 282
 283         return errors;
 284 }
 285
 286 /*
 287  * execute IFC NAND command and wait for it to complete
 288  */
 289 static int fsl_ifc_run_command(struct mtd_info *mtd)
 290 {
 291         struct nand_chip *chip = mtd->priv;
 292         struct fsl_ifc_mtd *priv = chip->priv;
 293         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 294         struct fsl_ifc *ifc = ctrl->regs;
 295         long long end_tick;
 296         u32 eccstat[4];
 297         int i;
 298
 299         /* set the chip select for NAND Transaction */
 300         ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
 301
 302         /* start read/write seq */
 303         ifc_out32(&ifc->ifc_nand.nandseq_strt,
 304                   IFC_NAND_SEQ_STRT_FIR_STRT);
 305
 306         /* wait for NAND Machine complete flag or timeout */
 307         end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
 308
 309         while (end_tick > get_ticks()) {
 310                 ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
 311
 312                 if (ctrl->status & IFC_NAND_EVTER_STAT_OPC)
 313                         break;
 314         }
 315
 316         ifc_out32(&ifc->ifc_nand.nand_evter_stat, ctrl->status);
 317
 318         if (ctrl->status & IFC_NAND_EVTER_STAT_FTOER)
 319                 printf("%s: Flash Time Out Error\n", __func__);
 320         if (ctrl->status & IFC_NAND_EVTER_STAT_WPER)
 321                 printf("%s: Write Protect Error\n", __func__);
 322
 323         if (ctrl->eccread) {
 324                 int errors;
 325                 int bufnum = ctrl->page & priv->bufnum_mask;
 326                 int sector = bufnum * chip->ecc.steps;
 327                 int sector_end = sector + chip->ecc.steps - 1;
 328
 329                 for (i = sector / 4; i <= sector_end / 4; i++)
 330                         eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]);
 331
 332                 for (i = sector; i <= sector_end; i++) {
 333                         errors = check_read_ecc(mtd, ctrl, eccstat, i);
 334
 335                         if (errors == 15) {
 336                                 /*
 337                                  * Uncorrectable error.
 338                                  * OK only if the whole page is blank.
 339                                  *
 340                                  * We disable ECCER reporting due to erratum
 341                                  * IFC-A002770 -- so report it now if we
 342                                  * see an uncorrectable error in ECCSTAT.
 343                                  */
 344                                 if (!is_blank(mtd, ctrl, bufnum))
 345                                         ctrl->status |=
 346                                                 IFC_NAND_EVTER_STAT_ECCER;
 347                                 break;
 348                         }
 349
 350                         mtd->ecc_stats.corrected += errors;
 351                 }
 352
 353                 ctrl->eccread = 0;
 354         }
 355
 356         /* returns 0 on success otherwise non-zero) */
 357         return ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO;
 358 }
 359
 360 static void fsl_ifc_do_read(struct nand_chip *chip,
 361                             int oob,
 362                             struct mtd_info *mtd)
 363 {
 364         struct fsl_ifc_mtd *priv = chip->priv;
 365         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 366         struct fsl_ifc *ifc = ctrl->regs;
 367
 368         /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
 369         if (mtd->writesize > 512) {
 370                 ifc_out32(&ifc->ifc_nand.nand_fir0,
 371                           (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 372                           (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 373                           (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
 374                           (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
 375                           (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT));
 376                 ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
 377
 378                 ifc_out32(&ifc->ifc_nand.nand_fcr0,
 379                           (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
 380                           (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
 381         } else {
 382                 ifc_out32(&ifc->ifc_nand.nand_fir0,
 383                           (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 384                           (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 385                           (IFC_FIR_OP_RA0  << IFC_NAND_FIR0_OP2_SHIFT) |
 386                           (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT));
 387
 388                 if (oob)
 389                         ifc_out32(&ifc->ifc_nand.nand_fcr0,
 390                                   NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT);
 391                 else
 392                         ifc_out32(&ifc->ifc_nand.nand_fcr0,
 393                                   NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
 394         }
 395 }
 396
 397 /* cmdfunc send commands to the IFC NAND Machine */
 398 static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 399                              int column, int page_addr)
 400 {
 401         struct nand_chip *chip = mtd->priv;
 402         struct fsl_ifc_mtd *priv = chip->priv;
 403         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 404         struct fsl_ifc *ifc = ctrl->regs;
 405
 406         /* clear the read buffer */
 407         ctrl->read_bytes = 0;
 408         if (command != NAND_CMD_PAGEPROG)
 409                 ctrl->index = 0;
 410
 411         switch (command) {
 412         /* READ0 read the entire buffer to use hardware ECC. */
 413         case NAND_CMD_READ0: {
 414                 ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
 415                 set_addr(mtd, 0, page_addr, 0);
 416
 417                 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 418                 ctrl->index += column;
 419
 420                 if (chip->ecc.mode == NAND_ECC_HW)
 421                         ctrl->eccread = 1;
 422
 423                 fsl_ifc_do_read(chip, 0, mtd);
 424                 fsl_ifc_run_command(mtd);
 425                 return;
 426         }
 427
 428         /* READOOB reads only the OOB because no ECC is performed. */
 429         case NAND_CMD_READOOB:
 430                 ifc_out32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column);
 431                 set_addr(mtd, column, page_addr, 1);
 432
 433                 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 434
 435                 fsl_ifc_do_read(chip, 1, mtd);
 436                 fsl_ifc_run_command(mtd);
 437
 438                 return;
 439
 440         /* READID must read all possible bytes while CEB is active */
 441         case NAND_CMD_READID:
 442         case NAND_CMD_PARAM: {
 443                 int timing = IFC_FIR_OP_RB;
 444                 if (command == NAND_CMD_PARAM)
 445                         timing = IFC_FIR_OP_RBCD;
 446
 447                 ifc_out32(&ifc->ifc_nand.nand_fir0,
 448                           (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 449                           (IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
 450                           (timing << IFC_NAND_FIR0_OP2_SHIFT));
 451                 ifc_out32(&ifc->ifc_nand.nand_fcr0,
 452                           command << IFC_NAND_FCR0_CMD0_SHIFT);
 453                 ifc_out32(&ifc->ifc_nand.row3, column);
 454
 455                 /*
 456                  * although currently it's 8 bytes for READID, we always read
 457                  * the maximum 256 bytes(for PARAM)
 458                  */
 459                 ifc_out32(&ifc->ifc_nand.nand_fbcr, 256);
 460                 ctrl->read_bytes = 256;
 461
 462                 set_addr(mtd, 0, 0, 0);
 463                 fsl_ifc_run_command(mtd);
 464                 return;
 465         }
 466
 467         /* ERASE1 stores the block and page address */
 468         case NAND_CMD_ERASE1:
 469                 set_addr(mtd, 0, page_addr, 0);
 470                 return;
 471
 472         /* ERASE2 uses the block and page address from ERASE1 */
 473         case NAND_CMD_ERASE2:
 474                 ifc_out32(&ifc->ifc_nand.nand_fir0,
 475                           (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 476                           (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 477                           (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT));
 478
 479                 ifc_out32(&ifc->ifc_nand.nand_fcr0,
 480                           (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
 481                           (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT));
 482
 483                 ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
 484                 ctrl->read_bytes = 0;
 485                 fsl_ifc_run_command(mtd);
 486                 return;
 487
 488         /* SEQIN sets up the addr buffer and all registers except the length */
 489         case NAND_CMD_SEQIN: {
 490                 u32 nand_fcr0;
 491                 ctrl->column = column;
 492                 ctrl->oob = 0;
 493
 494                 if (mtd->writesize > 512) {
 495                         nand_fcr0 =
 496                                 (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
 497                                 (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) |
 498                                 (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);
 499
 500                         ifc_out32(&ifc->ifc_nand.nand_fir0,
 501                                   (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 502                                   (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
 503                                   (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
 504                                   (IFC_FIR_OP_WBCD  <<
 505                                                 IFC_NAND_FIR0_OP3_SHIFT) |
 506                                   (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT));
 507                         ifc_out32(&ifc->ifc_nand.nand_fir1,
 508                                   (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
 509                                   (IFC_FIR_OP_RDSTAT <<
 510                                         IFC_NAND_FIR1_OP6_SHIFT) |
 511                                   (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT));
 512                 } else {
 513                         nand_fcr0 = ((NAND_CMD_PAGEPROG <<
 514                                         IFC_NAND_FCR0_CMD1_SHIFT) |
 515                                     (NAND_CMD_SEQIN <<
 516                                         IFC_NAND_FCR0_CMD2_SHIFT) |
 517                                     (NAND_CMD_STATUS <<
 518                                         IFC_NAND_FCR0_CMD3_SHIFT));
 519
 520                         ifc_out32(&ifc->ifc_nand.nand_fir0,
 521                                   (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 522                                   (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
 523                                   (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
 524                                   (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
 525                                   (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT));
 526                         ifc_out32(&ifc->ifc_nand.nand_fir1,
 527                                   (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
 528                                   (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
 529                                   (IFC_FIR_OP_RDSTAT <<
 530                                         IFC_NAND_FIR1_OP7_SHIFT) |
 531                                   (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT));
 532
 533                         if (column >= mtd->writesize)
 534                                 nand_fcr0 |=
 535                                 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT;
 536                         else
 537                                 nand_fcr0 |=
 538                                 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
 539                 }
 540
 541                 if (column >= mtd->writesize) {
 542                         /* OOB area --> READOOB */
 543                         column -= mtd->writesize;
 544                         ctrl->oob = 1;
 545                 }
 546                 ifc_out32(&ifc->ifc_nand.nand_fcr0, nand_fcr0);
 547                 set_addr(mtd, column, page_addr, ctrl->oob);
 548                 return;
 549         }
 550
 551         /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
 552         case NAND_CMD_PAGEPROG:
 553                 if (ctrl->oob)
 554                         ifc_out32(&ifc->ifc_nand.nand_fbcr,
 555                                   ctrl->index - ctrl->column);
 556                 else
 557                         ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
 558
 559                 fsl_ifc_run_command(mtd);
 560                 return;
 561
 562         case NAND_CMD_STATUS:
 563                 ifc_out32(&ifc->ifc_nand.nand_fir0,
 564                           (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 565                           (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT));
 566                 ifc_out32(&ifc->ifc_nand.nand_fcr0,
 567                           NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT);
 568                 ifc_out32(&ifc->ifc_nand.nand_fbcr, 1);
 569                 set_addr(mtd, 0, 0, 0);
 570                 ctrl->read_bytes = 1;
 571
 572                 fsl_ifc_run_command(mtd);
 573
 574                 /* Chip sometimes reporting write protect even when it's not */
 575                 out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
 576                 return;
 577
 578         case NAND_CMD_RESET:
 579                 ifc_out32(&ifc->ifc_nand.nand_fir0,
 580                           IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT);
 581                 ifc_out32(&ifc->ifc_nand.nand_fcr0,
 582                           NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT);
 583                 fsl_ifc_run_command(mtd);
 584                 return;
 585
 586         default:
 587                 printf("%s: error, unsupported command 0x%x.\n",
 588                         __func__, command);
 589         }
 590 }
 591
 592 /*
 593  * Write buf to the IFC NAND Controller Data Buffer
 594  */
 595 static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 596 {
 597         struct nand_chip *chip = mtd->priv;
 598         struct fsl_ifc_mtd *priv = chip->priv;
 599         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 600         unsigned int bufsize = mtd->writesize + mtd->oobsize;
 601
 602         if (len <= 0) {
 603                 printf("%s of %d bytes", __func__, len);
 604                 ctrl->status = 0;
 605                 return;
 606         }
 607
 608         if ((unsigned int)len > bufsize - ctrl->index) {
 609                 printf("%s beyond end of buffer "
 610                        "(%d requested, %u available)\n",
 611                         __func__, len, bufsize - ctrl->index);
 612                 len = bufsize - ctrl->index;
 613         }
 614
 615         memcpy_toio(&ctrl->addr[ctrl->index], buf, len);
 616         ctrl->index += len;
 617 }
 618
 619 /*
 620  * read a byte from either the IFC hardware buffer if it has any data left
 621  * otherwise issue a command to read a single byte.
 622  */
 623 static u8 fsl_ifc_read_byte(struct mtd_info *mtd)
 624 {
 625         struct nand_chip *chip = mtd->priv;
 626         struct fsl_ifc_mtd *priv = chip->priv;
 627         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 628
 629         /* If there are still bytes in the IFC buffer, then use the
 630          * next byte. */
 631         if (ctrl->index < ctrl->read_bytes)
 632                 return in_8(&ctrl->addr[ctrl->index++]);
 633
 634         printf("%s beyond end of buffer\n", __func__);
 635         return ERR_BYTE;
 636 }
 637
 638 /*
 639  * Read two bytes from the IFC hardware buffer
 640  * read function for 16-bit buswith
 641  */
 642 static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
 643 {
 644         struct nand_chip *chip = mtd->priv;
 645         struct fsl_ifc_mtd *priv = chip->priv;
 646         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 647         uint16_t data;
 648
 649         /*
 650          * If there are still bytes in the IFC buffer, then use the
 651          * next byte.
 652          */
 653         if (ctrl->index < ctrl->read_bytes) {
 654                 data = ifc_in16((uint16_t *)&ctrl->
 655                                  addr[ctrl->index]);
 656                 ctrl->index += 2;
 657                 return (uint8_t)data;
 658         }
 659
 660         printf("%s beyond end of buffer\n", __func__);
 661         return ERR_BYTE;
 662 }
 663
 664 /*
 665  * Read from the IFC Controller Data Buffer
 666  */
 667 static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 668 {
 669         struct nand_chip *chip = mtd->priv;
 670         struct fsl_ifc_mtd *priv = chip->priv;
 671         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 672         int avail;
 673
 674         if (len < 0)
 675                 return;
 676
 677         avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
 678         memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail);
 679         ctrl->index += avail;
 680
 681         if (len > avail)
 682                 printf("%s beyond end of buffer "
 683                        "(%d requested, %d available)\n",
 684                        __func__, len, avail);
 685 }
 686
 687 #if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
 688 /*
 689  * Verify buffer against the IFC Controller Data Buffer
 690  */
 691 static int fsl_ifc_verify_buf(struct mtd_info *mtd,
 692                                const u_char *buf, int len)
 693 {
 694         struct nand_chip *chip = mtd->priv;
 695         struct fsl_ifc_mtd *priv = chip->priv;
 696         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 697         int i;
 698
 699         if (len < 0) {
 700                 printf("%s of %d bytes", __func__, len);
 701                 return -EINVAL;
 702         }
 703
 704         if ((unsigned int)len > ctrl->read_bytes - ctrl->index) {
 705                 printf("%s beyond end of buffer "
 706                        "(%d requested, %u available)\n",
 707                        __func__, len, ctrl->read_bytes - ctrl->index);
 708
 709                 ctrl->index = ctrl->read_bytes;
 710                 return -EINVAL;
 711         }
 712
 713         for (i = 0; i < len; i++)
 714                 if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i])
 715                         break;
 716
 717         ctrl->index += len;
 718         return i == len && ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO;
 719 }
 720 #endif
 721
 722 /* This function is called after Program and Erase Operations to
 723  * check for success or failure.
 724  */
 725 static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 726 {
 727         struct fsl_ifc_mtd *priv = chip->priv;
 728         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 729         struct fsl_ifc *ifc = ctrl->regs;
 730         u32 nand_fsr;
 731
 732         if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
 733                 return NAND_STATUS_FAIL;
 734
 735         /* Use READ_STATUS command, but wait for the device to be ready */
 736         ifc_out32(&ifc->ifc_nand.nand_fir0,
 737                   (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 738                   (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT));
 739         ifc_out32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS <<
 740                   IFC_NAND_FCR0_CMD0_SHIFT);
 741         ifc_out32(&ifc->ifc_nand.nand_fbcr, 1);
 742         set_addr(mtd, 0, 0, 0);
 743         ctrl->read_bytes = 1;
 744
 745         fsl_ifc_run_command(mtd);
 746
 747         if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
 748                 return NAND_STATUS_FAIL;
 749
 750         nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
 751
 752         /* Chip sometimes reporting write protect even when it's not */
 753         nand_fsr = nand_fsr | NAND_STATUS_WP;
 754         return nand_fsr;
 755 }
 756
 757 static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
 758                              uint8_t *buf, int oob_required, int page)
 759 {
 760         struct fsl_ifc_mtd *priv = chip->priv;
 761         struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 762
 763         fsl_ifc_read_buf(mtd, buf, mtd->writesize);
 764         fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
 765
 766         if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
 767                 mtd->ecc_stats.failed++;
 768
 769         return 0;
 770 }
 771
 772 /* ECC will be calculated automatically, and errors will be detected in
 773  * waitfunc.
 774  */
 775 static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 776                                const uint8_t *buf, int oob_required)
 777 {
 778         fsl_ifc_write_buf(mtd, buf, mtd->writesize);
 779         fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 780
 781         return 0;
 782 }
 783
 784 static void fsl_ifc_ctrl_init(void)
 785 {
 786         ifc_ctrl = kzalloc(sizeof(*ifc_ctrl), GFP_KERNEL);
 787         if (!ifc_ctrl)
 788                 return;
 789
 790         ifc_ctrl->regs = IFC_BASE_ADDR;
 791
 792         /* clear event registers */
 793         ifc_out32(&ifc_ctrl->regs->ifc_nand.nand_evter_stat, ~0U);
 794         ifc_out32(&ifc_ctrl->regs->ifc_nand.pgrdcmpl_evt_stat, ~0U);
 795
 796         /* Enable error and event for any detected errors */
 797         ifc_out32(&ifc_ctrl->regs->ifc_nand.nand_evter_en,
 798                   IFC_NAND_EVTER_EN_OPC_EN |
 799                   IFC_NAND_EVTER_EN_PGRDCMPL_EN |
 800                   IFC_NAND_EVTER_EN_FTOER_EN |
 801                   IFC_NAND_EVTER_EN_WPER_EN);
 802
 803         ifc_out32(&ifc_ctrl->regs->ifc_nand.ncfgr, 0x0);
 804 }
 805
 806 static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
 807 {
 808 }
 809
 810 static int fsl_ifc_sram_init(uint32_t ver)
 811 {
 812         struct fsl_ifc *ifc = ifc_ctrl->regs;
 813         uint32_t cs = 0, csor = 0, csor_8k = 0, csor_ext = 0;
 814         uint32_t ncfgr = 0;
 815         long long end_tick;
 816
 817         if (ver > FSL_IFC_V1_1_0) {
 818                 ncfgr = ifc_in32(&ifc->ifc_nand.ncfgr);
 819                 ifc_out32(&ifc->ifc_nand.ncfgr, ncfgr | IFC_NAND_SRAM_INIT_EN);
 820
 821                 /* wait for  SRAM_INIT bit to be clear or timeout */
 822                 end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
 823                 while (end_tick > get_ticks()) {
 824                         ifc_ctrl->status =
 825                                 ifc_in32(&ifc->ifc_nand.nand_evter_stat);
 826
 827                         if (!(ifc_ctrl->status & IFC_NAND_SRAM_INIT_EN))
 828                                 return 0;
 829                 }
 830                 printf("fsl-ifc: Failed to Initialise SRAM\n");
 831                 return 1;
 832         }
 833
 834         cs = ifc_ctrl->cs_nand >> IFC_NAND_CSEL_SHIFT;
 835
 836         /* Save CSOR and CSOR_ext */
 837         csor = ifc_in32(&ifc_ctrl->regs->csor_cs[cs].csor);
 838         csor_ext = ifc_in32(&ifc_ctrl->regs->csor_cs[cs].csor_ext);
 839
 840         /* chage PageSize 8K and SpareSize 1K*/
 841         csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
 842         ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor, csor_8k);
 843         ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, 0x0000400);
 844
 845         /* READID */
 846         ifc_out32(&ifc->ifc_nand.nand_fir0,
 847                   (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
 848                   (IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
 849                   (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT));
 850         ifc_out32(&ifc->ifc_nand.nand_fcr0,
 851                   NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT);
 852         ifc_out32(&ifc->ifc_nand.row3, 0x0);
 853
 854         ifc_out32(&ifc->ifc_nand.nand_fbcr, 0x0);
 855
 856         /* Program ROW0/COL0 */
 857         ifc_out32(&ifc->ifc_nand.row0, 0x0);
 858         ifc_out32(&ifc->ifc_nand.col0, 0x0);
 859
 860         /* set the chip select for NAND Transaction */
 861         ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
 862
 863         /* start read seq */
 864         ifc_out32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
 865
 866         /* wait for NAND Machine complete flag or timeout */
 867         end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
 868
 869         while (end_tick > get_ticks()) {
 870                 ifc_ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
 871
 872                 if (ifc_ctrl->status & IFC_NAND_EVTER_STAT_OPC)
 873                         break;
 874         }
 875
 876         if (ifc_ctrl->status != IFC_NAND_EVTER_STAT_OPC) {
 877                 printf("fsl-ifc: Failed to Initialise SRAM\n");
 878                 return 1;
 879         }
 880
 881         ifc_out32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status);
 882
 883         /* Restore CSOR and CSOR_ext */
 884         ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor, csor);
 885         ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext);
 886
 887         return 0;
 888 }
 889
 890 static int fsl_ifc_chip_init(int devnum, u8 *addr)
 891 {
 892         struct mtd_info *mtd = &nand_info[devnum];
 893         struct nand_chip *nand;
 894         struct fsl_ifc_mtd *priv;
 895         struct nand_ecclayout *layout;
 896         uint32_t cspr = 0, csor = 0, ver = 0;
 897         int ret = 0;
 898
 899         if (!ifc_ctrl) {
 900                 fsl_ifc_ctrl_init();
 901                 if (!ifc_ctrl)
 902                         return -1;
 903         }
 904
 905         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 906         if (!priv)
 907                 return -ENOMEM;
 908
 909         priv->ctrl = ifc_ctrl;
 910         priv->vbase = addr;
 911
 912         /* Find which chip select it is connected to.
 913          */
 914         for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
 915                 phys_addr_t phys_addr = virt_to_phys(addr);
 916
 917                 cspr = ifc_in32(&ifc_ctrl->regs->cspr_cs[priv->bank].cspr);
 918                 csor = ifc_in32(&ifc_ctrl->regs->csor_cs[priv->bank].csor);
 919
 920                 if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND &&
 921                     (cspr & CSPR_BA) == CSPR_PHYS_ADDR(phys_addr)) {
 922                         ifc_ctrl->cs_nand = priv->bank << IFC_NAND_CSEL_SHIFT;
 923                         break;
 924                 }
 925         }
 926
 927         if (priv->bank >= MAX_BANKS) {
 928                 printf("%s: address did not match any "
 929                        "chip selects\n", __func__);
 930                 kfree(priv);
 931                 return -ENODEV;
 932         }
 933
 934         nand = &priv->chip;
 935         mtd->priv = nand;
 936
 937         ifc_ctrl->chips[priv->bank] = priv;
 938
 939         /* fill in nand_chip structure */
 940         /* set up function call table */
 941
 942         nand->write_buf = fsl_ifc_write_buf;
 943         nand->read_buf = fsl_ifc_read_buf;
 944 #if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
 945         nand->verify_buf = fsl_ifc_verify_buf;
 946 #endif
 947         nand->select_chip = fsl_ifc_select_chip;
 948         nand->cmdfunc = fsl_ifc_cmdfunc;
 949         nand->waitfunc = fsl_ifc_wait;
 950
 951         /* set up nand options */
 952         nand->bbt_td = &bbt_main_descr;
 953         nand->bbt_md = &bbt_mirror_descr;
 954
 955         /* set up nand options */
 956         nand->options = NAND_NO_SUBPAGE_WRITE;
 957         nand->bbt_options = NAND_BBT_USE_FLASH;
 958
 959         if (cspr & CSPR_PORT_SIZE_16) {
 960                 nand->read_byte = fsl_ifc_read_byte16;
 961                 nand->options |= NAND_BUSWIDTH_16;
 962         } else {
 963                 nand->read_byte = fsl_ifc_read_byte;
 964         }
 965
 966         nand->controller = &ifc_ctrl->controller;
 967         nand->priv = priv;
 968
 969         nand->ecc.read_page = fsl_ifc_read_page;
 970         nand->ecc.write_page = fsl_ifc_write_page;
 971
 972         /* Hardware generates ECC per 512 Bytes */
 973         nand->ecc.size = 512;
 974         nand->ecc.bytes = 8;
 975
 976         switch (csor & CSOR_NAND_PGS_MASK) {
 977         case CSOR_NAND_PGS_512:
 978                 if (nand->options & NAND_BUSWIDTH_16) {
 979                         layout = &oob_512_16bit_ecc4;
 980                 } else {
 981                         layout = &oob_512_8bit_ecc4;
 982
 983                         /* Avoid conflict with bad block marker */
 984                         bbt_main_descr.offs = 0;
 985                         bbt_mirror_descr.offs = 0;
 986                 }
 987
 988                 nand->ecc.strength = 4;
 989                 priv->bufnum_mask = 15;
 990                 break;
 991
 992         case CSOR_NAND_PGS_2K:
 993                 layout = &oob_2048_ecc4;
 994                 nand->ecc.strength = 4;
 995                 priv->bufnum_mask = 3;
 996                 break;
 997
 998         case CSOR_NAND_PGS_4K:
 999                 if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
1000                     CSOR_NAND_ECC_MODE_4) {
1001                         layout = &oob_4096_ecc4;
1002                         nand->ecc.strength = 4;
1003                 } else {
1004                         layout = &oob_4096_ecc8;
1005                         nand->ecc.strength = 8;
1006                         nand->ecc.bytes = 16;
1007                 }
1008
1009                 priv->bufnum_mask = 1;
1010                 break;
1011
1012         case CSOR_NAND_PGS_8K:
1013                 if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
1014                     CSOR_NAND_ECC_MODE_4) {
1015                         layout = &oob_8192_ecc4;
1016                         nand->ecc.strength = 4;
1017                 } else {
1018                         layout = &oob_8192_ecc8;
1019                         nand->ecc.strength = 8;
1020                         nand->ecc.bytes = 16;
1021                 }
1022
1023                 priv->bufnum_mask = 0;
1024                 break;
1025
1026
1027         default:
1028                 printf("ifc nand: bad csor %#x: bad page size\n", csor);
1029                 return -ENODEV;
1030         }
1031
1032         /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
1033         if (csor & CSOR_NAND_ECC_DEC_EN) {
1034                 nand->ecc.mode = NAND_ECC_HW;
1035                 nand->ecc.layout = layout;
1036         } else {
1037                 nand->ecc.mode = NAND_ECC_SOFT;
1038         }
1039
1040         ver = ifc_in32(&ifc_ctrl->regs->ifc_rev);
1041         if (ver >= FSL_IFC_V1_1_0)
1042                 ret = fsl_ifc_sram_init(ver);
1043         if (ret)
1044                 return ret;
1045
1046         if (ver >= FSL_IFC_V2_0_0)
1047                 priv->bufnum_mask = (priv->bufnum_mask * 2) + 1;
1048
1049         ret = nand_scan_ident(mtd, 1, NULL);
1050         if (ret)
1051                 return ret;
1052
1053         ret = nand_scan_tail(mtd);
1054         if (ret)
1055                 return ret;
1056
1057         ret = nand_register(devnum);
1058         if (ret)
1059                 return ret;
1060         return 0;
1061 }
1062
1063 #ifndef CONFIG_SYS_NAND_BASE_LIST
1064 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
1065 #endif
1066
1067 static unsigned long base_address[CONFIG_SYS_MAX_NAND_DEVICE] =
1068         CONFIG_SYS_NAND_BASE_LIST;
1069
1070 void board_nand_init(void)
1071 {
1072         int i;
1073
1074         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
1075                 fsl_ifc_chip_init(i, (u8 *)base_address[i]);
1076 }