1 /* Integrated Flash Controller NAND Machine Driver
3 * Copyright (c) 2012 Freescale Semiconductor, Inc
5 * Authors: Dipen Dudhat <Dipen.Dudhat@freescale.com>
7 * SPDX-License-Identifier: GPL-2.0+
14 #include <linux/mtd/mtd.h>
15 #include <linux/mtd/nand.h>
16 #include <linux/mtd/nand_ecc.h>
19 #include <asm/errno.h>
22 #ifndef CONFIG_SYS_FSL_IFC_BANK_COUNT
23 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
26 #define MAX_BANKS CONFIG_SYS_FSL_IFC_BANK_COUNT
27 #define ERR_BYTE 0xFF /* Value returned for read bytes
32 /* mtd information per set */
34 struct nand_chip chip;
35 struct fsl_ifc_ctrl *ctrl;
38 int bank; /* Chip select bank number */
39 unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
40 u8 __iomem *vbase; /* Chip select base virtual address */
43 /* overview of the fsl ifc controller */
45 struct nand_hw_control controller;
46 struct fsl_ifc_mtd *chips[MAX_BANKS];
50 uint8_t __iomem *addr; /* Address of assigned IFC buffer */
51 unsigned int cs_nand; /* On which chipsel NAND is connected */
52 unsigned int page; /* Last page written to / read from */
53 unsigned int read_bytes; /* Number of bytes read during command */
54 unsigned int column; /* Saved column from SEQIN */
55 unsigned int index; /* Pointer to next byte to 'read' */
56 unsigned int status; /* status read from NEESR after last op */
57 unsigned int oob; /* Non zero if operating on OOB data */
58 unsigned int eccread; /* Non zero for a full-page ECC read */
61 static struct fsl_ifc_ctrl *ifc_ctrl;
63 /* 512-byte page with 4-bit ECC, 8-bit */
64 static struct nand_ecclayout oob_512_8bit_ecc4 = {
66 .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
67 .oobfree = { {0, 5}, {6, 2} },
70 /* 512-byte page with 4-bit ECC, 16-bit */
71 static struct nand_ecclayout oob_512_16bit_ecc4 = {
73 .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
74 .oobfree = { {2, 6}, },
77 /* 2048-byte page size with 4-bit ECC */
78 static struct nand_ecclayout oob_2048_ecc4 = {
81 8, 9, 10, 11, 12, 13, 14, 15,
82 16, 17, 18, 19, 20, 21, 22, 23,
83 24, 25, 26, 27, 28, 29, 30, 31,
84 32, 33, 34, 35, 36, 37, 38, 39,
86 .oobfree = { {2, 6}, {40, 24} },
89 /* 4096-byte page size with 4-bit ECC */
90 static struct nand_ecclayout oob_4096_ecc4 = {
93 8, 9, 10, 11, 12, 13, 14, 15,
94 16, 17, 18, 19, 20, 21, 22, 23,
95 24, 25, 26, 27, 28, 29, 30, 31,
96 32, 33, 34, 35, 36, 37, 38, 39,
97 40, 41, 42, 43, 44, 45, 46, 47,
98 48, 49, 50, 51, 52, 53, 54, 55,
99 56, 57, 58, 59, 60, 61, 62, 63,
100 64, 65, 66, 67, 68, 69, 70, 71,
102 .oobfree = { {2, 6}, {72, 56} },
105 /* 4096-byte page size with 8-bit ECC -- requires 218-byte OOB */
106 static struct nand_ecclayout oob_4096_ecc8 = {
109 8, 9, 10, 11, 12, 13, 14, 15,
110 16, 17, 18, 19, 20, 21, 22, 23,
111 24, 25, 26, 27, 28, 29, 30, 31,
112 32, 33, 34, 35, 36, 37, 38, 39,
113 40, 41, 42, 43, 44, 45, 46, 47,
114 48, 49, 50, 51, 52, 53, 54, 55,
115 56, 57, 58, 59, 60, 61, 62, 63,
116 64, 65, 66, 67, 68, 69, 70, 71,
117 72, 73, 74, 75, 76, 77, 78, 79,
118 80, 81, 82, 83, 84, 85, 86, 87,
119 88, 89, 90, 91, 92, 93, 94, 95,
120 96, 97, 98, 99, 100, 101, 102, 103,
121 104, 105, 106, 107, 108, 109, 110, 111,
122 112, 113, 114, 115, 116, 117, 118, 119,
123 120, 121, 122, 123, 124, 125, 126, 127,
124 128, 129, 130, 131, 132, 133, 134, 135,
126 .oobfree = { {2, 6}, {136, 82} },
129 /* 8192-byte page size with 4-bit ECC */
130 static struct nand_ecclayout oob_8192_ecc4 = {
133 8, 9, 10, 11, 12, 13, 14, 15,
134 16, 17, 18, 19, 20, 21, 22, 23,
135 24, 25, 26, 27, 28, 29, 30, 31,
136 32, 33, 34, 35, 36, 37, 38, 39,
137 40, 41, 42, 43, 44, 45, 46, 47,
138 48, 49, 50, 51, 52, 53, 54, 55,
139 56, 57, 58, 59, 60, 61, 62, 63,
140 64, 65, 66, 67, 68, 69, 70, 71,
141 72, 73, 74, 75, 76, 77, 78, 79,
142 80, 81, 82, 83, 84, 85, 86, 87,
143 88, 89, 90, 91, 92, 93, 94, 95,
144 96, 97, 98, 99, 100, 101, 102, 103,
145 104, 105, 106, 107, 108, 109, 110, 111,
146 112, 113, 114, 115, 116, 117, 118, 119,
147 120, 121, 122, 123, 124, 125, 126, 127,
148 128, 129, 130, 131, 132, 133, 134, 135,
150 .oobfree = { {2, 6}, {136, 208} },
153 /* 8192-byte page size with 8-bit ECC -- requires 218-byte OOB */
154 static struct nand_ecclayout oob_8192_ecc8 = {
157 8, 9, 10, 11, 12, 13, 14, 15,
158 16, 17, 18, 19, 20, 21, 22, 23,
159 24, 25, 26, 27, 28, 29, 30, 31,
160 32, 33, 34, 35, 36, 37, 38, 39,
161 40, 41, 42, 43, 44, 45, 46, 47,
162 48, 49, 50, 51, 52, 53, 54, 55,
163 56, 57, 58, 59, 60, 61, 62, 63,
164 64, 65, 66, 67, 68, 69, 70, 71,
165 72, 73, 74, 75, 76, 77, 78, 79,
166 80, 81, 82, 83, 84, 85, 86, 87,
167 88, 89, 90, 91, 92, 93, 94, 95,
168 96, 97, 98, 99, 100, 101, 102, 103,
169 104, 105, 106, 107, 108, 109, 110, 111,
170 112, 113, 114, 115, 116, 117, 118, 119,
171 120, 121, 122, 123, 124, 125, 126, 127,
172 128, 129, 130, 131, 132, 133, 134, 135,
173 136, 137, 138, 139, 140, 141, 142, 143,
174 144, 145, 146, 147, 148, 149, 150, 151,
175 152, 153, 154, 155, 156, 157, 158, 159,
176 160, 161, 162, 163, 164, 165, 166, 167,
177 168, 169, 170, 171, 172, 173, 174, 175,
178 176, 177, 178, 179, 180, 181, 182, 183,
179 184, 185, 186, 187, 188, 189, 190, 191,
180 192, 193, 194, 195, 196, 197, 198, 199,
181 200, 201, 202, 203, 204, 205, 206, 207,
182 208, 209, 210, 211, 212, 213, 214, 215,
183 216, 217, 218, 219, 220, 221, 222, 223,
184 224, 225, 226, 227, 228, 229, 230, 231,
185 232, 233, 234, 235, 236, 237, 238, 239,
186 240, 241, 242, 243, 244, 245, 246, 247,
187 248, 249, 250, 251, 252, 253, 254, 255,
188 256, 257, 258, 259, 260, 261, 262, 263,
190 .oobfree = { {2, 6}, {264, 80} },
194 * Generic flash bbt descriptors
196 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
197 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
199 static struct nand_bbt_descr bbt_main_descr = {
200 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
201 NAND_BBT_2BIT | NAND_BBT_VERSION,
202 .offs = 2, /* 0 on 8-bit small page */
206 .pattern = bbt_pattern,
209 static struct nand_bbt_descr bbt_mirror_descr = {
210 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
211 NAND_BBT_2BIT | NAND_BBT_VERSION,
212 .offs = 2, /* 0 on 8-bit small page */
216 .pattern = mirror_pattern,
220 * Set up the IFC hardware block and page address fields, and the ifc nand
221 * structure addr field to point to the correct IFC buffer in memory
223 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
225 struct nand_chip *chip = mtd->priv;
226 struct fsl_ifc_mtd *priv = chip->priv;
227 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
228 struct fsl_ifc *ifc = ctrl->regs;
231 ctrl->page = page_addr;
233 /* Program ROW0/COL0 */
234 ifc_out32(&ifc->ifc_nand.row0, page_addr);
235 ifc_out32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column);
237 buf_num = page_addr & priv->bufnum_mask;
239 ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
240 ctrl->index = column;
242 /* for OOB data point to the second half of the buffer */
244 ctrl->index += mtd->writesize;
247 static int is_blank(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
250 struct nand_chip *chip = mtd->priv;
251 struct fsl_ifc_mtd *priv = chip->priv;
252 u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2);
253 u32 __iomem *main = (u32 *)addr;
254 u8 __iomem *oob = addr + mtd->writesize;
257 for (i = 0; i < mtd->writesize / 4; i++) {
258 if (__raw_readl(&main[i]) != 0xffffffff)
262 for (i = 0; i < chip->ecc.layout->eccbytes; i++) {
263 int pos = chip->ecc.layout->eccpos[i];
265 if (__raw_readb(&oob[pos]) != 0xff)
272 /* returns nonzero if entire page is blank */
273 static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
274 u32 *eccstat, unsigned int bufnum)
276 u32 reg = eccstat[bufnum / 4];
279 errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
285 * execute IFC NAND command and wait for it to complete
287 static int fsl_ifc_run_command(struct mtd_info *mtd)
289 struct nand_chip *chip = mtd->priv;
290 struct fsl_ifc_mtd *priv = chip->priv;
291 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
292 struct fsl_ifc *ifc = ctrl->regs;
293 u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
295 u32 eccstat[4] = {0};
298 /* set the chip select for NAND Transaction */
299 ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
301 /* start read/write seq */
302 ifc_out32(&ifc->ifc_nand.nandseq_strt,
303 IFC_NAND_SEQ_STRT_FIR_STRT);
305 /* wait for NAND Machine complete flag or timeout */
306 time_start = get_timer(0);
308 while (get_timer(time_start) < timeo) {
309 ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
311 if (ctrl->status & IFC_NAND_EVTER_STAT_OPC)
315 ifc_out32(&ifc->ifc_nand.nand_evter_stat, ctrl->status);
317 if (ctrl->status & IFC_NAND_EVTER_STAT_FTOER)
318 printf("%s: Flash Time Out Error\n", __func__);
319 if (ctrl->status & IFC_NAND_EVTER_STAT_WPER)
320 printf("%s: Write Protect Error\n", __func__);
324 int bufnum = ctrl->page & priv->bufnum_mask;
325 int sector = bufnum * chip->ecc.steps;
326 int sector_end = sector + chip->ecc.steps - 1;
328 for (i = sector / 4; i <= sector_end / 4; i++)
329 eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]);
331 for (i = sector; i <= sector_end; i++) {
332 errors = check_read_ecc(mtd, ctrl, eccstat, i);
336 * Uncorrectable error.
337 * OK only if the whole page is blank.
339 * We disable ECCER reporting due to erratum
340 * IFC-A002770 -- so report it now if we
341 * see an uncorrectable error in ECCSTAT.
343 if (!is_blank(mtd, ctrl, bufnum))
345 IFC_NAND_EVTER_STAT_ECCER;
349 mtd->ecc_stats.corrected += errors;
355 /* returns 0 on success otherwise non-zero) */
356 return ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO;
359 static void fsl_ifc_do_read(struct nand_chip *chip,
361 struct mtd_info *mtd)
363 struct fsl_ifc_mtd *priv = chip->priv;
364 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
365 struct fsl_ifc *ifc = ctrl->regs;
367 /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
368 if (mtd->writesize > 512) {
369 ifc_out32(&ifc->ifc_nand.nand_fir0,
370 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
371 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
372 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
373 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
374 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT));
375 ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
377 ifc_out32(&ifc->ifc_nand.nand_fcr0,
378 (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
379 (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
381 ifc_out32(&ifc->ifc_nand.nand_fir0,
382 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
383 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
384 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
385 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT));
388 ifc_out32(&ifc->ifc_nand.nand_fcr0,
389 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT);
391 ifc_out32(&ifc->ifc_nand.nand_fcr0,
392 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
396 /* cmdfunc send commands to the IFC NAND Machine */
397 static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
398 int column, int page_addr)
400 struct nand_chip *chip = mtd->priv;
401 struct fsl_ifc_mtd *priv = chip->priv;
402 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
403 struct fsl_ifc *ifc = ctrl->regs;
405 /* clear the read buffer */
406 ctrl->read_bytes = 0;
407 if (command != NAND_CMD_PAGEPROG)
411 /* READ0 read the entire buffer to use hardware ECC. */
412 case NAND_CMD_READ0: {
413 ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
414 set_addr(mtd, 0, page_addr, 0);
416 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
417 ctrl->index += column;
419 if (chip->ecc.mode == NAND_ECC_HW)
422 fsl_ifc_do_read(chip, 0, mtd);
423 fsl_ifc_run_command(mtd);
427 /* READOOB reads only the OOB because no ECC is performed. */
428 case NAND_CMD_READOOB:
429 ifc_out32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column);
430 set_addr(mtd, column, page_addr, 1);
432 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
434 fsl_ifc_do_read(chip, 1, mtd);
435 fsl_ifc_run_command(mtd);
439 /* READID must read all possible bytes while CEB is active */
440 case NAND_CMD_READID:
441 case NAND_CMD_PARAM: {
442 int timing = IFC_FIR_OP_RB;
443 if (command == NAND_CMD_PARAM)
444 timing = IFC_FIR_OP_RBCD;
446 ifc_out32(&ifc->ifc_nand.nand_fir0,
447 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
448 (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
449 (timing << IFC_NAND_FIR0_OP2_SHIFT));
450 ifc_out32(&ifc->ifc_nand.nand_fcr0,
451 command << IFC_NAND_FCR0_CMD0_SHIFT);
452 ifc_out32(&ifc->ifc_nand.row3, column);
455 * although currently it's 8 bytes for READID, we always read
456 * the maximum 256 bytes(for PARAM)
458 ifc_out32(&ifc->ifc_nand.nand_fbcr, 256);
459 ctrl->read_bytes = 256;
461 set_addr(mtd, 0, 0, 0);
462 fsl_ifc_run_command(mtd);
466 /* ERASE1 stores the block and page address */
467 case NAND_CMD_ERASE1:
468 set_addr(mtd, 0, page_addr, 0);
471 /* ERASE2 uses the block and page address from ERASE1 */
472 case NAND_CMD_ERASE2:
473 ifc_out32(&ifc->ifc_nand.nand_fir0,
474 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
475 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
476 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT));
478 ifc_out32(&ifc->ifc_nand.nand_fcr0,
479 (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
480 (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT));
482 ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
483 ctrl->read_bytes = 0;
484 fsl_ifc_run_command(mtd);
487 /* SEQIN sets up the addr buffer and all registers except the length */
488 case NAND_CMD_SEQIN: {
490 ctrl->column = column;
493 if (mtd->writesize > 512) {
495 (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
496 (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) |
497 (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);
499 ifc_out32(&ifc->ifc_nand.nand_fir0,
500 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
501 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
502 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
504 IFC_NAND_FIR0_OP3_SHIFT) |
505 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT));
506 ifc_out32(&ifc->ifc_nand.nand_fir1,
507 (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
508 (IFC_FIR_OP_RDSTAT <<
509 IFC_NAND_FIR1_OP6_SHIFT) |
510 (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT));
512 nand_fcr0 = ((NAND_CMD_PAGEPROG <<
513 IFC_NAND_FCR0_CMD1_SHIFT) |
515 IFC_NAND_FCR0_CMD2_SHIFT) |
517 IFC_NAND_FCR0_CMD3_SHIFT));
519 ifc_out32(&ifc->ifc_nand.nand_fir0,
520 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
521 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
522 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
523 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
524 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT));
525 ifc_out32(&ifc->ifc_nand.nand_fir1,
526 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
527 (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
528 (IFC_FIR_OP_RDSTAT <<
529 IFC_NAND_FIR1_OP7_SHIFT) |
530 (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT));
532 if (column >= mtd->writesize)
534 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT;
537 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
540 if (column >= mtd->writesize) {
541 /* OOB area --> READOOB */
542 column -= mtd->writesize;
545 ifc_out32(&ifc->ifc_nand.nand_fcr0, nand_fcr0);
546 set_addr(mtd, column, page_addr, ctrl->oob);
550 /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
551 case NAND_CMD_PAGEPROG:
553 ifc_out32(&ifc->ifc_nand.nand_fbcr,
554 ctrl->index - ctrl->column);
556 ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
558 fsl_ifc_run_command(mtd);
561 case NAND_CMD_STATUS:
562 ifc_out32(&ifc->ifc_nand.nand_fir0,
563 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
564 (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT));
565 ifc_out32(&ifc->ifc_nand.nand_fcr0,
566 NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT);
567 ifc_out32(&ifc->ifc_nand.nand_fbcr, 1);
568 set_addr(mtd, 0, 0, 0);
569 ctrl->read_bytes = 1;
571 fsl_ifc_run_command(mtd);
573 /* Chip sometimes reporting write protect even when it's not */
574 out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
578 ifc_out32(&ifc->ifc_nand.nand_fir0,
579 IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT);
580 ifc_out32(&ifc->ifc_nand.nand_fcr0,
581 NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT);
582 fsl_ifc_run_command(mtd);
586 printf("%s: error, unsupported command 0x%x.\n",
592 * Write buf to the IFC NAND Controller Data Buffer
594 static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
596 struct nand_chip *chip = mtd->priv;
597 struct fsl_ifc_mtd *priv = chip->priv;
598 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
599 unsigned int bufsize = mtd->writesize + mtd->oobsize;
602 printf("%s of %d bytes", __func__, len);
607 if ((unsigned int)len > bufsize - ctrl->index) {
608 printf("%s beyond end of buffer "
609 "(%d requested, %u available)\n",
610 __func__, len, bufsize - ctrl->index);
611 len = bufsize - ctrl->index;
614 memcpy_toio(&ctrl->addr[ctrl->index], buf, len);
619 * read a byte from either the IFC hardware buffer if it has any data left
620 * otherwise issue a command to read a single byte.
622 static u8 fsl_ifc_read_byte(struct mtd_info *mtd)
624 struct nand_chip *chip = mtd->priv;
625 struct fsl_ifc_mtd *priv = chip->priv;
626 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
628 /* If there are still bytes in the IFC buffer, then use the
630 if (ctrl->index < ctrl->read_bytes)
631 return in_8(&ctrl->addr[ctrl->index++]);
633 printf("%s beyond end of buffer\n", __func__);
638 * Read two bytes from the IFC hardware buffer
639 * read function for 16-bit buswith
641 static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
643 struct nand_chip *chip = mtd->priv;
644 struct fsl_ifc_mtd *priv = chip->priv;
645 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
649 * If there are still bytes in the IFC buffer, then use the
652 if (ctrl->index < ctrl->read_bytes) {
653 data = ifc_in16((uint16_t *)&ctrl->
656 return (uint8_t)data;
659 printf("%s beyond end of buffer\n", __func__);
664 * Read from the IFC Controller Data Buffer
666 static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
668 struct nand_chip *chip = mtd->priv;
669 struct fsl_ifc_mtd *priv = chip->priv;
670 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
676 avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
677 memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail);
678 ctrl->index += avail;
681 printf("%s beyond end of buffer "
682 "(%d requested, %d available)\n",
683 __func__, len, avail);
686 #if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
688 * Verify buffer against the IFC Controller Data Buffer
690 static int fsl_ifc_verify_buf(struct mtd_info *mtd,
691 const u_char *buf, int len)
693 struct nand_chip *chip = mtd->priv;
694 struct fsl_ifc_mtd *priv = chip->priv;
695 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
699 printf("%s of %d bytes", __func__, len);
703 if ((unsigned int)len > ctrl->read_bytes - ctrl->index) {
704 printf("%s beyond end of buffer "
705 "(%d requested, %u available)\n",
706 __func__, len, ctrl->read_bytes - ctrl->index);
708 ctrl->index = ctrl->read_bytes;
712 for (i = 0; i < len; i++)
713 if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i])
717 return i == len && ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO;
721 /* This function is called after Program and Erase Operations to
722 * check for success or failure.
724 static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
726 struct fsl_ifc_mtd *priv = chip->priv;
727 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
728 struct fsl_ifc *ifc = ctrl->regs;
731 if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
732 return NAND_STATUS_FAIL;
734 /* Use READ_STATUS command, but wait for the device to be ready */
735 ifc_out32(&ifc->ifc_nand.nand_fir0,
736 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
737 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT));
738 ifc_out32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS <<
739 IFC_NAND_FCR0_CMD0_SHIFT);
740 ifc_out32(&ifc->ifc_nand.nand_fbcr, 1);
741 set_addr(mtd, 0, 0, 0);
742 ctrl->read_bytes = 1;
744 fsl_ifc_run_command(mtd);
746 if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
747 return NAND_STATUS_FAIL;
749 nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
751 /* Chip sometimes reporting write protect even when it's not */
752 nand_fsr = nand_fsr | NAND_STATUS_WP;
756 static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
757 uint8_t *buf, int oob_required, int page)
759 struct fsl_ifc_mtd *priv = chip->priv;
760 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
762 fsl_ifc_read_buf(mtd, buf, mtd->writesize);
763 fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
765 if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
766 mtd->ecc_stats.failed++;
771 /* ECC will be calculated automatically, and errors will be detected in
774 static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
775 const uint8_t *buf, int oob_required)
777 fsl_ifc_write_buf(mtd, buf, mtd->writesize);
778 fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
783 static void fsl_ifc_ctrl_init(void)
785 ifc_ctrl = kzalloc(sizeof(*ifc_ctrl), GFP_KERNEL);
789 ifc_ctrl->regs = IFC_BASE_ADDR;
791 /* clear event registers */
792 ifc_out32(&ifc_ctrl->regs->ifc_nand.nand_evter_stat, ~0U);
793 ifc_out32(&ifc_ctrl->regs->ifc_nand.pgrdcmpl_evt_stat, ~0U);
795 /* Enable error and event for any detected errors */
796 ifc_out32(&ifc_ctrl->regs->ifc_nand.nand_evter_en,
797 IFC_NAND_EVTER_EN_OPC_EN |
798 IFC_NAND_EVTER_EN_PGRDCMPL_EN |
799 IFC_NAND_EVTER_EN_FTOER_EN |
800 IFC_NAND_EVTER_EN_WPER_EN);
802 ifc_out32(&ifc_ctrl->regs->ifc_nand.ncfgr, 0x0);
805 static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
809 static int fsl_ifc_sram_init(uint32_t ver)
811 struct fsl_ifc *ifc = ifc_ctrl->regs;
812 uint32_t cs = 0, csor = 0, csor_8k = 0, csor_ext = 0;
814 u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
817 if (ver > FSL_IFC_V1_1_0) {
818 ncfgr = ifc_in32(&ifc->ifc_nand.ncfgr);
819 ifc_out32(&ifc->ifc_nand.ncfgr, ncfgr | IFC_NAND_SRAM_INIT_EN);
821 /* wait for SRAM_INIT bit to be clear or timeout */
822 time_start = get_timer(0);
823 while (get_timer(time_start) < timeo) {
825 ifc_in32(&ifc->ifc_nand.nand_evter_stat);
827 if (!(ifc_ctrl->status & IFC_NAND_SRAM_INIT_EN))
830 printf("fsl-ifc: Failed to Initialise SRAM\n");
834 cs = ifc_ctrl->cs_nand >> IFC_NAND_CSEL_SHIFT;
836 /* Save CSOR and CSOR_ext */
837 csor = ifc_in32(&ifc_ctrl->regs->csor_cs[cs].csor);
838 csor_ext = ifc_in32(&ifc_ctrl->regs->csor_cs[cs].csor_ext);
840 /* chage PageSize 8K and SpareSize 1K*/
841 csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
842 ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor, csor_8k);
843 ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, 0x0000400);
846 ifc_out32(&ifc->ifc_nand.nand_fir0,
847 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
848 (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
849 (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT));
850 ifc_out32(&ifc->ifc_nand.nand_fcr0,
851 NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT);
852 ifc_out32(&ifc->ifc_nand.row3, 0x0);
854 ifc_out32(&ifc->ifc_nand.nand_fbcr, 0x0);
856 /* Program ROW0/COL0 */
857 ifc_out32(&ifc->ifc_nand.row0, 0x0);
858 ifc_out32(&ifc->ifc_nand.col0, 0x0);
860 /* set the chip select for NAND Transaction */
861 ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
864 ifc_out32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
866 time_start = get_timer(0);
868 while (get_timer(time_start) < timeo) {
869 ifc_ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
871 if (ifc_ctrl->status & IFC_NAND_EVTER_STAT_OPC)
875 if (ifc_ctrl->status != IFC_NAND_EVTER_STAT_OPC) {
876 printf("fsl-ifc: Failed to Initialise SRAM\n");
880 ifc_out32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status);
882 /* Restore CSOR and CSOR_ext */
883 ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor, csor);
884 ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext);
889 static int fsl_ifc_chip_init(int devnum, u8 *addr)
891 struct mtd_info *mtd = &nand_info[devnum];
892 struct nand_chip *nand;
893 struct fsl_ifc_mtd *priv;
894 struct nand_ecclayout *layout;
895 uint32_t cspr = 0, csor = 0, ver = 0;
904 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
908 priv->ctrl = ifc_ctrl;
911 /* Find which chip select it is connected to.
913 for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
914 phys_addr_t phys_addr = virt_to_phys(addr);
916 cspr = ifc_in32(&ifc_ctrl->regs->cspr_cs[priv->bank].cspr);
917 csor = ifc_in32(&ifc_ctrl->regs->csor_cs[priv->bank].csor);
919 if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND &&
920 (cspr & CSPR_BA) == CSPR_PHYS_ADDR(phys_addr)) {
921 ifc_ctrl->cs_nand = priv->bank << IFC_NAND_CSEL_SHIFT;
926 if (priv->bank >= MAX_BANKS) {
927 printf("%s: address did not match any "
928 "chip selects\n", __func__);
936 ifc_ctrl->chips[priv->bank] = priv;
938 /* fill in nand_chip structure */
939 /* set up function call table */
941 nand->write_buf = fsl_ifc_write_buf;
942 nand->read_buf = fsl_ifc_read_buf;
943 #if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
944 nand->verify_buf = fsl_ifc_verify_buf;
946 nand->select_chip = fsl_ifc_select_chip;
947 nand->cmdfunc = fsl_ifc_cmdfunc;
948 nand->waitfunc = fsl_ifc_wait;
950 /* set up nand options */
951 nand->bbt_td = &bbt_main_descr;
952 nand->bbt_md = &bbt_mirror_descr;
954 /* set up nand options */
955 nand->options = NAND_NO_SUBPAGE_WRITE;
956 nand->bbt_options = NAND_BBT_USE_FLASH;
958 if (cspr & CSPR_PORT_SIZE_16) {
959 nand->read_byte = fsl_ifc_read_byte16;
960 nand->options |= NAND_BUSWIDTH_16;
962 nand->read_byte = fsl_ifc_read_byte;
965 nand->controller = &ifc_ctrl->controller;
968 nand->ecc.read_page = fsl_ifc_read_page;
969 nand->ecc.write_page = fsl_ifc_write_page;
971 /* Hardware generates ECC per 512 Bytes */
972 nand->ecc.size = 512;
975 switch (csor & CSOR_NAND_PGS_MASK) {
976 case CSOR_NAND_PGS_512:
977 if (nand->options & NAND_BUSWIDTH_16) {
978 layout = &oob_512_16bit_ecc4;
980 layout = &oob_512_8bit_ecc4;
982 /* Avoid conflict with bad block marker */
983 bbt_main_descr.offs = 0;
984 bbt_mirror_descr.offs = 0;
987 nand->ecc.strength = 4;
988 priv->bufnum_mask = 15;
991 case CSOR_NAND_PGS_2K:
992 layout = &oob_2048_ecc4;
993 nand->ecc.strength = 4;
994 priv->bufnum_mask = 3;
997 case CSOR_NAND_PGS_4K:
998 if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
999 CSOR_NAND_ECC_MODE_4) {
1000 layout = &oob_4096_ecc4;
1001 nand->ecc.strength = 4;
1003 layout = &oob_4096_ecc8;
1004 nand->ecc.strength = 8;
1005 nand->ecc.bytes = 16;
1008 priv->bufnum_mask = 1;
1011 case CSOR_NAND_PGS_8K:
1012 if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
1013 CSOR_NAND_ECC_MODE_4) {
1014 layout = &oob_8192_ecc4;
1015 nand->ecc.strength = 4;
1017 layout = &oob_8192_ecc8;
1018 nand->ecc.strength = 8;
1019 nand->ecc.bytes = 16;
1022 priv->bufnum_mask = 0;
1027 printf("ifc nand: bad csor %#x: bad page size\n", csor);
1031 /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
1032 if (csor & CSOR_NAND_ECC_DEC_EN) {
1033 nand->ecc.mode = NAND_ECC_HW;
1034 nand->ecc.layout = layout;
1036 nand->ecc.mode = NAND_ECC_SOFT;
1039 ver = ifc_in32(&ifc_ctrl->regs->ifc_rev);
1040 if (ver >= FSL_IFC_V1_1_0)
1041 ret = fsl_ifc_sram_init(ver);
1045 if (ver >= FSL_IFC_V2_0_0)
1046 priv->bufnum_mask = (priv->bufnum_mask * 2) + 1;
1048 ret = nand_scan_ident(mtd, 1, NULL);
1052 ret = nand_scan_tail(mtd);
1056 ret = nand_register(devnum);
1062 #ifndef CONFIG_SYS_NAND_BASE_LIST
1063 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
1066 static unsigned long base_address[CONFIG_SYS_MAX_NAND_DEVICE] =
1067 CONFIG_SYS_NAND_BASE_LIST;
1069 void board_nand_init(void)
1073 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
1074 fsl_ifc_chip_init(i, (u8 *)base_address[i]);