drivers/mtd/nand/fsl_elbc_nand.c

   1 /* Freescale Enhanced Local Bus Controller NAND driver
   2  *
   3  * Copyright © 2006-2007, 2010 Freescale Semiconductor
   4  *
   5  * Authors: Nick Spence <nick.spence@freescale.com>,
   6  *          Scott Wood <scottwood@freescale.com>
   7  *          Jack Lan <jack.lan@freescale.com>
   8  *          Roy Zang <tie-fei.zang@freescale.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  23  */
  24
  25 #include <linux/module.h>
  26 #include <linux/types.h>
  27 #include <linux/init.h>
  28 #include <linux/kernel.h>
  29 #include <linux/string.h>
  30 #include <linux/ioport.h>
  31 #include <linux/of_platform.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/slab.h>
  34 #include <linux/interrupt.h>
  35
  36 #include <linux/mtd/mtd.h>
  37 #include <linux/mtd/nand.h>
  38 #include <linux/mtd/nand_ecc.h>
  39 #include <linux/mtd/partitions.h>
  40
  41 #include <asm/io.h>
  42 #include <asm/fsl_lbc.h>
  43
  44 #define MAX_BANKS 8
  45 #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
  46 #define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */
  47
  48 /* mtd information per set */
  49
  50 struct fsl_elbc_mtd {
  51         struct mtd_info mtd;
  52         struct nand_chip chip;
  53         struct fsl_lbc_ctrl *ctrl;
  54
  55         struct device *dev;
  56         int bank;               /* Chip select bank number           */
  57         u8 __iomem *vbase;      /* Chip select base virtual address  */
  58         int page_size;          /* NAND page size (0=512, 1=2048)    */
  59         unsigned int fmr;       /* FCM Flash Mode Register value     */
  60 };
  61
  62 /* Freescale eLBC FCM controller information */
  63
  64 struct fsl_elbc_fcm_ctrl {
  65         struct nand_hw_control controller;
  66         struct fsl_elbc_mtd *chips[MAX_BANKS];
  67
  68         u8 __iomem *addr;        /* Address of assigned FCM buffer        */
  69         unsigned int page;       /* Last page written to / read from      */
  70         unsigned int read_bytes; /* Number of bytes read during command   */
  71         unsigned int column;     /* Saved column from SEQIN               */
  72         unsigned int index;      /* Pointer to next byte to 'read'        */
  73         unsigned int status;     /* status read from LTESR after last op  */
  74         unsigned int mdr;        /* UPM/FCM Data Register value           */
  75         unsigned int use_mdr;    /* Non zero if the MDR is to be set      */
  76         unsigned int oob;        /* Non zero if operating on OOB data     */
  77         unsigned int counter;    /* counter for the initializations       */
  78         unsigned int max_bitflips;  /* Saved during READ0 cmd             */
  79 };
  80
  81 /* These map to the positions used by the FCM hardware ECC generator */
  82
  83 /* Small Page FLASH with FMR[ECCM] = 0 */
  84 static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = {
  85         .eccbytes = 3,
  86         .eccpos = {6, 7, 8},
  87         .oobfree = { {0, 5}, {9, 7} },
  88 };
  89
  90 /* Small Page FLASH with FMR[ECCM] = 1 */
  91 static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = {
  92         .eccbytes = 3,
  93         .eccpos = {8, 9, 10},
  94         .oobfree = { {0, 5}, {6, 2}, {11, 5} },
  95 };
  96
  97 /* Large Page FLASH with FMR[ECCM] = 0 */
  98 static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = {
  99         .eccbytes = 12,
 100         .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56},
 101         .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} },
 102 };
 103
 104 /* Large Page FLASH with FMR[ECCM] = 1 */
 105 static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = {
 106         .eccbytes = 12,
 107         .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
 108         .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} },
 109 };
 110
 111 /*
 112  * fsl_elbc_oob_lp_eccm* specify that LP NAND's OOB free area starts at offset
 113  * 1, so we have to adjust bad block pattern. This pattern should be used for
 114  * x8 chips only. So far hardware does not support x16 chips anyway.
 115  */
 116 static u8 scan_ff_pattern[] = { 0xff, };
 117
 118 static struct nand_bbt_descr largepage_memorybased = {
 119         .options = 0,
 120         .offs = 0,
 121         .len = 1,
 122         .pattern = scan_ff_pattern,
 123 };
 124
 125 /*
 126  * ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt,
 127  * interfere with ECC positions, that's why we implement our own descriptors.
 128  * OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0.
 129  */
 130 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
 131 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
 132
 133 static struct nand_bbt_descr bbt_main_descr = {
 134         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 135                    NAND_BBT_2BIT | NAND_BBT_VERSION,
 136         .offs = 11,
 137         .len = 4,
 138         .veroffs = 15,
 139         .maxblocks = 4,
 140         .pattern = bbt_pattern,
 141 };
 142
 143 static struct nand_bbt_descr bbt_mirror_descr = {
 144         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 145                    NAND_BBT_2BIT | NAND_BBT_VERSION,
 146         .offs = 11,
 147         .len = 4,
 148         .veroffs = 15,
 149         .maxblocks = 4,
 150         .pattern = mirror_pattern,
 151 };
 152
 153 /*=================================*/
 154
 155 /*
 156  * Set up the FCM hardware block and page address fields, and the fcm
 157  * structure addr field to point to the correct FCM buffer in memory
 158  */
 159 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 160 {
 161         struct nand_chip *chip = mtd->priv;
 162         struct fsl_elbc_mtd *priv = chip->priv;
 163         struct fsl_lbc_ctrl *ctrl = priv->ctrl;
 164         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 165         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
 166         int buf_num;
 167
 168         elbc_fcm_ctrl->page = page_addr;
 169
 170         if (priv->page_size) {
 171                 /*
 172                  * large page size chip : FPAR[PI] save the lowest 6 bits,
 173                  *                        FBAR[BLK] save the other bits.
 174                  */
 175                 out_be32(&lbc->fbar, page_addr >> 6);
 176                 out_be32(&lbc->fpar,
 177                          ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
 178                          (oob ? FPAR_LP_MS : 0) | column);
 179                 buf_num = (page_addr & 1) << 2;
 180         } else {
 181                 /*
 182                  * small page size chip : FPAR[PI] save the lowest 5 bits,
 183                  *                        FBAR[BLK] save the other bits.
 184                  */
 185                 out_be32(&lbc->fbar, page_addr >> 5);
 186                 out_be32(&lbc->fpar,
 187                          ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
 188                          (oob ? FPAR_SP_MS : 0) | column);
 189                 buf_num = page_addr & 7;
 190         }
 191
 192         elbc_fcm_ctrl->addr = priv->vbase + buf_num * 1024;
 193         elbc_fcm_ctrl->index = column;
 194
 195         /* for OOB data point to the second half of the buffer */
 196         if (oob)
 197                 elbc_fcm_ctrl->index += priv->page_size ? 2048 : 512;
 198
 199         dev_vdbg(priv->dev, "set_addr: bank=%d, "
 200                             "elbc_fcm_ctrl->addr=0x%p (0x%p), "
 201                             "index %x, pes %d ps %d\n",
 202                  buf_num, elbc_fcm_ctrl->addr, priv->vbase,
 203                  elbc_fcm_ctrl->index,
 204                  chip->phys_erase_shift, chip->page_shift);
 205 }
 206
 207 /*
 208  * execute FCM command and wait for it to complete
 209  */
 210 static int fsl_elbc_run_command(struct mtd_info *mtd)
 211 {
 212         struct nand_chip *chip = mtd->priv;
 213         struct fsl_elbc_mtd *priv = chip->priv;
 214         struct fsl_lbc_ctrl *ctrl = priv->ctrl;
 215         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
 216         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 217
 218         /* Setup the FMR[OP] to execute without write protection */
 219         out_be32(&lbc->fmr, priv->fmr | 3);
 220         if (elbc_fcm_ctrl->use_mdr)
 221                 out_be32(&lbc->mdr, elbc_fcm_ctrl->mdr);
 222
 223         dev_vdbg(priv->dev,
 224                  "fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n",
 225                  in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr));
 226         dev_vdbg(priv->dev,
 227                  "fsl_elbc_run_command: fbar=%08x fpar=%08x "
 228                  "fbcr=%08x bank=%d\n",
 229                  in_be32(&lbc->fbar), in_be32(&lbc->fpar),
 230                  in_be32(&lbc->fbcr), priv->bank);
 231
 232         ctrl->irq_status = 0;
 233         /* execute special operation */
 234         out_be32(&lbc->lsor, priv->bank);
 235
 236         /* wait for FCM complete flag or timeout */
 237         wait_event_timeout(ctrl->irq_wait, ctrl->irq_status,
 238                            FCM_TIMEOUT_MSECS * HZ/1000);
 239         elbc_fcm_ctrl->status = ctrl->irq_status;
 240         /* store mdr value in case it was needed */
 241         if (elbc_fcm_ctrl->use_mdr)
 242                 elbc_fcm_ctrl->mdr = in_be32(&lbc->mdr);
 243
 244         elbc_fcm_ctrl->use_mdr = 0;
 245
 246         if (elbc_fcm_ctrl->status != LTESR_CC) {
 247                 dev_info(priv->dev,
 248                          "command failed: fir %x fcr %x status %x mdr %x\n",
 249                          in_be32(&lbc->fir), in_be32(&lbc->fcr),
 250                          elbc_fcm_ctrl->status, elbc_fcm_ctrl->mdr);
 251                 return -EIO;
 252         }
 253
 254         if (chip->ecc.mode != NAND_ECC_HW)
 255                 return 0;
 256
 257         elbc_fcm_ctrl->max_bitflips = 0;
 258
 259         if (elbc_fcm_ctrl->read_bytes == mtd->writesize + mtd->oobsize) {
 260                 uint32_t lteccr = in_be32(&lbc->lteccr);
 261                 /*
 262                  * if command was a full page read and the ELBC
 263                  * has the LTECCR register, then bits 12-15 (ppc order) of
 264                  * LTECCR indicates which 512 byte sub-pages had fixed errors.
 265                  * bits 28-31 are uncorrectable errors, marked elsewhere.
 266                  * for small page nand only 1 bit is used.
 267                  * if the ELBC doesn't have the lteccr register it reads 0
 268                  * FIXME: 4 bits can be corrected on NANDs with 2k pages, so
 269                  * count the number of sub-pages with bitflips and update
 270                  * ecc_stats.corrected accordingly.
 271                  */
 272                 if (lteccr & 0x000F000F)
 273                         out_be32(&lbc->lteccr, 0x000F000F); /* clear lteccr */
 274                 if (lteccr & 0x000F0000) {
 275                         mtd->ecc_stats.corrected++;
 276                         elbc_fcm_ctrl->max_bitflips = 1;
 277                 }
 278         }
 279
 280         return 0;
 281 }
 282
 283 static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
 284 {
 285         struct fsl_elbc_mtd *priv = chip->priv;
 286         struct fsl_lbc_ctrl *ctrl = priv->ctrl;
 287         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 288
 289         if (priv->page_size) {
 290                 out_be32(&lbc->fir,
 291                          (FIR_OP_CM0 << FIR_OP0_SHIFT) |
 292                          (FIR_OP_CA  << FIR_OP1_SHIFT) |
 293                          (FIR_OP_PA  << FIR_OP2_SHIFT) |
 294                          (FIR_OP_CM1 << FIR_OP3_SHIFT) |
 295                          (FIR_OP_RBW << FIR_OP4_SHIFT));
 296
 297                 out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
 298                                     (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
 299         } else {
 300                 out_be32(&lbc->fir,
 301                          (FIR_OP_CM0 << FIR_OP0_SHIFT) |
 302                          (FIR_OP_CA  << FIR_OP1_SHIFT) |
 303                          (FIR_OP_PA  << FIR_OP2_SHIFT) |
 304                          (FIR_OP_RBW << FIR_OP3_SHIFT));
 305
 306                 if (oob)
 307                         out_be32(&lbc->fcr, NAND_CMD_READOOB << FCR_CMD0_SHIFT);
 308                 else
 309                         out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
 310         }
 311 }
 312
 313 /* cmdfunc send commands to the FCM */
 314 static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 315                              int column, int page_addr)
 316 {
 317         struct nand_chip *chip = mtd->priv;
 318         struct fsl_elbc_mtd *priv = chip->priv;
 319         struct fsl_lbc_ctrl *ctrl = priv->ctrl;
 320         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
 321         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 322
 323         elbc_fcm_ctrl->use_mdr = 0;
 324
 325         /* clear the read buffer */
 326         elbc_fcm_ctrl->read_bytes = 0;
 327         if (command != NAND_CMD_PAGEPROG)
 328                 elbc_fcm_ctrl->index = 0;
 329
 330         switch (command) {
 331         /* READ0 and READ1 read the entire buffer to use hardware ECC. */
 332         case NAND_CMD_READ1:
 333                 column += 256;
 334
 335         /* fall-through */
 336         case NAND_CMD_READ0:
 337                 dev_dbg(priv->dev,
 338                         "fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
 339                         " 0x%x, column: 0x%x.\n", page_addr, column);
 340
 341
 342                 out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */
 343                 set_addr(mtd, 0, page_addr, 0);
 344
 345                 elbc_fcm_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 346                 elbc_fcm_ctrl->index += column;
 347
 348                 fsl_elbc_do_read(chip, 0);
 349                 fsl_elbc_run_command(mtd);
 350                 return;
 351
 352         /* READOOB reads only the OOB because no ECC is performed. */
 353         case NAND_CMD_READOOB:
 354                 dev_vdbg(priv->dev,
 355                          "fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
 356                          " 0x%x, column: 0x%x.\n", page_addr, column);
 357
 358                 out_be32(&lbc->fbcr, mtd->oobsize - column);
 359                 set_addr(mtd, column, page_addr, 1);
 360
 361                 elbc_fcm_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 362
 363                 fsl_elbc_do_read(chip, 1);
 364                 fsl_elbc_run_command(mtd);
 365                 return;
 366
 367         case NAND_CMD_READID:
 368         case NAND_CMD_PARAM:
 369                 dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD %x\n", command);
 370
 371                 out_be32(&lbc->fir, (FIR_OP_CM0 << FIR_OP0_SHIFT) |
 372                                     (FIR_OP_UA  << FIR_OP1_SHIFT) |
 373                                     (FIR_OP_RBW << FIR_OP2_SHIFT));
 374                 out_be32(&lbc->fcr, command << FCR_CMD0_SHIFT);
 375                 /*
 376                  * although currently it's 8 bytes for READID, we always read
 377                  * the maximum 256 bytes(for PARAM)
 378                  */
 379                 out_be32(&lbc->fbcr, 256);
 380                 elbc_fcm_ctrl->read_bytes = 256;
 381                 elbc_fcm_ctrl->use_mdr = 1;
 382                 elbc_fcm_ctrl->mdr = column;
 383                 set_addr(mtd, 0, 0, 0);
 384                 fsl_elbc_run_command(mtd);
 385                 return;
 386
 387         /* ERASE1 stores the block and page address */
 388         case NAND_CMD_ERASE1:
 389                 dev_vdbg(priv->dev,
 390                          "fsl_elbc_cmdfunc: NAND_CMD_ERASE1, "
 391                          "page_addr: 0x%x.\n", page_addr);
 392                 set_addr(mtd, 0, page_addr, 0);
 393                 return;
 394
 395         /* ERASE2 uses the block and page address from ERASE1 */
 396         case NAND_CMD_ERASE2:
 397                 dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
 398
 399                 out_be32(&lbc->fir,
 400                          (FIR_OP_CM0 << FIR_OP0_SHIFT) |
 401                          (FIR_OP_PA  << FIR_OP1_SHIFT) |
 402                          (FIR_OP_CM2 << FIR_OP2_SHIFT) |
 403                          (FIR_OP_CW1 << FIR_OP3_SHIFT) |
 404                          (FIR_OP_RS  << FIR_OP4_SHIFT));
 405
 406                 out_be32(&lbc->fcr,
 407                          (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) |
 408                          (NAND_CMD_STATUS << FCR_CMD1_SHIFT) |
 409                          (NAND_CMD_ERASE2 << FCR_CMD2_SHIFT));
 410
 411                 out_be32(&lbc->fbcr, 0);
 412                 elbc_fcm_ctrl->read_bytes = 0;
 413                 elbc_fcm_ctrl->use_mdr = 1;
 414
 415                 fsl_elbc_run_command(mtd);
 416                 return;
 417
 418         /* SEQIN sets up the addr buffer and all registers except the length */
 419         case NAND_CMD_SEQIN: {
 420                 __be32 fcr;
 421                 dev_vdbg(priv->dev,
 422                          "fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, "
 423                          "page_addr: 0x%x, column: 0x%x.\n",
 424                          page_addr, column);
 425
 426                 elbc_fcm_ctrl->column = column;
 427                 elbc_fcm_ctrl->use_mdr = 1;
 428
 429                 if (column >= mtd->writesize) {
 430                         /* OOB area */
 431                         column -= mtd->writesize;
 432                         elbc_fcm_ctrl->oob = 1;
 433                 } else {
 434                         WARN_ON(column != 0);
 435                         elbc_fcm_ctrl->oob = 0;
 436                 }
 437
 438                 fcr = (NAND_CMD_STATUS   << FCR_CMD1_SHIFT) |
 439                       (NAND_CMD_SEQIN    << FCR_CMD2_SHIFT) |
 440                       (NAND_CMD_PAGEPROG << FCR_CMD3_SHIFT);
 441
 442                 if (priv->page_size) {
 443                         out_be32(&lbc->fir,
 444                                  (FIR_OP_CM2 << FIR_OP0_SHIFT) |
 445                                  (FIR_OP_CA  << FIR_OP1_SHIFT) |
 446                                  (FIR_OP_PA  << FIR_OP2_SHIFT) |
 447                                  (FIR_OP_WB  << FIR_OP3_SHIFT) |
 448                                  (FIR_OP_CM3 << FIR_OP4_SHIFT) |
 449                                  (FIR_OP_CW1 << FIR_OP5_SHIFT) |
 450                                  (FIR_OP_RS  << FIR_OP6_SHIFT));
 451                 } else {
 452                         out_be32(&lbc->fir,
 453                                  (FIR_OP_CM0 << FIR_OP0_SHIFT) |
 454                                  (FIR_OP_CM2 << FIR_OP1_SHIFT) |
 455                                  (FIR_OP_CA  << FIR_OP2_SHIFT) |
 456                                  (FIR_OP_PA  << FIR_OP3_SHIFT) |
 457                                  (FIR_OP_WB  << FIR_OP4_SHIFT) |
 458                                  (FIR_OP_CM3 << FIR_OP5_SHIFT) |
 459                                  (FIR_OP_CW1 << FIR_OP6_SHIFT) |
 460                                  (FIR_OP_RS  << FIR_OP7_SHIFT));
 461
 462                         if (elbc_fcm_ctrl->oob)
 463                                 /* OOB area --> READOOB */
 464                                 fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT;
 465                         else
 466                                 /* First 256 bytes --> READ0 */
 467                                 fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
 468                 }
 469
 470                 out_be32(&lbc->fcr, fcr);
 471                 set_addr(mtd, column, page_addr, elbc_fcm_ctrl->oob);
 472                 return;
 473         }
 474
 475         /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
 476         case NAND_CMD_PAGEPROG: {
 477                 dev_vdbg(priv->dev,
 478                          "fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG "
 479                          "writing %d bytes.\n", elbc_fcm_ctrl->index);
 480
 481                 /* if the write did not start at 0 or is not a full page
 482                  * then set the exact length, otherwise use a full page
 483                  * write so the HW generates the ECC.
 484                  */
 485                 if (elbc_fcm_ctrl->oob || elbc_fcm_ctrl->column != 0 ||
 486                     elbc_fcm_ctrl->index != mtd->writesize + mtd->oobsize)
 487                         out_be32(&lbc->fbcr,
 488                                 elbc_fcm_ctrl->index - elbc_fcm_ctrl->column);
 489                 else
 490                         out_be32(&lbc->fbcr, 0);
 491
 492                 fsl_elbc_run_command(mtd);
 493                 return;
 494         }
 495
 496         /* CMD_STATUS must read the status byte while CEB is active */
 497         /* Note - it does not wait for the ready line */
 498         case NAND_CMD_STATUS:
 499                 out_be32(&lbc->fir,
 500                          (FIR_OP_CM0 << FIR_OP0_SHIFT) |
 501                          (FIR_OP_RBW << FIR_OP1_SHIFT));
 502                 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
 503                 out_be32(&lbc->fbcr, 1);
 504                 set_addr(mtd, 0, 0, 0);
 505                 elbc_fcm_ctrl->read_bytes = 1;
 506
 507                 fsl_elbc_run_command(mtd);
 508
 509                 /* The chip always seems to report that it is
 510                  * write-protected, even when it is not.
 511                  */
 512                 setbits8(elbc_fcm_ctrl->addr, NAND_STATUS_WP);
 513                 return;
 514
 515         /* RESET without waiting for the ready line */
 516         case NAND_CMD_RESET:
 517                 dev_dbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
 518                 out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);
 519                 out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);
 520                 fsl_elbc_run_command(mtd);
 521                 return;
 522
 523         default:
 524                 dev_err(priv->dev,
 525                         "fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n",
 526                         command);
 527         }
 528 }
 529
 530 static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip)
 531 {
 532         /* The hardware does not seem to support multiple
 533          * chips per bank.
 534          */
 535 }
 536
 537 /*
 538  * Write buf to the FCM Controller Data Buffer
 539  */
 540 static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 541 {
 542         struct nand_chip *chip = mtd->priv;
 543         struct fsl_elbc_mtd *priv = chip->priv;
 544         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
 545         unsigned int bufsize = mtd->writesize + mtd->oobsize;
 546
 547         if (len <= 0) {
 548                 dev_err(priv->dev, "write_buf of %d bytes", len);
 549                 elbc_fcm_ctrl->status = 0;
 550                 return;
 551         }
 552
 553         if ((unsigned int)len > bufsize - elbc_fcm_ctrl->index) {
 554                 dev_err(priv->dev,
 555                         "write_buf beyond end of buffer "
 556                         "(%d requested, %u available)\n",
 557                         len, bufsize - elbc_fcm_ctrl->index);
 558                 len = bufsize - elbc_fcm_ctrl->index;
 559         }
 560
 561         memcpy_toio(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], buf, len);
 562         /*
 563          * This is workaround for the weird elbc hangs during nand write,
 564          * Scott Wood says: "...perhaps difference in how long it takes a
 565          * write to make it through the localbus compared to a write to IMMR
 566          * is causing problems, and sync isn't helping for some reason."
 567          * Reading back the last byte helps though.
 568          */
 569         in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index] + len - 1);
 570
 571         elbc_fcm_ctrl->index += len;
 572 }
 573
 574 /*
 575  * read a byte from either the FCM hardware buffer if it has any data left
 576  * otherwise issue a command to read a single byte.
 577  */
 578 static u8 fsl_elbc_read_byte(struct mtd_info *mtd)
 579 {
 580         struct nand_chip *chip = mtd->priv;
 581         struct fsl_elbc_mtd *priv = chip->priv;
 582         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
 583
 584         /* If there are still bytes in the FCM, then use the next byte. */
 585         if (elbc_fcm_ctrl->index < elbc_fcm_ctrl->read_bytes)
 586                 return in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index++]);
 587
 588         dev_err(priv->dev, "read_byte beyond end of buffer\n");
 589         return ERR_BYTE;
 590 }
 591
 592 /*
 593  * Read from the FCM Controller Data Buffer
 594  */
 595 static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 596 {
 597         struct nand_chip *chip = mtd->priv;
 598         struct fsl_elbc_mtd *priv = chip->priv;
 599         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
 600         int avail;
 601
 602         if (len < 0)
 603                 return;
 604
 605         avail = min((unsigned int)len,
 606                         elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index);
 607         memcpy_fromio(buf, &elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], avail);
 608         elbc_fcm_ctrl->index += avail;
 609
 610         if (len > avail)
 611                 dev_err(priv->dev,
 612                         "read_buf beyond end of buffer "
 613                         "(%d requested, %d available)\n",
 614                         len, avail);
 615 }
 616
 617 /*
 618  * Verify buffer against the FCM Controller Data Buffer
 619  */
 620 static int fsl_elbc_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
 621 {
 622         struct nand_chip *chip = mtd->priv;
 623         struct fsl_elbc_mtd *priv = chip->priv;
 624         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
 625         int i;
 626
 627         if (len < 0) {
 628                 dev_err(priv->dev, "write_buf of %d bytes", len);
 629                 return -EINVAL;
 630         }
 631
 632         if ((unsigned int)len >
 633                         elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index) {
 634                 dev_err(priv->dev,
 635                         "verify_buf beyond end of buffer "
 636                         "(%d requested, %u available)\n",
 637                         len, elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index);
 638
 639                 elbc_fcm_ctrl->index = elbc_fcm_ctrl->read_bytes;
 640                 return -EINVAL;
 641         }
 642
 643         for (i = 0; i < len; i++)
 644                 if (in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index + i])
 645                                 != buf[i])
 646                         break;
 647
 648         elbc_fcm_ctrl->index += len;
 649         return i == len && elbc_fcm_ctrl->status == LTESR_CC ? 0 : -EIO;
 650 }
 651
 652 /* This function is called after Program and Erase Operations to
 653  * check for success or failure.
 654  */
 655 static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 656 {
 657         struct fsl_elbc_mtd *priv = chip->priv;
 658         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
 659
 660         if (elbc_fcm_ctrl->status != LTESR_CC)
 661                 return NAND_STATUS_FAIL;
 662
 663         /* The chip always seems to report that it is
 664          * write-protected, even when it is not.
 665          */
 666         return (elbc_fcm_ctrl->mdr & 0xff) | NAND_STATUS_WP;
 667 }
 668
 669 static int fsl_elbc_chip_init_tail(struct mtd_info *mtd)
 670 {
 671         struct nand_chip *chip = mtd->priv;
 672         struct fsl_elbc_mtd *priv = chip->priv;
 673         struct fsl_lbc_ctrl *ctrl = priv->ctrl;
 674         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 675         unsigned int al;
 676
 677         /* calculate FMR Address Length field */
 678         al = 0;
 679         if (chip->pagemask & 0xffff0000)
 680                 al++;
 681         if (chip->pagemask & 0xff000000)
 682                 al++;
 683
 684         priv->fmr |= al << FMR_AL_SHIFT;
 685
 686         dev_dbg(priv->dev, "fsl_elbc_init: nand->numchips = %d\n",
 687                 chip->numchips);
 688         dev_dbg(priv->dev, "fsl_elbc_init: nand->chipsize = %lld\n",
 689                 chip->chipsize);
 690         dev_dbg(priv->dev, "fsl_elbc_init: nand->pagemask = %8x\n",
 691                 chip->pagemask);
 692         dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_delay = %d\n",
 693                 chip->chip_delay);
 694         dev_dbg(priv->dev, "fsl_elbc_init: nand->badblockpos = %d\n",
 695                 chip->badblockpos);
 696         dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_shift = %d\n",
 697                 chip->chip_shift);
 698         dev_dbg(priv->dev, "fsl_elbc_init: nand->page_shift = %d\n",
 699                 chip->page_shift);
 700         dev_dbg(priv->dev, "fsl_elbc_init: nand->phys_erase_shift = %d\n",
 701                 chip->phys_erase_shift);
 702         dev_dbg(priv->dev, "fsl_elbc_init: nand->ecclayout = %p\n",
 703                 chip->ecclayout);
 704         dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.mode = %d\n",
 705                 chip->ecc.mode);
 706         dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.steps = %d\n",
 707                 chip->ecc.steps);
 708         dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.bytes = %d\n",
 709                 chip->ecc.bytes);
 710         dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.total = %d\n",
 711                 chip->ecc.total);
 712         dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.layout = %p\n",
 713                 chip->ecc.layout);
 714         dev_dbg(priv->dev, "fsl_elbc_init: mtd->flags = %08x\n", mtd->flags);
 715         dev_dbg(priv->dev, "fsl_elbc_init: mtd->size = %lld\n", mtd->size);
 716         dev_dbg(priv->dev, "fsl_elbc_init: mtd->erasesize = %d\n",
 717                 mtd->erasesize);
 718         dev_dbg(priv->dev, "fsl_elbc_init: mtd->writesize = %d\n",
 719                 mtd->writesize);
 720         dev_dbg(priv->dev, "fsl_elbc_init: mtd->oobsize = %d\n",
 721                 mtd->oobsize);
 722
 723         /* adjust Option Register and ECC to match Flash page size */
 724         if (mtd->writesize == 512) {
 725                 priv->page_size = 0;
 726                 clrbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
 727         } else if (mtd->writesize == 2048) {
 728                 priv->page_size = 1;
 729                 setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
 730                 /* adjust ecc setup if needed */
 731                 if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
 732                     BR_DECC_CHK_GEN) {
 733                         chip->ecc.size = 512;
 734                         chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
 735                                            &fsl_elbc_oob_lp_eccm1 :
 736                                            &fsl_elbc_oob_lp_eccm0;
 737                         chip->badblock_pattern = &largepage_memorybased;
 738                 }
 739         } else {
 740                 dev_err(priv->dev,
 741                         "fsl_elbc_init: page size %d is not supported\n",
 742                         mtd->writesize);
 743                 return -1;
 744         }
 745
 746         return 0;
 747 }
 748
 749 static int fsl_elbc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
 750                               uint8_t *buf, int oob_required, int page)
 751 {
 752         struct fsl_elbc_mtd *priv = chip->priv;
 753         struct fsl_lbc_ctrl *ctrl = priv->ctrl;
 754         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
 755
 756         fsl_elbc_read_buf(mtd, buf, mtd->writesize);
 757         if (oob_required)
 758                 fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
 759
 760         if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL)
 761                 mtd->ecc_stats.failed++;
 762
 763         return elbc_fcm_ctrl->max_bitflips;
 764 }
 765
 766 /* ECC will be calculated automatically, and errors will be detected in
 767  * waitfunc.
 768  */
 769 static int fsl_elbc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 770                                 const uint8_t *buf, int oob_required)
 771 {
 772         fsl_elbc_write_buf(mtd, buf, mtd->writesize);
 773         fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 774
 775         return 0;
 776 }
 777
 778 static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv)
 779 {
 780         struct fsl_lbc_ctrl *ctrl = priv->ctrl;
 781         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 782         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
 783         struct nand_chip *chip = &priv->chip;
 784
 785         dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank);
 786
 787         /* Fill in fsl_elbc_mtd structure */
 788         priv->mtd.priv = chip;
 789         priv->mtd.owner = THIS_MODULE;
 790
 791         /* set timeout to maximum */
 792         priv->fmr = 15 << FMR_CWTO_SHIFT;
 793         if (in_be32(&lbc->bank[priv->bank].or) & OR_FCM_PGS)
 794                 priv->fmr |= FMR_ECCM;
 795
 796         /* fill in nand_chip structure */
 797         /* set up function call table */
 798         chip->read_byte = fsl_elbc_read_byte;
 799         chip->write_buf = fsl_elbc_write_buf;
 800         chip->read_buf = fsl_elbc_read_buf;
 801         chip->verify_buf = fsl_elbc_verify_buf;
 802         chip->select_chip = fsl_elbc_select_chip;
 803         chip->cmdfunc = fsl_elbc_cmdfunc;
 804         chip->waitfunc = fsl_elbc_wait;
 805
 806         chip->bbt_td = &bbt_main_descr;
 807         chip->bbt_md = &bbt_mirror_descr;
 808
 809         /* set up nand options */
 810         chip->bbt_options = NAND_BBT_USE_FLASH;
 811
 812         chip->controller = &elbc_fcm_ctrl->controller;
 813         chip->priv = priv;
 814
 815         chip->ecc.read_page = fsl_elbc_read_page;
 816         chip->ecc.write_page = fsl_elbc_write_page;
 817
 818         /* If CS Base Register selects full hardware ECC then use it */
 819         if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
 820             BR_DECC_CHK_GEN) {
 821                 chip->ecc.mode = NAND_ECC_HW;
 822                 /* put in small page settings and adjust later if needed */
 823                 chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
 824                                 &fsl_elbc_oob_sp_eccm1 : &fsl_elbc_oob_sp_eccm0;
 825                 chip->ecc.size = 512;
 826                 chip->ecc.bytes = 3;
 827                 chip->ecc.strength = 1;
 828         } else {
 829                 /* otherwise fall back to default software ECC */
 830                 chip->ecc.mode = NAND_ECC_SOFT;
 831         }
 832
 833         return 0;
 834 }
 835
 836 static int fsl_elbc_chip_remove(struct fsl_elbc_mtd *priv)
 837 {
 838         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
 839         nand_release(&priv->mtd);
 840
 841         kfree(priv->mtd.name);
 842
 843         if (priv->vbase)
 844                 iounmap(priv->vbase);
 845
 846         elbc_fcm_ctrl->chips[priv->bank] = NULL;
 847         kfree(priv);
 848         return 0;
 849 }
 850
 851 static DEFINE_MUTEX(fsl_elbc_nand_mutex);
 852
 853 static int __devinit fsl_elbc_nand_probe(struct platform_device *pdev)
 854 {
 855         struct fsl_lbc_regs __iomem *lbc;
 856         struct fsl_elbc_mtd *priv;
 857         struct resource res;
 858         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl;
 859         static const char *part_probe_types[]
 860                 = { "cmdlinepart", "RedBoot", "ofpart", NULL };
 861         int ret;
 862         int bank;
 863         struct device *dev;
 864         struct device_node *node = pdev->dev.of_node;
 865         struct mtd_part_parser_data ppdata;
 866
 867         ppdata.of_node = pdev->dev.of_node;
 868         if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
 869                 return -ENODEV;
 870         lbc = fsl_lbc_ctrl_dev->regs;
 871         dev = fsl_lbc_ctrl_dev->dev;
 872
 873         /* get, allocate and map the memory resource */
 874         ret = of_address_to_resource(node, 0, &res);
 875         if (ret) {
 876                 dev_err(dev, "failed to get resource\n");
 877                 return ret;
 878         }
 879
 880         /* find which chip select it is connected to */
 881         for (bank = 0; bank < MAX_BANKS; bank++)
 882                 if ((in_be32(&lbc->bank[bank].br) & BR_V) &&
 883                     (in_be32(&lbc->bank[bank].br) & BR_MSEL) == BR_MS_FCM &&
 884                     (in_be32(&lbc->bank[bank].br) &
 885                      in_be32(&lbc->bank[bank].or) & BR_BA)
 886                      == fsl_lbc_addr(res.start))
 887                         break;
 888
 889         if (bank >= MAX_BANKS) {
 890                 dev_err(dev, "address did not match any chip selects\n");
 891                 return -ENODEV;
 892         }
 893
 894         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 895         if (!priv)
 896                 return -ENOMEM;
 897
 898         mutex_lock(&fsl_elbc_nand_mutex);
 899         if (!fsl_lbc_ctrl_dev->nand) {
 900                 elbc_fcm_ctrl = kzalloc(sizeof(*elbc_fcm_ctrl), GFP_KERNEL);
 901                 if (!elbc_fcm_ctrl) {
 902                         dev_err(dev, "failed to allocate memory\n");
 903                         mutex_unlock(&fsl_elbc_nand_mutex);
 904                         ret = -ENOMEM;
 905                         goto err;
 906                 }
 907                 elbc_fcm_ctrl->counter++;
 908
 909                 spin_lock_init(&elbc_fcm_ctrl->controller.lock);
 910                 init_waitqueue_head(&elbc_fcm_ctrl->controller.wq);
 911                 fsl_lbc_ctrl_dev->nand = elbc_fcm_ctrl;
 912         } else {
 913                 elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand;
 914         }
 915         mutex_unlock(&fsl_elbc_nand_mutex);
 916
 917         elbc_fcm_ctrl->chips[bank] = priv;
 918         priv->bank = bank;
 919         priv->ctrl = fsl_lbc_ctrl_dev;
 920         priv->dev = &pdev->dev;
 921         dev_set_drvdata(priv->dev, priv);
 922
 923         priv->vbase = ioremap(res.start, resource_size(&res));
 924         if (!priv->vbase) {
 925                 dev_err(dev, "failed to map chip region\n");
 926                 ret = -ENOMEM;
 927                 goto err;
 928         }
 929
 930         priv->mtd.name = kasprintf(GFP_KERNEL, "%x.flash", (unsigned)res.start);
 931         if (!priv->mtd.name) {
 932                 ret = -ENOMEM;
 933                 goto err;
 934         }
 935
 936         ret = fsl_elbc_chip_init(priv);
 937         if (ret)
 938                 goto err;
 939
 940         ret = nand_scan_ident(&priv->mtd, 1, NULL);
 941         if (ret)
 942                 goto err;
 943
 944         ret = fsl_elbc_chip_init_tail(&priv->mtd);
 945         if (ret)
 946                 goto err;
 947
 948         ret = nand_scan_tail(&priv->mtd);
 949         if (ret)
 950                 goto err;
 951
 952         /* First look for RedBoot table or partitions on the command
 953          * line, these take precedence over device tree information */
 954         mtd_device_parse_register(&priv->mtd, part_probe_types, &ppdata,
 955                                   NULL, 0);
 956
 957         printk(KERN_INFO "eLBC NAND device at 0x%llx, bank %d\n",
 958                (unsigned long long)res.start, priv->bank);
 959         return 0;
 960
 961 err:
 962         fsl_elbc_chip_remove(priv);
 963         return ret;
 964 }
 965
 966 static int fsl_elbc_nand_remove(struct platform_device *pdev)
 967 {
 968         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand;
 969         struct fsl_elbc_mtd *priv = dev_get_drvdata(&pdev->dev);
 970
 971         fsl_elbc_chip_remove(priv);
 972
 973         mutex_lock(&fsl_elbc_nand_mutex);
 974         elbc_fcm_ctrl->counter--;
 975         if (!elbc_fcm_ctrl->counter) {
 976                 fsl_lbc_ctrl_dev->nand = NULL;
 977                 kfree(elbc_fcm_ctrl);
 978         }
 979         mutex_unlock(&fsl_elbc_nand_mutex);
 980
 981         return 0;
 982
 983 }
 984
 985 static const struct of_device_id fsl_elbc_nand_match[] = {
 986         { .compatible = "fsl,elbc-fcm-nand", },
 987         {}
 988 };
 989
 990 static struct platform_driver fsl_elbc_nand_driver = {
 991         .driver = {
 992                 .name = "fsl,elbc-fcm-nand",
 993                 .owner = THIS_MODULE,
 994                 .of_match_table = fsl_elbc_nand_match,
 995         },
 996         .probe = fsl_elbc_nand_probe,
 997         .remove = fsl_elbc_nand_remove,
 998 };
 999
1000 module_platform_driver(fsl_elbc_nand_driver);
1001
1002 MODULE_LICENSE("GPL");
1003 MODULE_AUTHOR("Freescale");
1004 MODULE_DESCRIPTION("Freescale Enhanced Local Bus Controller MTD NAND driver");