drivers/mtd/nand/fsl_elbc_nand.c

   1 /* Freescale Enhanced Local Bus Controller NAND driver
   2  *
   3  * Copyright © 2006-2007, 2010 Freescale Semiconductor
   4  *
   5  * Authors: Nick Spence <nick.spence@freescale.com>,
   6  *          Scott Wood <scottwood@freescale.com>
   7  *          Jack Lan <jack.lan@freescale.com>
   8  *          Roy Zang <tie-fei.zang@freescale.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  23  */
  24
  25 #include <linux/module.h>
  26 #include <linux/types.h>
  27 #include <linux/init.h>
  28 #include <linux/kernel.h>
  29 #include <linux/string.h>
  30 #include <linux/ioport.h>
  31 #include <linux/of_platform.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/slab.h>
  34 #include <linux/interrupt.h>
  35
  36 #include <linux/mtd/mtd.h>
  37 #include <linux/mtd/nand.h>
  38 #include <linux/mtd/nand_ecc.h>
  39 #include <linux/mtd/partitions.h>
  40
  41 #include <asm/io.h>
  42 #include <asm/fsl_lbc.h>
  43
  44 #define MAX_BANKS 8
  45 #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
  46 #define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */
  47
  48 /* mtd information per set */
  49
  50 struct fsl_elbc_mtd {
  51         struct mtd_info mtd;
  52         struct nand_chip chip;
  53         struct fsl_lbc_ctrl *ctrl;
  54
  55         struct device *dev;
  56         int bank;               /* Chip select bank number           */
  57         u8 __iomem *vbase;      /* Chip select base virtual address  */
  58         int page_size;          /* NAND page size (0=512, 1=2048)    */
  59         unsigned int fmr;       /* FCM Flash Mode Register value     */
  60 };
  61
  62 /* Freescale eLBC FCM controller information */
  63
  64 struct fsl_elbc_fcm_ctrl {
  65         struct nand_hw_control controller;
  66         struct fsl_elbc_mtd *chips[MAX_BANKS];
  67
  68         u8 __iomem *addr;        /* Address of assigned FCM buffer        */
  69         unsigned int page;       /* Last page written to / read from      */
  70         unsigned int read_bytes; /* Number of bytes read during command   */
  71         unsigned int column;     /* Saved column from SEQIN               */
  72         unsigned int index;      /* Pointer to next byte to 'read'        */
  73         unsigned int status;     /* status read from LTESR after last op  */
  74         unsigned int mdr;        /* UPM/FCM Data Register value           */
  75         unsigned int use_mdr;    /* Non zero if the MDR is to be set      */
  76         unsigned int oob;        /* Non zero if operating on OOB data     */
  77         unsigned int counter;    /* counter for the initializations       */
  78         char *oob_poi;           /* Place to write ECC after read back    */
  79 };
  80
  81 /* These map to the positions used by the FCM hardware ECC generator */
  82
  83 /* Small Page FLASH with FMR[ECCM] = 0 */
  84 static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = {
  85         .eccbytes = 3,
  86         .eccpos = {6, 7, 8},
  87         .oobfree = { {0, 5}, {9, 7} },
  88 };
  89
  90 /* Small Page FLASH with FMR[ECCM] = 1 */
  91 static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = {
  92         .eccbytes = 3,
  93         .eccpos = {8, 9, 10},
  94         .oobfree = { {0, 5}, {6, 2}, {11, 5} },
  95 };
  96
  97 /* Large Page FLASH with FMR[ECCM] = 0 */
  98 static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = {
  99         .eccbytes = 12,
 100         .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56},
 101         .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} },
 102 };
 103
 104 /* Large Page FLASH with FMR[ECCM] = 1 */
 105 static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = {
 106         .eccbytes = 12,
 107         .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
 108         .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} },
 109 };
 110
 111 /*
 112  * fsl_elbc_oob_lp_eccm* specify that LP NAND's OOB free area starts at offset
 113  * 1, so we have to adjust bad block pattern. This pattern should be used for
 114  * x8 chips only. So far hardware does not support x16 chips anyway.
 115  */
 116 static u8 scan_ff_pattern[] = { 0xff, };
 117
 118 static struct nand_bbt_descr largepage_memorybased = {
 119         .options = 0,
 120         .offs = 0,
 121         .len = 1,
 122         .pattern = scan_ff_pattern,
 123 };
 124
 125 /*
 126  * ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt,
 127  * interfere with ECC positions, that's why we implement our own descriptors.
 128  * OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0.
 129  */
 130 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
 131 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
 132
 133 static struct nand_bbt_descr bbt_main_descr = {
 134         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 135                    NAND_BBT_2BIT | NAND_BBT_VERSION,
 136         .offs = 11,
 137         .len = 4,
 138         .veroffs = 15,
 139         .maxblocks = 4,
 140         .pattern = bbt_pattern,
 141 };
 142
 143 static struct nand_bbt_descr bbt_mirror_descr = {
 144         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 145                    NAND_BBT_2BIT | NAND_BBT_VERSION,
 146         .offs = 11,
 147         .len = 4,
 148         .veroffs = 15,
 149         .maxblocks = 4,
 150         .pattern = mirror_pattern,
 151 };
 152
 153 /*=================================*/
 154
 155 /*
 156  * Set up the FCM hardware block and page address fields, and the fcm
 157  * structure addr field to point to the correct FCM buffer in memory
 158  */
 159 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 160 {
 161         struct nand_chip *chip = mtd->priv;
 162         struct fsl_elbc_mtd *priv = chip->priv;
 163         struct fsl_lbc_ctrl *ctrl = priv->ctrl;
 164         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 165         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
 166         int buf_num;
 167
 168         elbc_fcm_ctrl->page = page_addr;
 169
 170         out_be32(&lbc->fbar,
 171                  page_addr >> (chip->phys_erase_shift - chip->page_shift));
 172
 173         if (priv->page_size) {
 174                 out_be32(&lbc->fpar,
 175                          ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
 176                          (oob ? FPAR_LP_MS : 0) | column);
 177                 buf_num = (page_addr & 1) << 2;
 178         } else {
 179                 out_be32(&lbc->fpar,
 180                          ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
 181                          (oob ? FPAR_SP_MS : 0) | column);
 182                 buf_num = page_addr & 7;
 183         }
 184
 185         elbc_fcm_ctrl->addr = priv->vbase + buf_num * 1024;
 186         elbc_fcm_ctrl->index = column;
 187
 188         /* for OOB data point to the second half of the buffer */
 189         if (oob)
 190                 elbc_fcm_ctrl->index += priv->page_size ? 2048 : 512;
 191
 192         dev_vdbg(priv->dev, "set_addr: bank=%d, "
 193                             "elbc_fcm_ctrl->addr=0x%p (0x%p), "
 194                             "index %x, pes %d ps %d\n",
 195                  buf_num, elbc_fcm_ctrl->addr, priv->vbase,
 196                  elbc_fcm_ctrl->index,
 197                  chip->phys_erase_shift, chip->page_shift);
 198 }
 199
 200 /*
 201  * execute FCM command and wait for it to complete
 202  */
 203 static int fsl_elbc_run_command(struct mtd_info *mtd)
 204 {
 205         struct nand_chip *chip = mtd->priv;
 206         struct fsl_elbc_mtd *priv = chip->priv;
 207         struct fsl_lbc_ctrl *ctrl = priv->ctrl;
 208         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
 209         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 210
 211         /* Setup the FMR[OP] to execute without write protection */
 212         out_be32(&lbc->fmr, priv->fmr | 3);
 213         if (elbc_fcm_ctrl->use_mdr)
 214                 out_be32(&lbc->mdr, elbc_fcm_ctrl->mdr);
 215
 216         dev_vdbg(priv->dev,
 217                  "fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n",
 218                  in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr));
 219         dev_vdbg(priv->dev,
 220                  "fsl_elbc_run_command: fbar=%08x fpar=%08x "
 221                  "fbcr=%08x bank=%d\n",
 222                  in_be32(&lbc->fbar), in_be32(&lbc->fpar),
 223                  in_be32(&lbc->fbcr), priv->bank);
 224
 225         ctrl->irq_status = 0;
 226         /* execute special operation */
 227         out_be32(&lbc->lsor, priv->bank);
 228
 229         /* wait for FCM complete flag or timeout */
 230         wait_event_timeout(ctrl->irq_wait, ctrl->irq_status,
 231                            FCM_TIMEOUT_MSECS * HZ/1000);
 232         elbc_fcm_ctrl->status = ctrl->irq_status;
 233         /* store mdr value in case it was needed */
 234         if (elbc_fcm_ctrl->use_mdr)
 235                 elbc_fcm_ctrl->mdr = in_be32(&lbc->mdr);
 236
 237         elbc_fcm_ctrl->use_mdr = 0;
 238
 239         if (elbc_fcm_ctrl->status != LTESR_CC) {
 240                 dev_info(priv->dev,
 241                          "command failed: fir %x fcr %x status %x mdr %x\n",
 242                          in_be32(&lbc->fir), in_be32(&lbc->fcr),
 243                          elbc_fcm_ctrl->status, elbc_fcm_ctrl->mdr);
 244                 return -EIO;
 245         }
 246
 247         return 0;
 248 }
 249
 250 static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
 251 {
 252         struct fsl_elbc_mtd *priv = chip->priv;
 253         struct fsl_lbc_ctrl *ctrl = priv->ctrl;
 254         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 255
 256         if (priv->page_size) {
 257                 out_be32(&lbc->fir,
 258                          (FIR_OP_CM0 << FIR_OP0_SHIFT) |
 259                          (FIR_OP_CA  << FIR_OP1_SHIFT) |
 260                          (FIR_OP_PA  << FIR_OP2_SHIFT) |
 261                          (FIR_OP_CM1 << FIR_OP3_SHIFT) |
 262                          (FIR_OP_RBW << FIR_OP4_SHIFT));
 263
 264                 out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
 265                                     (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
 266         } else {
 267                 out_be32(&lbc->fir,
 268                          (FIR_OP_CM0 << FIR_OP0_SHIFT) |
 269                          (FIR_OP_CA  << FIR_OP1_SHIFT) |
 270                          (FIR_OP_PA  << FIR_OP2_SHIFT) |
 271                          (FIR_OP_RBW << FIR_OP3_SHIFT));
 272
 273                 if (oob)
 274                         out_be32(&lbc->fcr, NAND_CMD_READOOB << FCR_CMD0_SHIFT);
 275                 else
 276                         out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
 277         }
 278 }
 279
 280 /* cmdfunc send commands to the FCM */
 281 static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 282                              int column, int page_addr)
 283 {
 284         struct nand_chip *chip = mtd->priv;
 285         struct fsl_elbc_mtd *priv = chip->priv;
 286         struct fsl_lbc_ctrl *ctrl = priv->ctrl;
 287         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
 288         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 289
 290         elbc_fcm_ctrl->use_mdr = 0;
 291
 292         /* clear the read buffer */
 293         elbc_fcm_ctrl->read_bytes = 0;
 294         if (command != NAND_CMD_PAGEPROG)
 295                 elbc_fcm_ctrl->index = 0;
 296
 297         switch (command) {
 298         /* READ0 and READ1 read the entire buffer to use hardware ECC. */
 299         case NAND_CMD_READ1:
 300                 column += 256;
 301
 302         /* fall-through */
 303         case NAND_CMD_READ0:
 304                 dev_dbg(priv->dev,
 305                         "fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
 306                         " 0x%x, column: 0x%x.\n", page_addr, column);
 307
 308
 309                 out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */
 310                 set_addr(mtd, 0, page_addr, 0);
 311
 312                 elbc_fcm_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 313                 elbc_fcm_ctrl->index += column;
 314
 315                 fsl_elbc_do_read(chip, 0);
 316                 fsl_elbc_run_command(mtd);
 317                 return;
 318
 319         /* READOOB reads only the OOB because no ECC is performed. */
 320         case NAND_CMD_READOOB:
 321                 dev_vdbg(priv->dev,
 322                          "fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
 323                          " 0x%x, column: 0x%x.\n", page_addr, column);
 324
 325                 out_be32(&lbc->fbcr, mtd->oobsize - column);
 326                 set_addr(mtd, column, page_addr, 1);
 327
 328                 elbc_fcm_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 329
 330                 fsl_elbc_do_read(chip, 1);
 331                 fsl_elbc_run_command(mtd);
 332                 return;
 333
 334         /* READID must read all 5 possible bytes while CEB is active */
 335         case NAND_CMD_READID:
 336                 dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_READID.\n");
 337
 338                 out_be32(&lbc->fir, (FIR_OP_CM0 << FIR_OP0_SHIFT) |
 339                                     (FIR_OP_UA  << FIR_OP1_SHIFT) |
 340                                     (FIR_OP_RBW << FIR_OP2_SHIFT));
 341                 out_be32(&lbc->fcr, NAND_CMD_READID << FCR_CMD0_SHIFT);
 342                 /* 5 bytes for manuf, device and exts */
 343                 out_be32(&lbc->fbcr, 5);
 344                 elbc_fcm_ctrl->read_bytes = 5;
 345                 elbc_fcm_ctrl->use_mdr = 1;
 346                 elbc_fcm_ctrl->mdr = 0;
 347
 348                 set_addr(mtd, 0, 0, 0);
 349                 fsl_elbc_run_command(mtd);
 350                 return;
 351
 352         /* ERASE1 stores the block and page address */
 353         case NAND_CMD_ERASE1:
 354                 dev_vdbg(priv->dev,
 355                          "fsl_elbc_cmdfunc: NAND_CMD_ERASE1, "
 356                          "page_addr: 0x%x.\n", page_addr);
 357                 set_addr(mtd, 0, page_addr, 0);
 358                 return;
 359
 360         /* ERASE2 uses the block and page address from ERASE1 */
 361         case NAND_CMD_ERASE2:
 362                 dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
 363
 364                 out_be32(&lbc->fir,
 365                          (FIR_OP_CM0 << FIR_OP0_SHIFT) |
 366                          (FIR_OP_PA  << FIR_OP1_SHIFT) |
 367                          (FIR_OP_CM2 << FIR_OP2_SHIFT) |
 368                          (FIR_OP_CW1 << FIR_OP3_SHIFT) |
 369                          (FIR_OP_RS  << FIR_OP4_SHIFT));
 370
 371                 out_be32(&lbc->fcr,
 372                          (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) |
 373                          (NAND_CMD_STATUS << FCR_CMD1_SHIFT) |
 374                          (NAND_CMD_ERASE2 << FCR_CMD2_SHIFT));
 375
 376                 out_be32(&lbc->fbcr, 0);
 377                 elbc_fcm_ctrl->read_bytes = 0;
 378                 elbc_fcm_ctrl->use_mdr = 1;
 379
 380                 fsl_elbc_run_command(mtd);
 381                 return;
 382
 383         /* SEQIN sets up the addr buffer and all registers except the length */
 384         case NAND_CMD_SEQIN: {
 385                 __be32 fcr;
 386                 dev_vdbg(priv->dev,
 387                          "fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, "
 388                          "page_addr: 0x%x, column: 0x%x.\n",
 389                          page_addr, column);
 390
 391                 elbc_fcm_ctrl->column = column;
 392                 elbc_fcm_ctrl->oob = 0;
 393                 elbc_fcm_ctrl->use_mdr = 1;
 394
 395                 fcr = (NAND_CMD_STATUS   << FCR_CMD1_SHIFT) |
 396                       (NAND_CMD_SEQIN    << FCR_CMD2_SHIFT) |
 397                       (NAND_CMD_PAGEPROG << FCR_CMD3_SHIFT);
 398
 399                 if (priv->page_size) {
 400                         out_be32(&lbc->fir,
 401                                  (FIR_OP_CM2 << FIR_OP0_SHIFT) |
 402                                  (FIR_OP_CA  << FIR_OP1_SHIFT) |
 403                                  (FIR_OP_PA  << FIR_OP2_SHIFT) |
 404                                  (FIR_OP_WB  << FIR_OP3_SHIFT) |
 405                                  (FIR_OP_CM3 << FIR_OP4_SHIFT) |
 406                                  (FIR_OP_CW1 << FIR_OP5_SHIFT) |
 407                                  (FIR_OP_RS  << FIR_OP6_SHIFT));
 408                 } else {
 409                         out_be32(&lbc->fir,
 410                                  (FIR_OP_CM0 << FIR_OP0_SHIFT) |
 411                                  (FIR_OP_CM2 << FIR_OP1_SHIFT) |
 412                                  (FIR_OP_CA  << FIR_OP2_SHIFT) |
 413                                  (FIR_OP_PA  << FIR_OP3_SHIFT) |
 414                                  (FIR_OP_WB  << FIR_OP4_SHIFT) |
 415                                  (FIR_OP_CM3 << FIR_OP5_SHIFT) |
 416                                  (FIR_OP_CW1 << FIR_OP6_SHIFT) |
 417                                  (FIR_OP_RS  << FIR_OP7_SHIFT));
 418
 419                         if (column >= mtd->writesize) {
 420                                 /* OOB area --> READOOB */
 421                                 column -= mtd->writesize;
 422                                 fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT;
 423                                 elbc_fcm_ctrl->oob = 1;
 424                         } else {
 425                                 WARN_ON(column != 0);
 426                                 /* First 256 bytes --> READ0 */
 427                                 fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
 428                         }
 429                 }
 430
 431                 out_be32(&lbc->fcr, fcr);
 432                 set_addr(mtd, column, page_addr, elbc_fcm_ctrl->oob);
 433                 return;
 434         }
 435
 436         /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
 437         case NAND_CMD_PAGEPROG: {
 438                 int full_page;
 439                 dev_vdbg(priv->dev,
 440                          "fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG "
 441                          "writing %d bytes.\n", elbc_fcm_ctrl->index);
 442
 443                 /* if the write did not start at 0 or is not a full page
 444                  * then set the exact length, otherwise use a full page
 445                  * write so the HW generates the ECC.
 446                  */
 447                 if (elbc_fcm_ctrl->oob || elbc_fcm_ctrl->column != 0 ||
 448                     elbc_fcm_ctrl->index != mtd->writesize + mtd->oobsize) {
 449                         out_be32(&lbc->fbcr, elbc_fcm_ctrl->index);
 450                         full_page = 0;
 451                 } else {
 452                         out_be32(&lbc->fbcr, 0);
 453                         full_page = 1;
 454                 }
 455
 456                 fsl_elbc_run_command(mtd);
 457
 458                 /* Read back the page in order to fill in the ECC for the
 459                  * caller.  Is this really needed?
 460                  */
 461                 if (full_page && elbc_fcm_ctrl->oob_poi) {
 462                         out_be32(&lbc->fbcr, 3);
 463                         set_addr(mtd, 6, page_addr, 1);
 464
 465                         elbc_fcm_ctrl->read_bytes = mtd->writesize + 9;
 466
 467                         fsl_elbc_do_read(chip, 1);
 468                         fsl_elbc_run_command(mtd);
 469
 470                         memcpy_fromio(elbc_fcm_ctrl->oob_poi + 6,
 471                                 &elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], 3);
 472                         elbc_fcm_ctrl->index += 3;
 473                 }
 474
 475                 elbc_fcm_ctrl->oob_poi = NULL;
 476                 return;
 477         }
 478
 479         /* CMD_STATUS must read the status byte while CEB is active */
 480         /* Note - it does not wait for the ready line */
 481         case NAND_CMD_STATUS:
 482                 out_be32(&lbc->fir,
 483                          (FIR_OP_CM0 << FIR_OP0_SHIFT) |
 484                          (FIR_OP_RBW << FIR_OP1_SHIFT));
 485                 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
 486                 out_be32(&lbc->fbcr, 1);
 487                 set_addr(mtd, 0, 0, 0);
 488                 elbc_fcm_ctrl->read_bytes = 1;
 489
 490                 fsl_elbc_run_command(mtd);
 491
 492                 /* The chip always seems to report that it is
 493                  * write-protected, even when it is not.
 494                  */
 495                 setbits8(elbc_fcm_ctrl->addr, NAND_STATUS_WP);
 496                 return;
 497
 498         /* RESET without waiting for the ready line */
 499         case NAND_CMD_RESET:
 500                 dev_dbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
 501                 out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);
 502                 out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);
 503                 fsl_elbc_run_command(mtd);
 504                 return;
 505
 506         default:
 507                 dev_err(priv->dev,
 508                         "fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n",
 509                         command);
 510         }
 511 }
 512
 513 static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip)
 514 {
 515         /* The hardware does not seem to support multiple
 516          * chips per bank.
 517          */
 518 }
 519
 520 /*
 521  * Write buf to the FCM Controller Data Buffer
 522  */
 523 static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 524 {
 525         struct nand_chip *chip = mtd->priv;
 526         struct fsl_elbc_mtd *priv = chip->priv;
 527         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
 528         unsigned int bufsize = mtd->writesize + mtd->oobsize;
 529
 530         if (len <= 0) {
 531                 dev_err(priv->dev, "write_buf of %d bytes", len);
 532                 elbc_fcm_ctrl->status = 0;
 533                 return;
 534         }
 535
 536         if ((unsigned int)len > bufsize - elbc_fcm_ctrl->index) {
 537                 dev_err(priv->dev,
 538                         "write_buf beyond end of buffer "
 539                         "(%d requested, %u available)\n",
 540                         len, bufsize - elbc_fcm_ctrl->index);
 541                 len = bufsize - elbc_fcm_ctrl->index;
 542         }
 543
 544         memcpy_toio(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], buf, len);
 545         /*
 546          * This is workaround for the weird elbc hangs during nand write,
 547          * Scott Wood says: "...perhaps difference in how long it takes a
 548          * write to make it through the localbus compared to a write to IMMR
 549          * is causing problems, and sync isn't helping for some reason."
 550          * Reading back the last byte helps though.
 551          */
 552         in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index] + len - 1);
 553
 554         elbc_fcm_ctrl->index += len;
 555 }
 556
 557 /*
 558  * read a byte from either the FCM hardware buffer if it has any data left
 559  * otherwise issue a command to read a single byte.
 560  */
 561 static u8 fsl_elbc_read_byte(struct mtd_info *mtd)
 562 {
 563         struct nand_chip *chip = mtd->priv;
 564         struct fsl_elbc_mtd *priv = chip->priv;
 565         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
 566
 567         /* If there are still bytes in the FCM, then use the next byte. */
 568         if (elbc_fcm_ctrl->index < elbc_fcm_ctrl->read_bytes)
 569                 return in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index++]);
 570
 571         dev_err(priv->dev, "read_byte beyond end of buffer\n");
 572         return ERR_BYTE;
 573 }
 574
 575 /*
 576  * Read from the FCM Controller Data Buffer
 577  */
 578 static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 579 {
 580         struct nand_chip *chip = mtd->priv;
 581         struct fsl_elbc_mtd *priv = chip->priv;
 582         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
 583         int avail;
 584
 585         if (len < 0)
 586                 return;
 587
 588         avail = min((unsigned int)len,
 589                         elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index);
 590         memcpy_fromio(buf, &elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], avail);
 591         elbc_fcm_ctrl->index += avail;
 592
 593         if (len > avail)
 594                 dev_err(priv->dev,
 595                         "read_buf beyond end of buffer "
 596                         "(%d requested, %d available)\n",
 597                         len, avail);
 598 }
 599
 600 /*
 601  * Verify buffer against the FCM Controller Data Buffer
 602  */
 603 static int fsl_elbc_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
 604 {
 605         struct nand_chip *chip = mtd->priv;
 606         struct fsl_elbc_mtd *priv = chip->priv;
 607         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
 608         int i;
 609
 610         if (len < 0) {
 611                 dev_err(priv->dev, "write_buf of %d bytes", len);
 612                 return -EINVAL;
 613         }
 614
 615         if ((unsigned int)len >
 616                         elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index) {
 617                 dev_err(priv->dev,
 618                         "verify_buf beyond end of buffer "
 619                         "(%d requested, %u available)\n",
 620                         len, elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index);
 621
 622                 elbc_fcm_ctrl->index = elbc_fcm_ctrl->read_bytes;
 623                 return -EINVAL;
 624         }
 625
 626         for (i = 0; i < len; i++)
 627                 if (in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index + i])
 628                                 != buf[i])
 629                         break;
 630
 631         elbc_fcm_ctrl->index += len;
 632         return i == len && elbc_fcm_ctrl->status == LTESR_CC ? 0 : -EIO;
 633 }
 634
 635 /* This function is called after Program and Erase Operations to
 636  * check for success or failure.
 637  */
 638 static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 639 {
 640         struct fsl_elbc_mtd *priv = chip->priv;
 641         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
 642
 643         if (elbc_fcm_ctrl->status != LTESR_CC)
 644                 return NAND_STATUS_FAIL;
 645
 646         /* The chip always seems to report that it is
 647          * write-protected, even when it is not.
 648          */
 649         return (elbc_fcm_ctrl->mdr & 0xff) | NAND_STATUS_WP;
 650 }
 651
 652 static int fsl_elbc_chip_init_tail(struct mtd_info *mtd)
 653 {
 654         struct nand_chip *chip = mtd->priv;
 655         struct fsl_elbc_mtd *priv = chip->priv;
 656         struct fsl_lbc_ctrl *ctrl = priv->ctrl;
 657         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 658         unsigned int al;
 659
 660         /* calculate FMR Address Length field */
 661         al = 0;
 662         if (chip->pagemask & 0xffff0000)
 663                 al++;
 664         if (chip->pagemask & 0xff000000)
 665                 al++;
 666
 667         /* add to ECCM mode set in fsl_elbc_init */
 668         priv->fmr |= (12 << FMR_CWTO_SHIFT) |  /* Timeout > 12 ms */
 669                      (al << FMR_AL_SHIFT);
 670
 671         dev_dbg(priv->dev, "fsl_elbc_init: nand->numchips = %d\n",
 672                 chip->numchips);
 673         dev_dbg(priv->dev, "fsl_elbc_init: nand->chipsize = %lld\n",
 674                 chip->chipsize);
 675         dev_dbg(priv->dev, "fsl_elbc_init: nand->pagemask = %8x\n",
 676                 chip->pagemask);
 677         dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_delay = %d\n",
 678                 chip->chip_delay);
 679         dev_dbg(priv->dev, "fsl_elbc_init: nand->badblockpos = %d\n",
 680                 chip->badblockpos);
 681         dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_shift = %d\n",
 682                 chip->chip_shift);
 683         dev_dbg(priv->dev, "fsl_elbc_init: nand->page_shift = %d\n",
 684                 chip->page_shift);
 685         dev_dbg(priv->dev, "fsl_elbc_init: nand->phys_erase_shift = %d\n",
 686                 chip->phys_erase_shift);
 687         dev_dbg(priv->dev, "fsl_elbc_init: nand->ecclayout = %p\n",
 688                 chip->ecclayout);
 689         dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.mode = %d\n",
 690                 chip->ecc.mode);
 691         dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.steps = %d\n",
 692                 chip->ecc.steps);
 693         dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.bytes = %d\n",
 694                 chip->ecc.bytes);
 695         dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.total = %d\n",
 696                 chip->ecc.total);
 697         dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.layout = %p\n",
 698                 chip->ecc.layout);
 699         dev_dbg(priv->dev, "fsl_elbc_init: mtd->flags = %08x\n", mtd->flags);
 700         dev_dbg(priv->dev, "fsl_elbc_init: mtd->size = %lld\n", mtd->size);
 701         dev_dbg(priv->dev, "fsl_elbc_init: mtd->erasesize = %d\n",
 702                 mtd->erasesize);
 703         dev_dbg(priv->dev, "fsl_elbc_init: mtd->writesize = %d\n",
 704                 mtd->writesize);
 705         dev_dbg(priv->dev, "fsl_elbc_init: mtd->oobsize = %d\n",
 706                 mtd->oobsize);
 707
 708         /* adjust Option Register and ECC to match Flash page size */
 709         if (mtd->writesize == 512) {
 710                 priv->page_size = 0;
 711                 clrbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
 712         } else if (mtd->writesize == 2048) {
 713                 priv->page_size = 1;
 714                 setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
 715                 /* adjust ecc setup if needed */
 716                 if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
 717                     BR_DECC_CHK_GEN) {
 718                         chip->ecc.size = 512;
 719                         chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
 720                                            &fsl_elbc_oob_lp_eccm1 :
 721                                            &fsl_elbc_oob_lp_eccm0;
 722                         chip->badblock_pattern = &largepage_memorybased;
 723                 }
 724         } else {
 725                 dev_err(priv->dev,
 726                         "fsl_elbc_init: page size %d is not supported\n",
 727                         mtd->writesize);
 728                 return -1;
 729         }
 730
 731         return 0;
 732 }
 733
 734 static int fsl_elbc_read_page(struct mtd_info *mtd,
 735                               struct nand_chip *chip,
 736                               uint8_t *buf,
 737                               int page)
 738 {
 739         fsl_elbc_read_buf(mtd, buf, mtd->writesize);
 740         fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
 741
 742         if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL)
 743                 mtd->ecc_stats.failed++;
 744
 745         return 0;
 746 }
 747
 748 /* ECC will be calculated automatically, and errors will be detected in
 749  * waitfunc.
 750  */
 751 static void fsl_elbc_write_page(struct mtd_info *mtd,
 752                                 struct nand_chip *chip,
 753                                 const uint8_t *buf)
 754 {
 755         struct fsl_elbc_mtd *priv = chip->priv;
 756         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
 757
 758         fsl_elbc_write_buf(mtd, buf, mtd->writesize);
 759         fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 760
 761         elbc_fcm_ctrl->oob_poi = chip->oob_poi;
 762 }
 763
 764 static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv)
 765 {
 766         struct fsl_lbc_ctrl *ctrl = priv->ctrl;
 767         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 768         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
 769         struct nand_chip *chip = &priv->chip;
 770
 771         dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank);
 772
 773         /* Fill in fsl_elbc_mtd structure */
 774         priv->mtd.priv = chip;
 775         priv->mtd.owner = THIS_MODULE;
 776
 777         /* Set the ECCM according to the settings in bootloader.*/
 778         priv->fmr = in_be32(&lbc->fmr) & FMR_ECCM;
 779
 780         /* fill in nand_chip structure */
 781         /* set up function call table */
 782         chip->read_byte = fsl_elbc_read_byte;
 783         chip->write_buf = fsl_elbc_write_buf;
 784         chip->read_buf = fsl_elbc_read_buf;
 785         chip->verify_buf = fsl_elbc_verify_buf;
 786         chip->select_chip = fsl_elbc_select_chip;
 787         chip->cmdfunc = fsl_elbc_cmdfunc;
 788         chip->waitfunc = fsl_elbc_wait;
 789
 790         chip->bbt_td = &bbt_main_descr;
 791         chip->bbt_md = &bbt_mirror_descr;
 792
 793         /* set up nand options */
 794         chip->options = NAND_NO_READRDY | NAND_NO_AUTOINCR |
 795                         NAND_USE_FLASH_BBT;
 796
 797         chip->controller = &elbc_fcm_ctrl->controller;
 798         chip->priv = priv;
 799
 800         chip->ecc.read_page = fsl_elbc_read_page;
 801         chip->ecc.write_page = fsl_elbc_write_page;
 802
 803         /* If CS Base Register selects full hardware ECC then use it */
 804         if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
 805             BR_DECC_CHK_GEN) {
 806                 chip->ecc.mode = NAND_ECC_HW;
 807                 /* put in small page settings and adjust later if needed */
 808                 chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
 809                                 &fsl_elbc_oob_sp_eccm1 : &fsl_elbc_oob_sp_eccm0;
 810                 chip->ecc.size = 512;
 811                 chip->ecc.bytes = 3;
 812         } else {
 813                 /* otherwise fall back to default software ECC */
 814                 chip->ecc.mode = NAND_ECC_SOFT;
 815         }
 816
 817         return 0;
 818 }
 819
 820 static int fsl_elbc_chip_remove(struct fsl_elbc_mtd *priv)
 821 {
 822         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
 823         nand_release(&priv->mtd);
 824
 825         kfree(priv->mtd.name);
 826
 827         if (priv->vbase)
 828                 iounmap(priv->vbase);
 829
 830         elbc_fcm_ctrl->chips[priv->bank] = NULL;
 831         kfree(priv);
 832         kfree(elbc_fcm_ctrl);
 833         return 0;
 834 }
 835
 836 static DEFINE_MUTEX(fsl_elbc_nand_mutex);
 837
 838 static int __devinit fsl_elbc_nand_probe(struct platform_device *pdev)
 839 {
 840         struct fsl_lbc_regs __iomem *lbc;
 841         struct fsl_elbc_mtd *priv;
 842         struct resource res;
 843         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl;
 844
 845 #ifdef CONFIG_MTD_PARTITIONS
 846         static const char *part_probe_types[]
 847                 = { "cmdlinepart", "RedBoot", NULL };
 848         struct mtd_partition *parts;
 849 #endif
 850         int ret;
 851         int bank;
 852         struct device *dev;
 853         struct device_node *node = pdev->dev.of_node;
 854
 855         if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
 856                 return -ENODEV;
 857         lbc = fsl_lbc_ctrl_dev->regs;
 858         dev = fsl_lbc_ctrl_dev->dev;
 859
 860         /* get, allocate and map the memory resource */
 861         ret = of_address_to_resource(node, 0, &res);
 862         if (ret) {
 863                 dev_err(dev, "failed to get resource\n");
 864                 return ret;
 865         }
 866
 867         /* find which chip select it is connected to */
 868         for (bank = 0; bank < MAX_BANKS; bank++)
 869                 if ((in_be32(&lbc->bank[bank].br) & BR_V) &&
 870                     (in_be32(&lbc->bank[bank].br) & BR_MSEL) == BR_MS_FCM &&
 871                     (in_be32(&lbc->bank[bank].br) &
 872                      in_be32(&lbc->bank[bank].or) & BR_BA)
 873                      == fsl_lbc_addr(res.start))
 874                         break;
 875
 876         if (bank >= MAX_BANKS) {
 877                 dev_err(dev, "address did not match any chip selects\n");
 878                 return -ENODEV;
 879         }
 880
 881         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 882         if (!priv)
 883                 return -ENOMEM;
 884
 885         mutex_lock(&fsl_elbc_nand_mutex);
 886         if (!fsl_lbc_ctrl_dev->nand) {
 887                 elbc_fcm_ctrl = kzalloc(sizeof(*elbc_fcm_ctrl), GFP_KERNEL);
 888                 if (!elbc_fcm_ctrl) {
 889                         dev_err(dev, "failed to allocate memory\n");
 890                         mutex_unlock(&fsl_elbc_nand_mutex);
 891                         ret = -ENOMEM;
 892                         goto err;
 893                 }
 894                 elbc_fcm_ctrl->counter++;
 895
 896                 spin_lock_init(&elbc_fcm_ctrl->controller.lock);
 897                 init_waitqueue_head(&elbc_fcm_ctrl->controller.wq);
 898                 fsl_lbc_ctrl_dev->nand = elbc_fcm_ctrl;
 899         } else {
 900                 elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand;
 901         }
 902         mutex_unlock(&fsl_elbc_nand_mutex);
 903
 904         elbc_fcm_ctrl->chips[bank] = priv;
 905         priv->bank = bank;
 906         priv->ctrl = fsl_lbc_ctrl_dev;
 907         priv->dev = dev;
 908
 909         priv->vbase = ioremap(res.start, resource_size(&res));
 910         if (!priv->vbase) {
 911                 dev_err(dev, "failed to map chip region\n");
 912                 ret = -ENOMEM;
 913                 goto err;
 914         }
 915
 916         priv->mtd.name = kasprintf(GFP_KERNEL, "%x.flash", (unsigned)res.start);
 917         if (!priv->mtd.name) {
 918                 ret = -ENOMEM;
 919                 goto err;
 920         }
 921
 922         ret = fsl_elbc_chip_init(priv);
 923         if (ret)
 924                 goto err;
 925
 926         ret = nand_scan_ident(&priv->mtd, 1, NULL);
 927         if (ret)
 928                 goto err;
 929
 930         ret = fsl_elbc_chip_init_tail(&priv->mtd);
 931         if (ret)
 932                 goto err;
 933
 934         ret = nand_scan_tail(&priv->mtd);
 935         if (ret)
 936                 goto err;
 937
 938 #ifdef CONFIG_MTD_PARTITIONS
 939         /* First look for RedBoot table or partitions on the command
 940          * line, these take precedence over device tree information */
 941         ret = parse_mtd_partitions(&priv->mtd, part_probe_types, &parts, 0);
 942         if (ret < 0)
 943                 goto err;
 944
 945 #ifdef CONFIG_MTD_OF_PARTS
 946         if (ret == 0) {
 947                 ret = of_mtd_parse_partitions(priv->dev, node, &parts);
 948                 if (ret < 0)
 949                         goto err;
 950         }
 951 #endif
 952
 953         if (ret > 0)
 954                 add_mtd_partitions(&priv->mtd, parts, ret);
 955         else
 956 #endif
 957                 add_mtd_device(&priv->mtd);
 958
 959         printk(KERN_INFO "eLBC NAND device at 0x%llx, bank %d\n",
 960                (unsigned long long)res.start, priv->bank);
 961         return 0;
 962
 963 err:
 964         fsl_elbc_chip_remove(priv);
 965         return ret;
 966 }
 967
 968 static int fsl_elbc_nand_remove(struct platform_device *pdev)
 969 {
 970         int i;
 971         struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand;
 972         for (i = 0; i < MAX_BANKS; i++)
 973                 if (elbc_fcm_ctrl->chips[i])
 974                         fsl_elbc_chip_remove(elbc_fcm_ctrl->chips[i]);
 975
 976         mutex_lock(&fsl_elbc_nand_mutex);
 977         elbc_fcm_ctrl->counter--;
 978         if (!elbc_fcm_ctrl->counter) {
 979                 fsl_lbc_ctrl_dev->nand = NULL;
 980                 kfree(elbc_fcm_ctrl);
 981         }
 982         mutex_unlock(&fsl_elbc_nand_mutex);
 983
 984         return 0;
 985
 986 }
 987
 988 static const struct of_device_id fsl_elbc_nand_match[] = {
 989         { .compatible = "fsl,elbc-fcm-nand", },
 990         {}
 991 };
 992
 993 static struct platform_driver fsl_elbc_nand_driver = {
 994         .driver = {
 995                 .name = "fsl,elbc-fcm-nand",
 996                 .owner = THIS_MODULE,
 997                 .of_match_table = fsl_elbc_nand_match,
 998         },
 999         .probe = fsl_elbc_nand_probe,
1000         .remove = fsl_elbc_nand_remove,
1001 };
1002
1003 static int __init fsl_elbc_nand_init(void)
1004 {
1005         return platform_driver_register(&fsl_elbc_nand_driver);
1006 }
1007
1008 static void __exit fsl_elbc_nand_exit(void)
1009 {
1010         platform_driver_unregister(&fsl_elbc_nand_driver);
1011 }
1012
1013 module_init(fsl_elbc_nand_init);
1014 module_exit(fsl_elbc_nand_exit);
1015
1016 MODULE_LICENSE("GPL");
1017 MODULE_AUTHOR("Freescale");
1018 MODULE_DESCRIPTION("Freescale Enhanced Local Bus Controller MTD NAND driver");