2 * Copyright (C) 2013-2014 Altera Corporation <www.altera.com>
3 * Copyright (C) 2009-2010, Intel Corporation and its suppliers.
5 * SPDX-License-Identifier: GPL-2.0+
8 #include <linux/mtd/nand.h>
10 #define DEVICE_RESET 0x0
11 #define DEVICE_RESET__BANK0 0x0001
12 #define DEVICE_RESET__BANK1 0x0002
13 #define DEVICE_RESET__BANK2 0x0004
14 #define DEVICE_RESET__BANK3 0x0008
16 #define TRANSFER_SPARE_REG 0x10
17 #define TRANSFER_SPARE_REG__FLAG 0x0001
19 #define LOAD_WAIT_CNT 0x20
20 #define LOAD_WAIT_CNT__VALUE 0xffff
22 #define PROGRAM_WAIT_CNT 0x30
23 #define PROGRAM_WAIT_CNT__VALUE 0xffff
25 #define ERASE_WAIT_CNT 0x40
26 #define ERASE_WAIT_CNT__VALUE 0xffff
28 #define INT_MON_CYCCNT 0x50
29 #define INT_MON_CYCCNT__VALUE 0xffff
31 #define RB_PIN_ENABLED 0x60
32 #define RB_PIN_ENABLED__BANK0 0x0001
33 #define RB_PIN_ENABLED__BANK1 0x0002
34 #define RB_PIN_ENABLED__BANK2 0x0004
35 #define RB_PIN_ENABLED__BANK3 0x0008
37 #define MULTIPLANE_OPERATION 0x70
38 #define MULTIPLANE_OPERATION__FLAG 0x0001
40 #define MULTIPLANE_READ_ENABLE 0x80
41 #define MULTIPLANE_READ_ENABLE__FLAG 0x0001
43 #define COPYBACK_DISABLE 0x90
44 #define COPYBACK_DISABLE__FLAG 0x0001
46 #define CACHE_WRITE_ENABLE 0xa0
47 #define CACHE_WRITE_ENABLE__FLAG 0x0001
49 #define CACHE_READ_ENABLE 0xb0
50 #define CACHE_READ_ENABLE__FLAG 0x0001
52 #define PREFETCH_MODE 0xc0
53 #define PREFETCH_MODE__PREFETCH_EN 0x0001
54 #define PREFETCH_MODE__PREFETCH_BURST_LENGTH 0xfff0
56 #define CHIP_ENABLE_DONT_CARE 0xd0
57 #define CHIP_EN_DONT_CARE__FLAG 0x01
59 #define ECC_ENABLE 0xe0
60 #define ECC_ENABLE__FLAG 0x0001
62 #define GLOBAL_INT_ENABLE 0xf0
63 #define GLOBAL_INT_EN_FLAG 0x01
66 #define WE_2_RE__VALUE 0x003f
68 #define ADDR_2_DATA 0x110
69 #define ADDR_2_DATA__VALUE 0x003f
72 #define RE_2_WE__VALUE 0x003f
74 #define ACC_CLKS 0x130
75 #define ACC_CLKS__VALUE 0x000f
77 #define NUMBER_OF_PLANES 0x140
78 #define NUMBER_OF_PLANES__VALUE 0x0007
80 #define PAGES_PER_BLOCK 0x150
81 #define PAGES_PER_BLOCK__VALUE 0xffff
83 #define DEVICE_WIDTH 0x160
84 #define DEVICE_WIDTH__VALUE 0x0003
86 #define DEVICE_MAIN_AREA_SIZE 0x170
87 #define DEVICE_MAIN_AREA_SIZE__VALUE 0xffff
89 #define DEVICE_SPARE_AREA_SIZE 0x180
90 #define DEVICE_SPARE_AREA_SIZE__VALUE 0xffff
92 #define TWO_ROW_ADDR_CYCLES 0x190
93 #define TWO_ROW_ADDR_CYCLES__FLAG 0x0001
95 #define MULTIPLANE_ADDR_RESTRICT 0x1a0
96 #define MULTIPLANE_ADDR_RESTRICT__FLAG 0x0001
98 #define ECC_CORRECTION 0x1b0
99 #define ECC_CORRECTION__VALUE 0x001f
101 #define READ_MODE 0x1c0
102 #define READ_MODE__VALUE 0x000f
104 #define WRITE_MODE 0x1d0
105 #define WRITE_MODE__VALUE 0x000f
107 #define COPYBACK_MODE 0x1e0
108 #define COPYBACK_MODE__VALUE 0x000f
110 #define RDWR_EN_LO_CNT 0x1f0
111 #define RDWR_EN_LO_CNT__VALUE 0x001f
113 #define RDWR_EN_HI_CNT 0x200
114 #define RDWR_EN_HI_CNT__VALUE 0x001f
116 #define MAX_RD_DELAY 0x210
117 #define MAX_RD_DELAY__VALUE 0x000f
119 #define CS_SETUP_CNT 0x220
120 #define CS_SETUP_CNT__VALUE 0x001f
122 #define SPARE_AREA_SKIP_BYTES 0x230
123 #define SPARE_AREA_SKIP_BYTES__VALUE 0x003f
125 #define SPARE_AREA_MARKER 0x240
126 #define SPARE_AREA_MARKER__VALUE 0xffff
128 #define DEVICES_CONNECTED 0x250
129 #define DEVICES_CONNECTED__VALUE 0x0007
131 #define DIE_MASK 0x260
132 #define DIE_MASK__VALUE 0x00ff
134 #define FIRST_BLOCK_OF_NEXT_PLANE 0x270
135 #define FIRST_BLOCK_OF_NEXT_PLANE__VALUE 0xffff
137 #define WRITE_PROTECT 0x280
138 #define WRITE_PROTECT__FLAG 0x0001
140 #define RE_2_RE 0x290
141 #define RE_2_RE__VALUE 0x003f
143 #define MANUFACTURER_ID 0x300
144 #define MANUFACTURER_ID__VALUE 0x00ff
146 #define DEVICE_ID 0x310
147 #define DEVICE_ID__VALUE 0x00ff
149 #define DEVICE_PARAM_0 0x320
150 #define DEVICE_PARAM_0__VALUE 0x00ff
152 #define DEVICE_PARAM_1 0x330
153 #define DEVICE_PARAM_1__VALUE 0x00ff
155 #define DEVICE_PARAM_2 0x340
156 #define DEVICE_PARAM_2__VALUE 0x00ff
158 #define LOGICAL_PAGE_DATA_SIZE 0x350
159 #define LOGICAL_PAGE_DATA_SIZE__VALUE 0xffff
161 #define LOGICAL_PAGE_SPARE_SIZE 0x360
162 #define LOGICAL_PAGE_SPARE_SIZE__VALUE 0xffff
164 #define REVISION 0x370
165 #define REVISION__VALUE 0xffff
167 #define ONFI_DEVICE_FEATURES 0x380
168 #define ONFI_DEVICE_FEATURES__VALUE 0x003f
170 #define ONFI_OPTIONAL_COMMANDS 0x390
171 #define ONFI_OPTIONAL_COMMANDS__VALUE 0x003f
173 #define ONFI_TIMING_MODE 0x3a0
174 #define ONFI_TIMING_MODE__VALUE 0x003f
176 #define ONFI_PGM_CACHE_TIMING_MODE 0x3b0
177 #define ONFI_PGM_CACHE_TIMING_MODE__VALUE 0x003f
179 #define ONFI_DEVICE_NO_OF_LUNS 0x3c0
180 #define ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS 0x00ff
181 #define ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE 0x0100
183 #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L 0x3d0
184 #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L__VALUE 0xffff
186 #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U 0x3e0
187 #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U__VALUE 0xffff
189 #define FEATURES 0x3f0
190 #define FEATURES__N_BANKS 0x0003
191 #define FEATURES__ECC_MAX_ERR 0x003c
192 #define FEATURES__DMA 0x0040
193 #define FEATURES__CMD_DMA 0x0080
194 #define FEATURES__PARTITION 0x0100
195 #define FEATURES__XDMA_SIDEBAND 0x0200
196 #define FEATURES__GPREG 0x0400
197 #define FEATURES__INDEX_ADDR 0x0800
199 #define TRANSFER_MODE 0x400
200 #define TRANSFER_MODE__VALUE 0x0003
202 #define INTR_STATUS(__bank) (0x410 + ((__bank) * 0x50))
203 #define INTR_EN(__bank) (0x420 + ((__bank) * 0x50))
206 * Some versions of the IP have the ECC fixup handled in hardware. In this
207 * configuration we only get interrupted when the error is uncorrectable.
208 * Unfortunately this bit replaces INTR_STATUS__ECC_TRANSACTION_DONE from the
211 #define INTR_STATUS__ECC_UNCOR_ERR 0x0001
212 #define INTR_STATUS__ECC_TRANSACTION_DONE 0x0001
213 #define INTR_STATUS__ECC_ERR 0x0002
214 #define INTR_STATUS__DMA_CMD_COMP 0x0004
215 #define INTR_STATUS__TIME_OUT 0x0008
216 #define INTR_STATUS__PROGRAM_FAIL 0x0010
217 #define INTR_STATUS__ERASE_FAIL 0x0020
218 #define INTR_STATUS__LOAD_COMP 0x0040
219 #define INTR_STATUS__PROGRAM_COMP 0x0080
220 #define INTR_STATUS__ERASE_COMP 0x0100
221 #define INTR_STATUS__PIPE_CPYBCK_CMD_COMP 0x0200
222 #define INTR_STATUS__LOCKED_BLK 0x0400
223 #define INTR_STATUS__UNSUP_CMD 0x0800
224 #define INTR_STATUS__INT_ACT 0x1000
225 #define INTR_STATUS__RST_COMP 0x2000
226 #define INTR_STATUS__PIPE_CMD_ERR 0x4000
227 #define INTR_STATUS__PAGE_XFER_INC 0x8000
229 #define INTR_EN__ECC_TRANSACTION_DONE 0x0001
230 #define INTR_EN__ECC_ERR 0x0002
231 #define INTR_EN__DMA_CMD_COMP 0x0004
232 #define INTR_EN__TIME_OUT 0x0008
233 #define INTR_EN__PROGRAM_FAIL 0x0010
234 #define INTR_EN__ERASE_FAIL 0x0020
235 #define INTR_EN__LOAD_COMP 0x0040
236 #define INTR_EN__PROGRAM_COMP 0x0080
237 #define INTR_EN__ERASE_COMP 0x0100
238 #define INTR_EN__PIPE_CPYBCK_CMD_COMP 0x0200
239 #define INTR_EN__LOCKED_BLK 0x0400
240 #define INTR_EN__UNSUP_CMD 0x0800
241 #define INTR_EN__INT_ACT 0x1000
242 #define INTR_EN__RST_COMP 0x2000
243 #define INTR_EN__PIPE_CMD_ERR 0x4000
244 #define INTR_EN__PAGE_XFER_INC 0x8000
246 #define PAGE_CNT(__bank) (0x430 + ((__bank) * 0x50))
247 #define ERR_PAGE_ADDR(__bank) (0x440 + ((__bank) * 0x50))
248 #define ERR_BLOCK_ADDR(__bank) (0x450 + ((__bank) * 0x50))
250 #define DATA_INTR 0x550
251 #define DATA_INTR__WRITE_SPACE_AV 0x0001
252 #define DATA_INTR__READ_DATA_AV 0x0002
254 #define DATA_INTR_EN 0x560
255 #define DATA_INTR_EN__WRITE_SPACE_AV 0x0001
256 #define DATA_INTR_EN__READ_DATA_AV 0x0002
258 #define GPREG_0 0x570
259 #define GPREG_0__VALUE 0xffff
261 #define GPREG_1 0x580
262 #define GPREG_1__VALUE 0xffff
264 #define GPREG_2 0x590
265 #define GPREG_2__VALUE 0xffff
267 #define GPREG_3 0x5a0
268 #define GPREG_3__VALUE 0xffff
270 #define ECC_THRESHOLD 0x600
271 #define ECC_THRESHOLD__VALUE 0x03ff
273 #define ECC_ERROR_BLOCK_ADDRESS 0x610
274 #define ECC_ERROR_BLOCK_ADDRESS__VALUE 0xffff
276 #define ECC_ERROR_PAGE_ADDRESS 0x620
277 #define ECC_ERROR_PAGE_ADDRESS__VALUE 0x0fff
278 #define ECC_ERROR_PAGE_ADDRESS__BANK 0xf000
280 #define ECC_ERROR_ADDRESS 0x630
281 #define ECC_ERROR_ADDRESS__OFFSET 0x0fff
282 #define ECC_ERROR_ADDRESS__SECTOR_NR 0xf000
284 #define ERR_CORRECTION_INFO 0x640
285 #define ERR_CORRECTION_INFO__BYTEMASK 0x00ff
286 #define ERR_CORRECTION_INFO__DEVICE_NR 0x0f00
287 #define ERR_CORRECTION_INFO__ERROR_TYPE 0x4000
288 #define ERR_CORRECTION_INFO__LAST_ERR_INFO 0x8000
290 #define DMA_ENABLE 0x700
291 #define DMA_ENABLE__FLAG 0x0001
293 #define IGNORE_ECC_DONE 0x710
294 #define IGNORE_ECC_DONE__FLAG 0x0001
296 #define DMA_INTR 0x720
297 #define DMA_INTR__TARGET_ERROR 0x0001
298 #define DMA_INTR__DESC_COMP_CHANNEL0 0x0002
299 #define DMA_INTR__DESC_COMP_CHANNEL1 0x0004
300 #define DMA_INTR__DESC_COMP_CHANNEL2 0x0008
301 #define DMA_INTR__DESC_COMP_CHANNEL3 0x0010
302 #define DMA_INTR__MEMCOPY_DESC_COMP 0x0020
304 #define DMA_INTR_EN 0x730
305 #define DMA_INTR_EN__TARGET_ERROR 0x0001
306 #define DMA_INTR_EN__DESC_COMP_CHANNEL0 0x0002
307 #define DMA_INTR_EN__DESC_COMP_CHANNEL1 0x0004
308 #define DMA_INTR_EN__DESC_COMP_CHANNEL2 0x0008
309 #define DMA_INTR_EN__DESC_COMP_CHANNEL3 0x0010
310 #define DMA_INTR_EN__MEMCOPY_DESC_COMP 0x0020
312 #define TARGET_ERR_ADDR_LO 0x740
313 #define TARGET_ERR_ADDR_LO__VALUE 0xffff
315 #define TARGET_ERR_ADDR_HI 0x750
316 #define TARGET_ERR_ADDR_HI__VALUE 0xffff
318 #define CHNL_ACTIVE 0x760
319 #define CHNL_ACTIVE__CHANNEL0 0x0001
320 #define CHNL_ACTIVE__CHANNEL1 0x0002
321 #define CHNL_ACTIVE__CHANNEL2 0x0004
322 #define CHNL_ACTIVE__CHANNEL3 0x0008
324 #define ACTIVE_SRC_ID 0x800
325 #define ACTIVE_SRC_ID__VALUE 0x00ff
327 #define PTN_INTR 0x810
328 #define PTN_INTR__CONFIG_ERROR 0x0001
329 #define PTN_INTR__ACCESS_ERROR_BANK0 0x0002
330 #define PTN_INTR__ACCESS_ERROR_BANK1 0x0004
331 #define PTN_INTR__ACCESS_ERROR_BANK2 0x0008
332 #define PTN_INTR__ACCESS_ERROR_BANK3 0x0010
333 #define PTN_INTR__REG_ACCESS_ERROR 0x0020
335 #define PTN_INTR_EN 0x820
336 #define PTN_INTR_EN__CONFIG_ERROR 0x0001
337 #define PTN_INTR_EN__ACCESS_ERROR_BANK0 0x0002
338 #define PTN_INTR_EN__ACCESS_ERROR_BANK1 0x0004
339 #define PTN_INTR_EN__ACCESS_ERROR_BANK2 0x0008
340 #define PTN_INTR_EN__ACCESS_ERROR_BANK3 0x0010
341 #define PTN_INTR_EN__REG_ACCESS_ERROR 0x0020
343 #define PERM_SRC_ID(__bank) (0x830 + ((__bank) * 0x40))
344 #define PERM_SRC_ID__SRCID 0x00ff
345 #define PERM_SRC_ID__DIRECT_ACCESS_ACTIVE 0x0800
346 #define PERM_SRC_ID__WRITE_ACTIVE 0x2000
347 #define PERM_SRC_ID__READ_ACTIVE 0x4000
348 #define PERM_SRC_ID__PARTITION_VALID 0x8000
350 #define MIN_BLK_ADDR(__bank) (0x840 + ((__bank) * 0x40))
351 #define MIN_BLK_ADDR__VALUE 0xffff
353 #define MAX_BLK_ADDR(__bank) (0x850 + ((__bank) * 0x40))
354 #define MAX_BLK_ADDR__VALUE 0xffff
356 #define MIN_MAX_BANK(__bank) (0x860 + ((__bank) * 0x40))
357 #define MIN_MAX_BANK__MIN_VALUE 0x0003
358 #define MIN_MAX_BANK__MAX_VALUE 0x000c
362 #define DEFECTIVE_BLOCK 1
368 /* spectraswconfig.h */
371 #define SPECTRA_PARTITION_ID 0
372 /**** Block Table and Reserved Block Parameters *****/
373 #define SPECTRA_START_BLOCK 3
374 #define NUM_FREE_BLOCKS_GATE 30
376 /* KBV - Updated to LNW scratch register address */
377 #define SCRATCH_REG_ADDR CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR
378 #define SCRATCH_REG_SIZE 64
380 #define GLOB_HWCTL_DEFAULT_BLKS 2048
382 #define CUSTOM_CONF_PARAMS 0
387 #define INDEX_CTRL_REG 0x0
388 #define INDEX_DATA_REG 0x10
390 #define MODE_00 0x00000000
391 #define MODE_01 0x04000000
392 #define MODE_10 0x08000000
393 #define MODE_11 0x0C000000
396 #define DATA_TRANSFER_MODE 0
397 #define PROTECTION_PER_BLOCK 1
398 #define LOAD_WAIT_COUNT 2
399 #define PROGRAM_WAIT_COUNT 3
400 #define ERASE_WAIT_COUNT 4
401 #define INT_MONITOR_CYCLE_COUNT 5
402 #define READ_BUSY_PIN_ENABLED 6
403 #define MULTIPLANE_OPERATION_SUPPORT 7
404 #define PRE_FETCH_MODE 8
405 #define CE_DONT_CARE_SUPPORT 9
406 #define COPYBACK_SUPPORT 10
407 #define CACHE_WRITE_SUPPORT 11
408 #define CACHE_READ_SUPPORT 12
409 #define NUM_PAGES_IN_BLOCK 13
410 #define ECC_ENABLE_SELECT 14
411 #define WRITE_ENABLE_2_READ_ENABLE 15
412 #define ADDRESS_2_DATA 16
413 #define READ_ENABLE_2_WRITE_ENABLE 17
414 #define TWO_ROW_ADDRESS_CYCLES 18
415 #define MULTIPLANE_ADDRESS_RESTRICT 19
416 #define ACC_CLOCKS 20
417 #define READ_WRITE_ENABLE_LOW_COUNT 21
418 #define READ_WRITE_ENABLE_HIGH_COUNT 22
420 #define ECC_SECTOR_SIZE 512
422 #define DENALI_BUF_SIZE (NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE)
427 /* seprating dma_buf as buf can be used for status read purpose */
428 uint8_t dma_buf[DENALI_BUF_SIZE] __aligned(64);
429 uint8_t buf[DENALI_BUF_SIZE];
432 #define INTEL_CE4100 1
436 struct denali_nand_info {
438 struct nand_chip *nand;
440 int flash_bank; /* currently selected chip */
445 int total_used_banks;
446 uint32_t block; /* stored for future use */
448 void __iomem *flash_reg; /* Mapped io reg base address */
449 void __iomem *flash_mem; /* Mapped io reg base address */
451 /* elements used by ISR */
452 /*struct completion complete;*/
455 int irq_debug_array[32];
459 uint32_t devnum; /* represent how many nands connected */
460 uint32_t fwblks; /* represent how many blocks FW used */
462 uint32_t blksperchip;
463 uint32_t bbtskipbytes;
467 #endif /*_LLD_NAND_*/