2 * NAND Flash Controller Device Driver
3 * Copyright (c) 2009 - 2010, Intel Corporation and its suppliers.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
23 #include <linux/bitops.h>
24 #include <linux/mtd/nand.h>
26 #define DEVICE_RESET 0x0
27 #define DEVICE_RESET__BANK(bank) BIT(bank)
29 #define TRANSFER_SPARE_REG 0x10
30 #define TRANSFER_SPARE_REG__FLAG BIT(0)
32 #define LOAD_WAIT_CNT 0x20
33 #define LOAD_WAIT_CNT__VALUE GENMASK(15, 0)
35 #define PROGRAM_WAIT_CNT 0x30
36 #define PROGRAM_WAIT_CNT__VALUE GENMASK(15, 0)
38 #define ERASE_WAIT_CNT 0x40
39 #define ERASE_WAIT_CNT__VALUE GENMASK(15, 0)
41 #define INT_MON_CYCCNT 0x50
42 #define INT_MON_CYCCNT__VALUE GENMASK(15, 0)
44 #define RB_PIN_ENABLED 0x60
45 #define RB_PIN_ENABLED__BANK(bank) BIT(bank)
47 #define MULTIPLANE_OPERATION 0x70
48 #define MULTIPLANE_OPERATION__FLAG BIT(0)
50 #define MULTIPLANE_READ_ENABLE 0x80
51 #define MULTIPLANE_READ_ENABLE__FLAG BIT(0)
53 #define COPYBACK_DISABLE 0x90
54 #define COPYBACK_DISABLE__FLAG BIT(0)
56 #define CACHE_WRITE_ENABLE 0xa0
57 #define CACHE_WRITE_ENABLE__FLAG BIT(0)
59 #define CACHE_READ_ENABLE 0xb0
60 #define CACHE_READ_ENABLE__FLAG BIT(0)
62 #define PREFETCH_MODE 0xc0
63 #define PREFETCH_MODE__PREFETCH_EN BIT(0)
64 #define PREFETCH_MODE__PREFETCH_BURST_LENGTH GENMASK(15, 4)
66 #define CHIP_ENABLE_DONT_CARE 0xd0
67 #define CHIP_EN_DONT_CARE__FLAG BIT(0)
69 #define ECC_ENABLE 0xe0
70 #define ECC_ENABLE__FLAG BIT(0)
72 #define GLOBAL_INT_ENABLE 0xf0
73 #define GLOBAL_INT_EN_FLAG BIT(0)
75 #define TWHR2_AND_WE_2_RE 0x100
76 #define TWHR2_AND_WE_2_RE__WE_2_RE GENMASK(5, 0)
77 #define TWHR2_AND_WE_2_RE__TWHR2 GENMASK(13, 8)
79 #define TCWAW_AND_ADDR_2_DATA 0x110
80 /* The width of ADDR_2_DATA is 6 bit for old IP, 7 bit for new IP */
81 #define TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA GENMASK(6, 0)
82 #define TCWAW_AND_ADDR_2_DATA__TCWAW GENMASK(13, 8)
85 #define RE_2_WE__VALUE GENMASK(5, 0)
87 #define ACC_CLKS 0x130
88 #define ACC_CLKS__VALUE GENMASK(3, 0)
90 #define NUMBER_OF_PLANES 0x140
91 #define NUMBER_OF_PLANES__VALUE GENMASK(2, 0)
93 #define PAGES_PER_BLOCK 0x150
94 #define PAGES_PER_BLOCK__VALUE GENMASK(15, 0)
96 #define DEVICE_WIDTH 0x160
97 #define DEVICE_WIDTH__VALUE GENMASK(1, 0)
99 #define DEVICE_MAIN_AREA_SIZE 0x170
100 #define DEVICE_MAIN_AREA_SIZE__VALUE GENMASK(15, 0)
102 #define DEVICE_SPARE_AREA_SIZE 0x180
103 #define DEVICE_SPARE_AREA_SIZE__VALUE GENMASK(15, 0)
105 #define TWO_ROW_ADDR_CYCLES 0x190
106 #define TWO_ROW_ADDR_CYCLES__FLAG BIT(0)
108 #define MULTIPLANE_ADDR_RESTRICT 0x1a0
109 #define MULTIPLANE_ADDR_RESTRICT__FLAG BIT(0)
111 #define ECC_CORRECTION 0x1b0
112 #define ECC_CORRECTION__VALUE GENMASK(4, 0)
113 #define ECC_CORRECTION__ERASE_THRESHOLD GENMASK(31, 16)
114 #define MAKE_ECC_CORRECTION(val, thresh) \
115 (((val) & (ECC_CORRECTION__VALUE)) | \
116 (((thresh) << 16) & (ECC_CORRECTION__ERASE_THRESHOLD)))
118 #define READ_MODE 0x1c0
119 #define READ_MODE__VALUE GENMASK(3, 0)
121 #define WRITE_MODE 0x1d0
122 #define WRITE_MODE__VALUE GENMASK(3, 0)
124 #define COPYBACK_MODE 0x1e0
125 #define COPYBACK_MODE__VALUE GENMASK(3, 0)
127 #define RDWR_EN_LO_CNT 0x1f0
128 #define RDWR_EN_LO_CNT__VALUE GENMASK(4, 0)
130 #define RDWR_EN_HI_CNT 0x200
131 #define RDWR_EN_HI_CNT__VALUE GENMASK(4, 0)
133 #define MAX_RD_DELAY 0x210
134 #define MAX_RD_DELAY__VALUE GENMASK(3, 0)
136 #define CS_SETUP_CNT 0x220
137 #define CS_SETUP_CNT__VALUE GENMASK(4, 0)
138 #define CS_SETUP_CNT__TWB GENMASK(17, 12)
140 #define SPARE_AREA_SKIP_BYTES 0x230
141 #define SPARE_AREA_SKIP_BYTES__VALUE GENMASK(5, 0)
143 #define SPARE_AREA_MARKER 0x240
144 #define SPARE_AREA_MARKER__VALUE GENMASK(15, 0)
146 #define DEVICES_CONNECTED 0x250
147 #define DEVICES_CONNECTED__VALUE GENMASK(2, 0)
149 #define DIE_MASK 0x260
150 #define DIE_MASK__VALUE GENMASK(7, 0)
152 #define FIRST_BLOCK_OF_NEXT_PLANE 0x270
153 #define FIRST_BLOCK_OF_NEXT_PLANE__VALUE GENMASK(15, 0)
155 #define WRITE_PROTECT 0x280
156 #define WRITE_PROTECT__FLAG BIT(0)
158 #define RE_2_RE 0x290
159 #define RE_2_RE__VALUE GENMASK(5, 0)
161 #define MANUFACTURER_ID 0x300
162 #define MANUFACTURER_ID__VALUE GENMASK(7, 0)
164 #define DEVICE_ID 0x310
165 #define DEVICE_ID__VALUE GENMASK(7, 0)
167 #define DEVICE_PARAM_0 0x320
168 #define DEVICE_PARAM_0__VALUE GENMASK(7, 0)
170 #define DEVICE_PARAM_1 0x330
171 #define DEVICE_PARAM_1__VALUE GENMASK(7, 0)
173 #define DEVICE_PARAM_2 0x340
174 #define DEVICE_PARAM_2__VALUE GENMASK(7, 0)
176 #define LOGICAL_PAGE_DATA_SIZE 0x350
177 #define LOGICAL_PAGE_DATA_SIZE__VALUE GENMASK(15, 0)
179 #define LOGICAL_PAGE_SPARE_SIZE 0x360
180 #define LOGICAL_PAGE_SPARE_SIZE__VALUE GENMASK(15, 0)
182 #define REVISION 0x370
183 #define REVISION__VALUE GENMASK(15, 0)
185 #define ONFI_DEVICE_FEATURES 0x380
186 #define ONFI_DEVICE_FEATURES__VALUE GENMASK(5, 0)
188 #define ONFI_OPTIONAL_COMMANDS 0x390
189 #define ONFI_OPTIONAL_COMMANDS__VALUE GENMASK(5, 0)
191 #define ONFI_TIMING_MODE 0x3a0
192 #define ONFI_TIMING_MODE__VALUE GENMASK(5, 0)
194 #define ONFI_PGM_CACHE_TIMING_MODE 0x3b0
195 #define ONFI_PGM_CACHE_TIMING_MODE__VALUE GENMASK(5, 0)
197 #define ONFI_DEVICE_NO_OF_LUNS 0x3c0
198 #define ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS GENMASK(7, 0)
199 #define ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE BIT(8)
201 #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L 0x3d0
202 #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L__VALUE GENMASK(15, 0)
204 #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U 0x3e0
205 #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U__VALUE GENMASK(15, 0)
207 #define FEATURES 0x3f0
208 #define FEATURES__N_BANKS GENMASK(1, 0)
209 #define FEATURES__ECC_MAX_ERR GENMASK(5, 2)
210 #define FEATURES__DMA BIT(6)
211 #define FEATURES__CMD_DMA BIT(7)
212 #define FEATURES__PARTITION BIT(8)
213 #define FEATURES__XDMA_SIDEBAND BIT(9)
214 #define FEATURES__GPREG BIT(10)
215 #define FEATURES__INDEX_ADDR BIT(11)
217 #define TRANSFER_MODE 0x400
218 #define TRANSFER_MODE__VALUE GENMASK(1, 0)
220 #define INTR_STATUS(bank) (0x410 + (bank) * 0x50)
221 #define INTR_EN(bank) (0x420 + (bank) * 0x50)
222 /* bit[1:0] is used differently depending on IP version */
223 #define INTR__ECC_UNCOR_ERR BIT(0) /* new IP */
224 #define INTR__ECC_TRANSACTION_DONE BIT(0) /* old IP */
225 #define INTR__ECC_ERR BIT(1) /* old IP */
226 #define INTR__DMA_CMD_COMP BIT(2)
227 #define INTR__TIME_OUT BIT(3)
228 #define INTR__PROGRAM_FAIL BIT(4)
229 #define INTR__ERASE_FAIL BIT(5)
230 #define INTR__LOAD_COMP BIT(6)
231 #define INTR__PROGRAM_COMP BIT(7)
232 #define INTR__ERASE_COMP BIT(8)
233 #define INTR__PIPE_CPYBCK_CMD_COMP BIT(9)
234 #define INTR__LOCKED_BLK BIT(10)
235 #define INTR__UNSUP_CMD BIT(11)
236 #define INTR__INT_ACT BIT(12)
237 #define INTR__RST_COMP BIT(13)
238 #define INTR__PIPE_CMD_ERR BIT(14)
239 #define INTR__PAGE_XFER_INC BIT(15)
240 #define INTR__ERASED_PAGE BIT(16)
242 #define PAGE_CNT(bank) (0x430 + (bank) * 0x50)
243 #define ERR_PAGE_ADDR(bank) (0x440 + (bank) * 0x50)
244 #define ERR_BLOCK_ADDR(bank) (0x450 + (bank) * 0x50)
246 #define ECC_THRESHOLD 0x600
247 #define ECC_THRESHOLD__VALUE GENMASK(9, 0)
249 #define ECC_ERROR_BLOCK_ADDRESS 0x610
250 #define ECC_ERROR_BLOCK_ADDRESS__VALUE GENMASK(15, 0)
252 #define ECC_ERROR_PAGE_ADDRESS 0x620
253 #define ECC_ERROR_PAGE_ADDRESS__VALUE GENMASK(11, 0)
254 #define ECC_ERROR_PAGE_ADDRESS__BANK GENMASK(15, 12)
256 #define ECC_ERROR_ADDRESS 0x630
257 #define ECC_ERROR_ADDRESS__OFFSET GENMASK(11, 0)
258 #define ECC_ERROR_ADDRESS__SECTOR_NR GENMASK(15, 12)
260 #define ERR_CORRECTION_INFO 0x640
261 #define ERR_CORRECTION_INFO__BYTEMASK GENMASK(7, 0)
262 #define ERR_CORRECTION_INFO__DEVICE_NR GENMASK(11, 8)
263 #define ERR_CORRECTION_INFO__ERROR_TYPE BIT(14)
264 #define ERR_CORRECTION_INFO__LAST_ERR_INFO BIT(15)
266 #define ECC_COR_INFO(bank) (0x650 + (bank) / 2 * 0x10)
267 #define ECC_COR_INFO__SHIFT(bank) ((bank) % 2 * 8)
268 #define ECC_COR_INFO__MAX_ERRORS GENMASK(6, 0)
269 #define ECC_COR_INFO__UNCOR_ERR BIT(7)
271 #define CFG_DATA_BLOCK_SIZE 0x6b0
273 #define CFG_LAST_DATA_BLOCK_SIZE 0x6c0
275 #define CFG_NUM_DATA_BLOCKS 0x6d0
277 #define CFG_META_DATA_SIZE 0x6e0
279 #define DMA_ENABLE 0x700
280 #define DMA_ENABLE__FLAG BIT(0)
282 #define IGNORE_ECC_DONE 0x710
283 #define IGNORE_ECC_DONE__FLAG BIT(0)
285 #define DMA_INTR 0x720
286 #define DMA_INTR_EN 0x730
287 #define DMA_INTR__TARGET_ERROR BIT(0)
288 #define DMA_INTR__DESC_COMP_CHANNEL0 BIT(1)
289 #define DMA_INTR__DESC_COMP_CHANNEL1 BIT(2)
290 #define DMA_INTR__DESC_COMP_CHANNEL2 BIT(3)
291 #define DMA_INTR__DESC_COMP_CHANNEL3 BIT(4)
292 #define DMA_INTR__MEMCOPY_DESC_COMP BIT(5)
294 #define TARGET_ERR_ADDR_LO 0x740
295 #define TARGET_ERR_ADDR_LO__VALUE GENMASK(15, 0)
297 #define TARGET_ERR_ADDR_HI 0x750
298 #define TARGET_ERR_ADDR_HI__VALUE GENMASK(15, 0)
300 #define CHNL_ACTIVE 0x760
301 #define CHNL_ACTIVE__CHANNEL0 BIT(0)
302 #define CHNL_ACTIVE__CHANNEL1 BIT(1)
303 #define CHNL_ACTIVE__CHANNEL2 BIT(2)
304 #define CHNL_ACTIVE__CHANNEL3 BIT(3)
306 struct denali_nand_info {
307 struct nand_chip nand;
308 unsigned long clk_x_rate; /* bus interface clock rate */
309 int active_bank; /* currently selected bank */
311 void __iomem *reg; /* Register Interface */
312 void __iomem *host; /* Host Data/Command Interface */
314 /* elements used by ISR */
315 struct completion complete;
324 int devs_per_cs; /* devices connected in parallel */
327 unsigned int revision;
329 const struct nand_ecc_caps *ecc_caps;
332 #define DENALI_CAP_HW_ECC_FIXUP BIT(0)
333 #define DENALI_CAP_DMA_64BIT BIT(1)
335 int denali_calc_ecc_bytes(int step_size, int strength);
336 extern int denali_init(struct denali_nand_info *denali);
337 extern void denali_remove(struct denali_nand_info *denali);
339 #endif /* __DENALI_H__ */