2 * NAND Flash Controller Device Driver
3 * Copyright © 2009-2010, Intel Corporation and its suppliers.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/bitfield.h>
16 #include <linux/completion.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/interrupt.h>
20 #include <linux/module.h>
21 #include <linux/mtd/mtd.h>
22 #include <linux/mtd/rawnand.h>
23 #include <linux/slab.h>
24 #include <linux/spinlock.h>
28 MODULE_LICENSE("GPL");
30 #define DENALI_NAND_NAME "denali-nand"
32 /* Host Data/Command Interface */
33 #define DENALI_HOST_ADDR 0x00
34 #define DENALI_HOST_DATA 0x10
36 #define DENALI_MAP00 (0 << 26) /* direct access to buffer */
37 #define DENALI_MAP01 (1 << 26) /* read/write pages in PIO */
38 #define DENALI_MAP10 (2 << 26) /* high-level control plane */
39 #define DENALI_MAP11 (3 << 26) /* direct controller access */
41 /* MAP11 access cycle type */
42 #define DENALI_MAP11_CMD ((DENALI_MAP11) | 0) /* command cycle */
43 #define DENALI_MAP11_ADDR ((DENALI_MAP11) | 1) /* address cycle */
44 #define DENALI_MAP11_DATA ((DENALI_MAP11) | 2) /* data cycle */
47 #define DENALI_ERASE 0x01
49 #define DENALI_BANK(denali) ((denali)->active_bank << 24)
51 #define DENALI_INVALID_BANK -1
52 #define DENALI_NR_BANKS 4
55 * The bus interface clock, clk_x, is phase aligned with the core clock. The
56 * clk_x is an integral multiple N of the core clk. The value N is configured
57 * at IP delivery time, and its available value is 4, 5, or 6. We need to align
58 * to the largest value to make it work with any possible configuration.
60 #define DENALI_CLK_X_MULT 6
62 static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd)
64 return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand);
67 static void denali_host_write(struct denali_nand_info *denali,
68 uint32_t addr, uint32_t data)
70 iowrite32(addr, denali->host + DENALI_HOST_ADDR);
71 iowrite32(data, denali->host + DENALI_HOST_DATA);
75 * Use the configuration feature register to determine the maximum number of
76 * banks that the hardware supports.
78 static void denali_detect_max_banks(struct denali_nand_info *denali)
80 uint32_t features = ioread32(denali->reg + FEATURES);
82 denali->max_banks = 1 << FIELD_GET(FEATURES__N_BANKS, features);
84 /* the encoding changed from rev 5.0 to 5.1 */
85 if (denali->revision < 0x0501)
86 denali->max_banks <<= 1;
89 static void denali_enable_irq(struct denali_nand_info *denali)
93 for (i = 0; i < DENALI_NR_BANKS; i++)
94 iowrite32(U32_MAX, denali->reg + INTR_EN(i));
95 iowrite32(GLOBAL_INT_EN_FLAG, denali->reg + GLOBAL_INT_ENABLE);
98 static void denali_disable_irq(struct denali_nand_info *denali)
102 for (i = 0; i < DENALI_NR_BANKS; i++)
103 iowrite32(0, denali->reg + INTR_EN(i));
104 iowrite32(0, denali->reg + GLOBAL_INT_ENABLE);
107 static void denali_clear_irq(struct denali_nand_info *denali,
108 int bank, uint32_t irq_status)
110 /* write one to clear bits */
111 iowrite32(irq_status, denali->reg + INTR_STATUS(bank));
114 static void denali_clear_irq_all(struct denali_nand_info *denali)
118 for (i = 0; i < DENALI_NR_BANKS; i++)
119 denali_clear_irq(denali, i, U32_MAX);
122 static irqreturn_t denali_isr(int irq, void *dev_id)
124 struct denali_nand_info *denali = dev_id;
125 irqreturn_t ret = IRQ_NONE;
129 spin_lock(&denali->irq_lock);
131 for (i = 0; i < DENALI_NR_BANKS; i++) {
132 irq_status = ioread32(denali->reg + INTR_STATUS(i));
136 denali_clear_irq(denali, i, irq_status);
138 if (i != denali->active_bank)
141 denali->irq_status |= irq_status;
143 if (denali->irq_status & denali->irq_mask)
144 complete(&denali->complete);
147 spin_unlock(&denali->irq_lock);
152 static void denali_reset_irq(struct denali_nand_info *denali)
156 spin_lock_irqsave(&denali->irq_lock, flags);
157 denali->irq_status = 0;
158 denali->irq_mask = 0;
159 spin_unlock_irqrestore(&denali->irq_lock, flags);
162 static uint32_t denali_wait_for_irq(struct denali_nand_info *denali,
165 unsigned long time_left, flags;
168 spin_lock_irqsave(&denali->irq_lock, flags);
170 irq_status = denali->irq_status;
172 if (irq_mask & irq_status) {
173 /* return immediately if the IRQ has already happened. */
174 spin_unlock_irqrestore(&denali->irq_lock, flags);
178 denali->irq_mask = irq_mask;
179 reinit_completion(&denali->complete);
180 spin_unlock_irqrestore(&denali->irq_lock, flags);
182 time_left = wait_for_completion_timeout(&denali->complete,
183 msecs_to_jiffies(1000));
185 dev_err(denali->dev, "timeout while waiting for irq 0x%x\n",
190 return denali->irq_status;
193 static uint32_t denali_check_irq(struct denali_nand_info *denali)
198 spin_lock_irqsave(&denali->irq_lock, flags);
199 irq_status = denali->irq_status;
200 spin_unlock_irqrestore(&denali->irq_lock, flags);
205 static void denali_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
207 struct denali_nand_info *denali = mtd_to_denali(mtd);
210 iowrite32(DENALI_MAP11_DATA | DENALI_BANK(denali),
211 denali->host + DENALI_HOST_ADDR);
213 for (i = 0; i < len; i++)
214 buf[i] = ioread32(denali->host + DENALI_HOST_DATA);
217 static void denali_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
219 struct denali_nand_info *denali = mtd_to_denali(mtd);
222 iowrite32(DENALI_MAP11_DATA | DENALI_BANK(denali),
223 denali->host + DENALI_HOST_ADDR);
225 for (i = 0; i < len; i++)
226 iowrite32(buf[i], denali->host + DENALI_HOST_DATA);
229 static void denali_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
231 struct denali_nand_info *denali = mtd_to_denali(mtd);
232 uint16_t *buf16 = (uint16_t *)buf;
235 iowrite32(DENALI_MAP11_DATA | DENALI_BANK(denali),
236 denali->host + DENALI_HOST_ADDR);
238 for (i = 0; i < len / 2; i++)
239 buf16[i] = ioread32(denali->host + DENALI_HOST_DATA);
242 static void denali_write_buf16(struct mtd_info *mtd, const uint8_t *buf,
245 struct denali_nand_info *denali = mtd_to_denali(mtd);
246 const uint16_t *buf16 = (const uint16_t *)buf;
249 iowrite32(DENALI_MAP11_DATA | DENALI_BANK(denali),
250 denali->host + DENALI_HOST_ADDR);
252 for (i = 0; i < len / 2; i++)
253 iowrite32(buf16[i], denali->host + DENALI_HOST_DATA);
256 static uint8_t denali_read_byte(struct mtd_info *mtd)
260 denali_read_buf(mtd, &byte, 1);
265 static void denali_write_byte(struct mtd_info *mtd, uint8_t byte)
267 denali_write_buf(mtd, &byte, 1);
270 static uint16_t denali_read_word(struct mtd_info *mtd)
274 denali_read_buf16(mtd, (uint8_t *)&word, 2);
279 static void denali_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
281 struct denali_nand_info *denali = mtd_to_denali(mtd);
285 type = DENALI_MAP11_CMD;
286 else if (ctrl & NAND_ALE)
287 type = DENALI_MAP11_ADDR;
292 * Some commands are followed by chip->dev_ready or chip->waitfunc.
293 * irq_status must be cleared here to catch the R/B# interrupt later.
295 if (ctrl & NAND_CTRL_CHANGE)
296 denali_reset_irq(denali);
298 denali_host_write(denali, DENALI_BANK(denali) | type, dat);
301 static int denali_dev_ready(struct mtd_info *mtd)
303 struct denali_nand_info *denali = mtd_to_denali(mtd);
305 return !!(denali_check_irq(denali) & INTR__INT_ACT);
308 static int denali_check_erased_page(struct mtd_info *mtd,
309 struct nand_chip *chip, uint8_t *buf,
310 unsigned long uncor_ecc_flags,
311 unsigned int max_bitflips)
313 uint8_t *ecc_code = chip->buffers->ecccode;
314 int ecc_steps = chip->ecc.steps;
315 int ecc_size = chip->ecc.size;
316 int ecc_bytes = chip->ecc.bytes;
319 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
324 for (i = 0; i < ecc_steps; i++) {
325 if (!(uncor_ecc_flags & BIT(i)))
328 stat = nand_check_erased_ecc_chunk(buf, ecc_size,
333 mtd->ecc_stats.failed++;
335 mtd->ecc_stats.corrected += stat;
336 max_bitflips = max_t(unsigned int, max_bitflips, stat);
340 ecc_code += ecc_bytes;
346 static int denali_hw_ecc_fixup(struct mtd_info *mtd,
347 struct denali_nand_info *denali,
348 unsigned long *uncor_ecc_flags)
350 struct nand_chip *chip = mtd_to_nand(mtd);
351 int bank = denali->active_bank;
353 unsigned int max_bitflips;
355 ecc_cor = ioread32(denali->reg + ECC_COR_INFO(bank));
356 ecc_cor >>= ECC_COR_INFO__SHIFT(bank);
358 if (ecc_cor & ECC_COR_INFO__UNCOR_ERR) {
360 * This flag is set when uncorrectable error occurs at least in
361 * one ECC sector. We can not know "how many sectors", or
362 * "which sector(s)". We need erase-page check for all sectors.
364 *uncor_ecc_flags = GENMASK(chip->ecc.steps - 1, 0);
368 max_bitflips = FIELD_GET(ECC_COR_INFO__MAX_ERRORS, ecc_cor);
371 * The register holds the maximum of per-sector corrected bitflips.
372 * This is suitable for the return value of the ->read_page() callback.
373 * Unfortunately, we can not know the total number of corrected bits in
374 * the page. Increase the stats by max_bitflips. (compromised solution)
376 mtd->ecc_stats.corrected += max_bitflips;
381 static int denali_sw_ecc_fixup(struct mtd_info *mtd,
382 struct denali_nand_info *denali,
383 unsigned long *uncor_ecc_flags, uint8_t *buf)
385 unsigned int ecc_size = denali->nand.ecc.size;
386 unsigned int bitflips = 0;
387 unsigned int max_bitflips = 0;
388 uint32_t err_addr, err_cor_info;
389 unsigned int err_byte, err_sector, err_device;
390 uint8_t err_cor_value;
391 unsigned int prev_sector = 0;
394 denali_reset_irq(denali);
397 err_addr = ioread32(denali->reg + ECC_ERROR_ADDRESS);
398 err_sector = FIELD_GET(ECC_ERROR_ADDRESS__SECTOR, err_addr);
399 err_byte = FIELD_GET(ECC_ERROR_ADDRESS__OFFSET, err_addr);
401 err_cor_info = ioread32(denali->reg + ERR_CORRECTION_INFO);
402 err_cor_value = FIELD_GET(ERR_CORRECTION_INFO__BYTE,
404 err_device = FIELD_GET(ERR_CORRECTION_INFO__DEVICE,
407 /* reset the bitflip counter when crossing ECC sector */
408 if (err_sector != prev_sector)
411 if (err_cor_info & ERR_CORRECTION_INFO__UNCOR) {
413 * Check later if this is a real ECC error, or
416 *uncor_ecc_flags |= BIT(err_sector);
417 } else if (err_byte < ecc_size) {
419 * If err_byte is larger than ecc_size, means error
420 * happened in OOB, so we ignore it. It's no need for
421 * us to correct it err_device is represented the NAND
422 * error bits are happened in if there are more than
423 * one NAND connected.
426 unsigned int flips_in_byte;
428 offset = (err_sector * ecc_size + err_byte) *
429 denali->devs_per_cs + err_device;
431 /* correct the ECC error */
432 flips_in_byte = hweight8(buf[offset] ^ err_cor_value);
433 buf[offset] ^= err_cor_value;
434 mtd->ecc_stats.corrected += flips_in_byte;
435 bitflips += flips_in_byte;
437 max_bitflips = max(max_bitflips, bitflips);
440 prev_sector = err_sector;
441 } while (!(err_cor_info & ERR_CORRECTION_INFO__LAST_ERR));
444 * Once handle all ECC errors, controller will trigger an
445 * ECC_TRANSACTION_DONE interrupt.
447 irq_status = denali_wait_for_irq(denali, INTR__ECC_TRANSACTION_DONE);
448 if (!(irq_status & INTR__ECC_TRANSACTION_DONE))
454 static void denali_setup_dma64(struct denali_nand_info *denali,
455 dma_addr_t dma_addr, int page, int write)
458 const int page_count = 1;
460 mode = DENALI_MAP10 | DENALI_BANK(denali) | page;
462 /* DMA is a three step process */
465 * 1. setup transfer type, interrupt when complete,
466 * burst len = 64 bytes, the number of pages
468 denali_host_write(denali, mode,
469 0x01002000 | (64 << 16) | (write << 8) | page_count);
471 /* 2. set memory low address */
472 denali_host_write(denali, mode, dma_addr);
474 /* 3. set memory high address */
475 denali_host_write(denali, mode, (uint64_t)dma_addr >> 32);
478 static void denali_setup_dma32(struct denali_nand_info *denali,
479 dma_addr_t dma_addr, int page, int write)
482 const int page_count = 1;
484 mode = DENALI_MAP10 | DENALI_BANK(denali);
486 /* DMA is a four step process */
488 /* 1. setup transfer type and # of pages */
489 denali_host_write(denali, mode | page,
490 0x2000 | (write << 8) | page_count);
492 /* 2. set memory high address bits 23:8 */
493 denali_host_write(denali, mode | ((dma_addr >> 16) << 8), 0x2200);
495 /* 3. set memory low address bits 23:8 */
496 denali_host_write(denali, mode | ((dma_addr & 0xffff) << 8), 0x2300);
498 /* 4. interrupt when complete, burst len = 64 bytes */
499 denali_host_write(denali, mode | 0x14000, 0x2400);
502 static void denali_setup_dma(struct denali_nand_info *denali,
503 dma_addr_t dma_addr, int page, int write)
505 if (denali->caps & DENALI_CAP_DMA_64BIT)
506 denali_setup_dma64(denali, dma_addr, page, write);
508 denali_setup_dma32(denali, dma_addr, page, write);
511 static int denali_pio_read(struct denali_nand_info *denali, void *buf,
512 size_t size, int page, int raw)
514 uint32_t addr = DENALI_BANK(denali) | page;
515 uint32_t *buf32 = (uint32_t *)buf;
516 uint32_t irq_status, ecc_err_mask;
519 if (denali->caps & DENALI_CAP_HW_ECC_FIXUP)
520 ecc_err_mask = INTR__ECC_UNCOR_ERR;
522 ecc_err_mask = INTR__ECC_ERR;
524 denali_reset_irq(denali);
526 iowrite32(DENALI_MAP01 | addr, denali->host + DENALI_HOST_ADDR);
527 for (i = 0; i < size / 4; i++)
528 *buf32++ = ioread32(denali->host + DENALI_HOST_DATA);
530 irq_status = denali_wait_for_irq(denali, INTR__PAGE_XFER_INC);
531 if (!(irq_status & INTR__PAGE_XFER_INC))
534 if (irq_status & INTR__ERASED_PAGE)
535 memset(buf, 0xff, size);
537 return irq_status & ecc_err_mask ? -EBADMSG : 0;
540 static int denali_pio_write(struct denali_nand_info *denali,
541 const void *buf, size_t size, int page, int raw)
543 uint32_t addr = DENALI_BANK(denali) | page;
544 const uint32_t *buf32 = (uint32_t *)buf;
548 denali_reset_irq(denali);
550 iowrite32(DENALI_MAP01 | addr, denali->host + DENALI_HOST_ADDR);
551 for (i = 0; i < size / 4; i++)
552 iowrite32(*buf32++, denali->host + DENALI_HOST_DATA);
554 irq_status = denali_wait_for_irq(denali,
555 INTR__PROGRAM_COMP | INTR__PROGRAM_FAIL);
556 if (!(irq_status & INTR__PROGRAM_COMP))
562 static int denali_pio_xfer(struct denali_nand_info *denali, void *buf,
563 size_t size, int page, int raw, int write)
566 return denali_pio_write(denali, buf, size, page, raw);
568 return denali_pio_read(denali, buf, size, page, raw);
571 static int denali_dma_xfer(struct denali_nand_info *denali, void *buf,
572 size_t size, int page, int raw, int write)
575 uint32_t irq_mask, irq_status, ecc_err_mask;
576 enum dma_data_direction dir = write ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
579 dma_addr = dma_map_single(denali->dev, buf, size, dir);
580 if (dma_mapping_error(denali->dev, dma_addr)) {
581 dev_dbg(denali->dev, "Failed to DMA-map buffer. Trying PIO.\n");
582 return denali_pio_xfer(denali, buf, size, page, raw, write);
587 * INTR__PROGRAM_COMP is never asserted for the DMA transfer.
588 * We can use INTR__DMA_CMD_COMP instead. This flag is asserted
589 * when the page program is completed.
591 irq_mask = INTR__DMA_CMD_COMP | INTR__PROGRAM_FAIL;
593 } else if (denali->caps & DENALI_CAP_HW_ECC_FIXUP) {
594 irq_mask = INTR__DMA_CMD_COMP;
595 ecc_err_mask = INTR__ECC_UNCOR_ERR;
597 irq_mask = INTR__DMA_CMD_COMP;
598 ecc_err_mask = INTR__ECC_ERR;
601 iowrite32(DMA_ENABLE__FLAG, denali->reg + DMA_ENABLE);
603 denali_reset_irq(denali);
604 denali_setup_dma(denali, dma_addr, page, write);
606 irq_status = denali_wait_for_irq(denali, irq_mask);
607 if (!(irq_status & INTR__DMA_CMD_COMP))
609 else if (irq_status & ecc_err_mask)
612 iowrite32(0, denali->reg + DMA_ENABLE);
614 dma_unmap_single(denali->dev, dma_addr, size, dir);
616 if (irq_status & INTR__ERASED_PAGE)
617 memset(buf, 0xff, size);
622 static int denali_data_xfer(struct denali_nand_info *denali, void *buf,
623 size_t size, int page, int raw, int write)
625 iowrite32(raw ? 0 : ECC_ENABLE__FLAG, denali->reg + ECC_ENABLE);
626 iowrite32(raw ? TRANSFER_SPARE_REG__FLAG : 0,
627 denali->reg + TRANSFER_SPARE_REG);
629 if (denali->dma_avail)
630 return denali_dma_xfer(denali, buf, size, page, raw, write);
632 return denali_pio_xfer(denali, buf, size, page, raw, write);
635 static void denali_oob_xfer(struct mtd_info *mtd, struct nand_chip *chip,
638 struct denali_nand_info *denali = mtd_to_denali(mtd);
639 unsigned int start_cmd = write ? NAND_CMD_SEQIN : NAND_CMD_READ0;
640 unsigned int rnd_cmd = write ? NAND_CMD_RNDIN : NAND_CMD_RNDOUT;
641 int writesize = mtd->writesize;
642 int oobsize = mtd->oobsize;
643 uint8_t *bufpoi = chip->oob_poi;
644 int ecc_steps = chip->ecc.steps;
645 int ecc_size = chip->ecc.size;
646 int ecc_bytes = chip->ecc.bytes;
647 int oob_skip = denali->oob_skip_bytes;
648 size_t size = writesize + oobsize;
651 /* BBM at the beginning of the OOB area */
652 chip->cmdfunc(mtd, start_cmd, writesize, page);
654 chip->write_buf(mtd, bufpoi, oob_skip);
656 chip->read_buf(mtd, bufpoi, oob_skip);
660 for (i = 0; i < ecc_steps; i++) {
661 pos = ecc_size + i * (ecc_size + ecc_bytes);
664 if (pos >= writesize)
666 else if (pos + len > writesize)
667 len = writesize - pos;
669 chip->cmdfunc(mtd, rnd_cmd, pos, -1);
671 chip->write_buf(mtd, bufpoi, len);
673 chip->read_buf(mtd, bufpoi, len);
675 if (len < ecc_bytes) {
676 len = ecc_bytes - len;
677 chip->cmdfunc(mtd, rnd_cmd, writesize + oob_skip, -1);
679 chip->write_buf(mtd, bufpoi, len);
681 chip->read_buf(mtd, bufpoi, len);
687 len = oobsize - (bufpoi - chip->oob_poi);
688 chip->cmdfunc(mtd, rnd_cmd, size - len, -1);
690 chip->write_buf(mtd, bufpoi, len);
692 chip->read_buf(mtd, bufpoi, len);
695 static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
696 uint8_t *buf, int oob_required, int page)
698 struct denali_nand_info *denali = mtd_to_denali(mtd);
699 int writesize = mtd->writesize;
700 int oobsize = mtd->oobsize;
701 int ecc_steps = chip->ecc.steps;
702 int ecc_size = chip->ecc.size;
703 int ecc_bytes = chip->ecc.bytes;
704 void *dma_buf = denali->buf;
705 int oob_skip = denali->oob_skip_bytes;
706 size_t size = writesize + oobsize;
707 int ret, i, pos, len;
709 ret = denali_data_xfer(denali, dma_buf, size, page, 1, 0);
713 /* Arrange the buffer for syndrome payload/ecc layout */
715 for (i = 0; i < ecc_steps; i++) {
716 pos = i * (ecc_size + ecc_bytes);
719 if (pos >= writesize)
721 else if (pos + len > writesize)
722 len = writesize - pos;
724 memcpy(buf, dma_buf + pos, len);
726 if (len < ecc_size) {
727 len = ecc_size - len;
728 memcpy(buf, dma_buf + writesize + oob_skip,
736 uint8_t *oob = chip->oob_poi;
738 /* BBM at the beginning of the OOB area */
739 memcpy(oob, dma_buf + writesize, oob_skip);
743 for (i = 0; i < ecc_steps; i++) {
744 pos = ecc_size + i * (ecc_size + ecc_bytes);
747 if (pos >= writesize)
749 else if (pos + len > writesize)
750 len = writesize - pos;
752 memcpy(oob, dma_buf + pos, len);
754 if (len < ecc_bytes) {
755 len = ecc_bytes - len;
756 memcpy(oob, dma_buf + writesize + oob_skip,
763 len = oobsize - (oob - chip->oob_poi);
764 memcpy(oob, dma_buf + size - len, len);
770 static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
773 denali_oob_xfer(mtd, chip, page, 0);
778 static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
781 struct denali_nand_info *denali = mtd_to_denali(mtd);
784 denali_reset_irq(denali);
786 denali_oob_xfer(mtd, chip, page, 1);
788 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
789 status = chip->waitfunc(mtd, chip);
791 return status & NAND_STATUS_FAIL ? -EIO : 0;
794 static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
795 uint8_t *buf, int oob_required, int page)
797 struct denali_nand_info *denali = mtd_to_denali(mtd);
798 unsigned long uncor_ecc_flags = 0;
802 ret = denali_data_xfer(denali, buf, mtd->writesize, page, 0, 0);
803 if (ret && ret != -EBADMSG)
806 if (denali->caps & DENALI_CAP_HW_ECC_FIXUP)
807 stat = denali_hw_ecc_fixup(mtd, denali, &uncor_ecc_flags);
808 else if (ret == -EBADMSG)
809 stat = denali_sw_ecc_fixup(mtd, denali, &uncor_ecc_flags, buf);
814 if (uncor_ecc_flags) {
815 ret = denali_read_oob(mtd, chip, page);
819 stat = denali_check_erased_page(mtd, chip, buf,
820 uncor_ecc_flags, stat);
826 static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
827 const uint8_t *buf, int oob_required, int page)
829 struct denali_nand_info *denali = mtd_to_denali(mtd);
830 int writesize = mtd->writesize;
831 int oobsize = mtd->oobsize;
832 int ecc_steps = chip->ecc.steps;
833 int ecc_size = chip->ecc.size;
834 int ecc_bytes = chip->ecc.bytes;
835 void *dma_buf = denali->buf;
836 int oob_skip = denali->oob_skip_bytes;
837 size_t size = writesize + oobsize;
841 * Fill the buffer with 0xff first except the full page transfer.
842 * This simplifies the logic.
844 if (!buf || !oob_required)
845 memset(dma_buf, 0xff, size);
847 /* Arrange the buffer for syndrome payload/ecc layout */
849 for (i = 0; i < ecc_steps; i++) {
850 pos = i * (ecc_size + ecc_bytes);
853 if (pos >= writesize)
855 else if (pos + len > writesize)
856 len = writesize - pos;
858 memcpy(dma_buf + pos, buf, len);
860 if (len < ecc_size) {
861 len = ecc_size - len;
862 memcpy(dma_buf + writesize + oob_skip, buf,
870 const uint8_t *oob = chip->oob_poi;
872 /* BBM at the beginning of the OOB area */
873 memcpy(dma_buf + writesize, oob, oob_skip);
877 for (i = 0; i < ecc_steps; i++) {
878 pos = ecc_size + i * (ecc_size + ecc_bytes);
881 if (pos >= writesize)
883 else if (pos + len > writesize)
884 len = writesize - pos;
886 memcpy(dma_buf + pos, oob, len);
888 if (len < ecc_bytes) {
889 len = ecc_bytes - len;
890 memcpy(dma_buf + writesize + oob_skip, oob,
897 len = oobsize - (oob - chip->oob_poi);
898 memcpy(dma_buf + size - len, oob, len);
901 return denali_data_xfer(denali, dma_buf, size, page, 1, 1);
904 static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
905 const uint8_t *buf, int oob_required, int page)
907 struct denali_nand_info *denali = mtd_to_denali(mtd);
909 return denali_data_xfer(denali, (void *)buf, mtd->writesize,
913 static void denali_select_chip(struct mtd_info *mtd, int chip)
915 struct denali_nand_info *denali = mtd_to_denali(mtd);
917 denali->active_bank = chip;
920 static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
922 struct denali_nand_info *denali = mtd_to_denali(mtd);
925 /* R/B# pin transitioned from low to high? */
926 irq_status = denali_wait_for_irq(denali, INTR__INT_ACT);
928 return irq_status & INTR__INT_ACT ? 0 : NAND_STATUS_FAIL;
931 static int denali_erase(struct mtd_info *mtd, int page)
933 struct denali_nand_info *denali = mtd_to_denali(mtd);
936 denali_reset_irq(denali);
938 denali_host_write(denali, DENALI_MAP10 | DENALI_BANK(denali) | page,
941 /* wait for erase to complete or failure to occur */
942 irq_status = denali_wait_for_irq(denali,
943 INTR__ERASE_COMP | INTR__ERASE_FAIL);
945 return irq_status & INTR__ERASE_COMP ? 0 : NAND_STATUS_FAIL;
948 static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr,
949 const struct nand_data_interface *conf)
951 struct denali_nand_info *denali = mtd_to_denali(mtd);
952 const struct nand_sdr_timings *timings;
954 int acc_clks, re_2_we, re_2_re, we_2_re, addr_2_data;
955 int rdwr_en_lo, rdwr_en_hi, rdwr_en_lo_hi, cs_setup;
956 int addr_2_data_mask;
959 timings = nand_get_sdr_timings(conf);
961 return PTR_ERR(timings);
963 /* clk_x period in picoseconds */
964 t_clk = DIV_ROUND_DOWN_ULL(1000000000000ULL, denali->clk_x_rate);
968 if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
971 /* tREA -> ACC_CLKS */
972 acc_clks = DIV_ROUND_UP(timings->tREA_max, t_clk);
973 acc_clks = min_t(int, acc_clks, ACC_CLKS__VALUE);
975 tmp = ioread32(denali->reg + ACC_CLKS);
976 tmp &= ~ACC_CLKS__VALUE;
977 tmp |= FIELD_PREP(ACC_CLKS__VALUE, acc_clks);
978 iowrite32(tmp, denali->reg + ACC_CLKS);
980 /* tRWH -> RE_2_WE */
981 re_2_we = DIV_ROUND_UP(timings->tRHW_min, t_clk);
982 re_2_we = min_t(int, re_2_we, RE_2_WE__VALUE);
984 tmp = ioread32(denali->reg + RE_2_WE);
985 tmp &= ~RE_2_WE__VALUE;
986 tmp |= FIELD_PREP(RE_2_WE__VALUE, re_2_we);
987 iowrite32(tmp, denali->reg + RE_2_WE);
989 /* tRHZ -> RE_2_RE */
990 re_2_re = DIV_ROUND_UP(timings->tRHZ_max, t_clk);
991 re_2_re = min_t(int, re_2_re, RE_2_RE__VALUE);
993 tmp = ioread32(denali->reg + RE_2_RE);
994 tmp &= ~RE_2_RE__VALUE;
995 tmp |= FIELD_PREP(RE_2_RE__VALUE, re_2_re);
996 iowrite32(tmp, denali->reg + RE_2_RE);
998 /* tWHR -> WE_2_RE */
999 we_2_re = DIV_ROUND_UP(timings->tWHR_min, t_clk);
1000 we_2_re = min_t(int, we_2_re, TWHR2_AND_WE_2_RE__WE_2_RE);
1002 tmp = ioread32(denali->reg + TWHR2_AND_WE_2_RE);
1003 tmp &= ~TWHR2_AND_WE_2_RE__WE_2_RE;
1004 tmp |= FIELD_PREP(TWHR2_AND_WE_2_RE__WE_2_RE, we_2_re);
1005 iowrite32(tmp, denali->reg + TWHR2_AND_WE_2_RE);
1007 /* tADL -> ADDR_2_DATA */
1009 /* for older versions, ADDR_2_DATA is only 6 bit wide */
1010 addr_2_data_mask = TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA;
1011 if (denali->revision < 0x0501)
1012 addr_2_data_mask >>= 1;
1014 addr_2_data = DIV_ROUND_UP(timings->tADL_min, t_clk);
1015 addr_2_data = min_t(int, addr_2_data, addr_2_data_mask);
1017 tmp = ioread32(denali->reg + TCWAW_AND_ADDR_2_DATA);
1018 tmp &= ~TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA;
1019 tmp |= FIELD_PREP(TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA, addr_2_data);
1020 iowrite32(tmp, denali->reg + TCWAW_AND_ADDR_2_DATA);
1022 /* tREH, tWH -> RDWR_EN_HI_CNT */
1023 rdwr_en_hi = DIV_ROUND_UP(max(timings->tREH_min, timings->tWH_min),
1025 rdwr_en_hi = min_t(int, rdwr_en_hi, RDWR_EN_HI_CNT__VALUE);
1027 tmp = ioread32(denali->reg + RDWR_EN_HI_CNT);
1028 tmp &= ~RDWR_EN_HI_CNT__VALUE;
1029 tmp |= FIELD_PREP(RDWR_EN_HI_CNT__VALUE, rdwr_en_hi);
1030 iowrite32(tmp, denali->reg + RDWR_EN_HI_CNT);
1032 /* tRP, tWP -> RDWR_EN_LO_CNT */
1033 rdwr_en_lo = DIV_ROUND_UP(max(timings->tRP_min, timings->tWP_min),
1035 rdwr_en_lo_hi = DIV_ROUND_UP(max(timings->tRC_min, timings->tWC_min),
1037 rdwr_en_lo_hi = max(rdwr_en_lo_hi, DENALI_CLK_X_MULT);
1038 rdwr_en_lo = max(rdwr_en_lo, rdwr_en_lo_hi - rdwr_en_hi);
1039 rdwr_en_lo = min_t(int, rdwr_en_lo, RDWR_EN_LO_CNT__VALUE);
1041 tmp = ioread32(denali->reg + RDWR_EN_LO_CNT);
1042 tmp &= ~RDWR_EN_LO_CNT__VALUE;
1043 tmp |= FIELD_PREP(RDWR_EN_LO_CNT__VALUE, rdwr_en_lo);
1044 iowrite32(tmp, denali->reg + RDWR_EN_LO_CNT);
1046 /* tCS, tCEA -> CS_SETUP_CNT */
1047 cs_setup = max3((int)DIV_ROUND_UP(timings->tCS_min, t_clk) - rdwr_en_lo,
1048 (int)DIV_ROUND_UP(timings->tCEA_max, t_clk) - acc_clks,
1050 cs_setup = min_t(int, cs_setup, CS_SETUP_CNT__VALUE);
1052 tmp = ioread32(denali->reg + CS_SETUP_CNT);
1053 tmp &= ~CS_SETUP_CNT__VALUE;
1054 tmp |= FIELD_PREP(CS_SETUP_CNT__VALUE, cs_setup);
1055 iowrite32(tmp, denali->reg + CS_SETUP_CNT);
1060 static void denali_reset_banks(struct denali_nand_info *denali)
1065 for (i = 0; i < denali->max_banks; i++) {
1066 denali->active_bank = i;
1068 denali_reset_irq(denali);
1070 iowrite32(DEVICE_RESET__BANK(i),
1071 denali->reg + DEVICE_RESET);
1073 irq_status = denali_wait_for_irq(denali,
1074 INTR__RST_COMP | INTR__INT_ACT | INTR__TIME_OUT);
1075 if (!(irq_status & INTR__INT_ACT))
1079 dev_dbg(denali->dev, "%d chips connected\n", i);
1080 denali->max_banks = i;
1083 static void denali_hw_init(struct denali_nand_info *denali)
1086 * The REVISION register may not be reliable. Platforms are allowed to
1089 if (!denali->revision)
1090 denali->revision = swab16(ioread32(denali->reg + REVISION));
1093 * tell driver how many bit controller will skip before
1094 * writing ECC code in OOB, this register may be already
1095 * set by firmware. So we read this value out.
1096 * if this value is 0, just let it be.
1098 denali->oob_skip_bytes = ioread32(denali->reg + SPARE_AREA_SKIP_BYTES);
1099 denali_detect_max_banks(denali);
1100 iowrite32(0x0F, denali->reg + RB_PIN_ENABLED);
1101 iowrite32(CHIP_EN_DONT_CARE__FLAG, denali->reg + CHIP_ENABLE_DONT_CARE);
1103 iowrite32(0xffff, denali->reg + SPARE_AREA_MARKER);
1105 iowrite32(1, denali->reg + ECC_ENABLE);
1108 int denali_calc_ecc_bytes(int step_size, int strength)
1110 /* BCH code. Denali requires ecc.bytes to be multiple of 2 */
1111 return DIV_ROUND_UP(strength * fls(step_size * 8), 16) * 2;
1113 EXPORT_SYMBOL(denali_calc_ecc_bytes);
1115 static int denali_ecc_setup(struct mtd_info *mtd, struct nand_chip *chip,
1116 struct denali_nand_info *denali)
1118 int oobavail = mtd->oobsize - denali->oob_skip_bytes;
1122 * If .size and .strength are already set (usually by DT),
1123 * check if they are supported by this controller.
1125 if (chip->ecc.size && chip->ecc.strength)
1126 return nand_check_ecc_caps(chip, denali->ecc_caps, oobavail);
1129 * We want .size and .strength closest to the chip's requirement
1130 * unless NAND_ECC_MAXIMIZE is requested.
1132 if (!(chip->ecc.options & NAND_ECC_MAXIMIZE)) {
1133 ret = nand_match_ecc_req(chip, denali->ecc_caps, oobavail);
1138 /* Max ECC strength is the last thing we can do */
1139 return nand_maximize_ecc(chip, denali->ecc_caps, oobavail);
1142 static int denali_ooblayout_ecc(struct mtd_info *mtd, int section,
1143 struct mtd_oob_region *oobregion)
1145 struct denali_nand_info *denali = mtd_to_denali(mtd);
1146 struct nand_chip *chip = mtd_to_nand(mtd);
1151 oobregion->offset = denali->oob_skip_bytes;
1152 oobregion->length = chip->ecc.total;
1157 static int denali_ooblayout_free(struct mtd_info *mtd, int section,
1158 struct mtd_oob_region *oobregion)
1160 struct denali_nand_info *denali = mtd_to_denali(mtd);
1161 struct nand_chip *chip = mtd_to_nand(mtd);
1166 oobregion->offset = chip->ecc.total + denali->oob_skip_bytes;
1167 oobregion->length = mtd->oobsize - oobregion->offset;
1172 static const struct mtd_ooblayout_ops denali_ooblayout_ops = {
1173 .ecc = denali_ooblayout_ecc,
1174 .free = denali_ooblayout_free,
1177 static int denali_multidev_fixup(struct denali_nand_info *denali)
1179 struct nand_chip *chip = &denali->nand;
1180 struct mtd_info *mtd = nand_to_mtd(chip);
1183 * Support for multi device:
1184 * When the IP configuration is x16 capable and two x8 chips are
1185 * connected in parallel, DEVICES_CONNECTED should be set to 2.
1186 * In this case, the core framework knows nothing about this fact,
1187 * so we should tell it the _logical_ pagesize and anything necessary.
1189 denali->devs_per_cs = ioread32(denali->reg + DEVICES_CONNECTED);
1192 * On some SoCs, DEVICES_CONNECTED is not auto-detected.
1193 * For those, DEVICES_CONNECTED is left to 0. Set 1 if it is the case.
1195 if (denali->devs_per_cs == 0) {
1196 denali->devs_per_cs = 1;
1197 iowrite32(1, denali->reg + DEVICES_CONNECTED);
1200 if (denali->devs_per_cs == 1)
1203 if (denali->devs_per_cs != 2) {
1204 dev_err(denali->dev, "unsupported number of devices %d\n",
1205 denali->devs_per_cs);
1209 /* 2 chips in parallel */
1211 mtd->erasesize <<= 1;
1212 mtd->writesize <<= 1;
1214 chip->chipsize <<= 1;
1215 chip->page_shift += 1;
1216 chip->phys_erase_shift += 1;
1217 chip->bbt_erase_shift += 1;
1218 chip->chip_shift += 1;
1219 chip->pagemask <<= 1;
1220 chip->ecc.size <<= 1;
1221 chip->ecc.bytes <<= 1;
1222 chip->ecc.strength <<= 1;
1223 denali->oob_skip_bytes <<= 1;
1228 int denali_init(struct denali_nand_info *denali)
1230 struct nand_chip *chip = &denali->nand;
1231 struct mtd_info *mtd = nand_to_mtd(chip);
1234 mtd->dev.parent = denali->dev;
1235 denali_hw_init(denali);
1237 init_completion(&denali->complete);
1238 spin_lock_init(&denali->irq_lock);
1240 denali_clear_irq_all(denali);
1242 ret = devm_request_irq(denali->dev, denali->irq, denali_isr,
1243 IRQF_SHARED, DENALI_NAND_NAME, denali);
1245 dev_err(denali->dev, "Unable to request IRQ\n");
1249 denali_enable_irq(denali);
1250 denali_reset_banks(denali);
1252 denali->active_bank = DENALI_INVALID_BANK;
1254 nand_set_flash_node(chip, denali->dev->of_node);
1255 /* Fallback to the default name if DT did not give "label" property */
1257 mtd->name = "denali-nand";
1259 chip->select_chip = denali_select_chip;
1260 chip->read_byte = denali_read_byte;
1261 chip->write_byte = denali_write_byte;
1262 chip->read_word = denali_read_word;
1263 chip->cmd_ctrl = denali_cmd_ctrl;
1264 chip->dev_ready = denali_dev_ready;
1265 chip->waitfunc = denali_waitfunc;
1267 /* clk rate info is needed for setup_data_interface */
1268 if (denali->clk_x_rate)
1269 chip->setup_data_interface = denali_setup_data_interface;
1271 ret = nand_scan_ident(mtd, denali->max_banks, NULL);
1275 if (ioread32(denali->reg + FEATURES) & FEATURES__DMA)
1276 denali->dma_avail = 1;
1278 if (denali->dma_avail) {
1279 int dma_bit = denali->caps & DENALI_CAP_DMA_64BIT ? 64 : 32;
1281 ret = dma_set_mask(denali->dev, DMA_BIT_MASK(dma_bit));
1283 dev_info(denali->dev,
1284 "Failed to set DMA mask. Disabling DMA.\n");
1285 denali->dma_avail = 0;
1289 if (denali->dma_avail) {
1290 chip->options |= NAND_USE_BOUNCE_BUFFER;
1291 chip->buf_align = 16;
1294 chip->bbt_options |= NAND_BBT_USE_FLASH;
1295 chip->bbt_options |= NAND_BBT_NO_OOB;
1296 chip->ecc.mode = NAND_ECC_HW_SYNDROME;
1297 chip->options |= NAND_NO_SUBPAGE_WRITE;
1299 ret = denali_ecc_setup(mtd, chip, denali);
1301 dev_err(denali->dev, "Failed to setup ECC settings.\n");
1305 dev_dbg(denali->dev,
1306 "chosen ECC settings: step=%d, strength=%d, bytes=%d\n",
1307 chip->ecc.size, chip->ecc.strength, chip->ecc.bytes);
1309 iowrite32(FIELD_PREP(ECC_CORRECTION__ERASE_THRESHOLD, 1) |
1310 FIELD_PREP(ECC_CORRECTION__VALUE, chip->ecc.strength),
1311 denali->reg + ECC_CORRECTION);
1312 iowrite32(mtd->erasesize / mtd->writesize,
1313 denali->reg + PAGES_PER_BLOCK);
1314 iowrite32(chip->options & NAND_BUSWIDTH_16 ? 1 : 0,
1315 denali->reg + DEVICE_WIDTH);
1316 iowrite32(chip->options & NAND_ROW_ADDR_3 ? 0 : TWO_ROW_ADDR_CYCLES__FLAG,
1317 denali->reg + TWO_ROW_ADDR_CYCLES);
1318 iowrite32(mtd->writesize, denali->reg + DEVICE_MAIN_AREA_SIZE);
1319 iowrite32(mtd->oobsize, denali->reg + DEVICE_SPARE_AREA_SIZE);
1321 iowrite32(chip->ecc.size, denali->reg + CFG_DATA_BLOCK_SIZE);
1322 iowrite32(chip->ecc.size, denali->reg + CFG_LAST_DATA_BLOCK_SIZE);
1323 /* chip->ecc.steps is set by nand_scan_tail(); not available here */
1324 iowrite32(mtd->writesize / chip->ecc.size,
1325 denali->reg + CFG_NUM_DATA_BLOCKS);
1327 mtd_set_ooblayout(mtd, &denali_ooblayout_ops);
1329 if (chip->options & NAND_BUSWIDTH_16) {
1330 chip->read_buf = denali_read_buf16;
1331 chip->write_buf = denali_write_buf16;
1333 chip->read_buf = denali_read_buf;
1334 chip->write_buf = denali_write_buf;
1336 chip->ecc.options |= NAND_ECC_CUSTOM_PAGE_ACCESS;
1337 chip->ecc.read_page = denali_read_page;
1338 chip->ecc.read_page_raw = denali_read_page_raw;
1339 chip->ecc.write_page = denali_write_page;
1340 chip->ecc.write_page_raw = denali_write_page_raw;
1341 chip->ecc.read_oob = denali_read_oob;
1342 chip->ecc.write_oob = denali_write_oob;
1343 chip->erase = denali_erase;
1345 ret = denali_multidev_fixup(denali);
1350 * This buffer is DMA-mapped by denali_{read,write}_page_raw. Do not
1351 * use devm_kmalloc() because the memory allocated by devm_ does not
1352 * guarantee DMA-safe alignment.
1354 denali->buf = kmalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL);
1360 ret = nand_scan_tail(mtd);
1364 ret = mtd_device_register(mtd, NULL, 0);
1366 dev_err(denali->dev, "Failed to register MTD: %d\n", ret);
1374 denali_disable_irq(denali);
1378 EXPORT_SYMBOL(denali_init);
1380 void denali_remove(struct denali_nand_info *denali)
1382 struct mtd_info *mtd = nand_to_mtd(&denali->nand);
1386 denali_disable_irq(denali);
1388 EXPORT_SYMBOL(denali_remove);