2 * NAND driver for TI DaVinci based boards.
4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6 * Based on Linux DaVinci NAND driver by TI. Original copyright follows:
11 * linux/drivers/mtd/nand/nand_davinci.c
15 * Copyright (C) 2006 Texas Instruments.
17 * ----------------------------------------------------------------------------
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License as published by
21 * the Free Software Foundation; either version 2 of the License, or
22 * (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
32 * ----------------------------------------------------------------------------
35 * This is a device driver for the NAND flash device found on the
36 * DaVinci board which utilizes the Samsung k9k2g08 part.
39 ver. 1.0: Feb 2005, Vinod/Sudhakar
47 #include <asm/arch/nand_defs.h>
48 #include <asm/arch/emif_defs.h>
50 extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
52 static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
54 struct nand_chip *this = mtd->priv;
55 u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
57 IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
59 if (ctrl & NAND_CTRL_CHANGE) {
60 if ( ctrl & NAND_CLE )
61 IO_ADDR_W |= MASK_CLE;
62 if ( ctrl & NAND_ALE )
63 IO_ADDR_W |= MASK_ALE;
64 this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
67 if (cmd != NAND_CMD_NONE)
68 writeb(cmd, this->IO_ADDR_W);
71 /* Set WP on deselect, write enable on select */
72 static void nand_davinci_select_chip(struct mtd_info *mtd, int chip)
74 #define GPIO_SET_DATA01 0x01c67018
75 #define GPIO_CLR_DATA01 0x01c6701c
76 #define GPIO_NAND_WP (1 << 4)
77 #ifdef SONATA_BOARD_GPIOWP
79 REG(GPIO_CLR_DATA01) |= GPIO_NAND_WP;
81 REG(GPIO_SET_DATA01) |= GPIO_NAND_WP;
86 #ifdef CONFIG_SYS_NAND_HW_ECC
87 #ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
88 /* Linux-compatible ECC uses MTD defaults. */
89 /* These layouts are not compatible with Linux or RBL/UBL. */
90 #ifdef CONFIG_SYS_NAND_LARGEPAGE
91 static struct nand_ecclayout davinci_nand_ecclayout = {
93 .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
95 {.offset = 2, .length = 6},
96 {.offset = 12, .length = 12},
97 {.offset = 28, .length = 12},
98 {.offset = 44, .length = 12},
99 {.offset = 60, .length = 4}
102 #elif defined(CONFIG_SYS_NAND_SMALLPAGE)
103 static struct nand_ecclayout davinci_nand_ecclayout = {
107 {.offset = 6, .length = 2},
108 {.offset = 8, .length = 8}
112 #error "Either CONFIG_SYS_NAND_LARGEPAGE or CONFIG_SYS_NAND_SMALLPAGE must be defined!"
114 #endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */
116 static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
121 emif_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE;
123 dummy = emif_addr->NANDF1ECC;
124 dummy = emif_addr->NANDF2ECC;
125 dummy = emif_addr->NANDF3ECC;
126 dummy = emif_addr->NANDF4ECC;
128 emif_addr->NANDFCR |= (1 << 8);
131 static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
134 emifregs emif_base_addr;
136 emif_base_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE;
139 ecc = emif_base_addr->NANDF1ECC;
140 else if (region == 2)
141 ecc = emif_base_addr->NANDF2ECC;
142 else if (region == 3)
143 ecc = emif_base_addr->NANDF3ECC;
144 else if (region == 4)
145 ecc = emif_base_addr->NANDF4ECC;
150 static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
153 #ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
155 * This is not how you should read ECCs on large page Davinci devices.
156 * The region parameter gets you ECCs for flash chips on different chip
157 * selects, not the 4x512 byte pages in a 2048 byte page.
159 * Preserved for backwards compatibility though.
163 struct nand_chip *this = mtd->priv;
165 n = (this->ecc.size/512);
169 tmp = nand_davinci_readecc(mtd, region);
171 *ecc_code++ = tmp >> 16;
172 *ecc_code++ = ((tmp >> 8) & 0x0f) | ((tmp >> 20) & 0xf0);
176 const int region = 1;
178 tmp = nand_davinci_readecc(mtd, region);
180 /* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
181 * and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
182 tmp = (tmp & 0x00000fff) | ((tmp & 0x0fff0000) >> 4);
184 /* Invert so that erased block ECC is correct */
188 *ecc_code++ = tmp >> 8;
189 *ecc_code++ = tmp >> 16;
190 #endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */
194 #ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
195 static void nand_davinci_gen_true_ecc(u_int8_t *ecc_buf)
197 u_int32_t tmp = ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xf0) << 20) | ((ecc_buf[2] & 0x0f) << 8);
199 ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) | P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
200 ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) | P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
201 ecc_buf[2] = ~( P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) | P1e(tmp) | P2048o(tmp) | P2048e(tmp));
204 static int nand_davinci_compare_ecc(u_int8_t *ecc_nand, u_int8_t *ecc_calc, u_int8_t *page_data)
207 u_int8_t tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
208 u_int8_t comp0_bit[8], comp1_bit[8], comp2_bit[8];
209 u_int8_t ecc_bit[24];
210 u_int8_t ecc_sum = 0;
211 u_int8_t find_bit = 0;
212 u_int32_t find_byte = 0;
215 is_ecc_ff = ((*ecc_nand == 0xff) && (*(ecc_nand + 1) == 0xff) && (*(ecc_nand + 2) == 0xff));
217 nand_davinci_gen_true_ecc(ecc_nand);
218 nand_davinci_gen_true_ecc(ecc_calc);
220 for (i = 0; i <= 2; i++) {
221 *(ecc_nand + i) = ~(*(ecc_nand + i));
222 *(ecc_calc + i) = ~(*(ecc_calc + i));
225 for (i = 0; i < 8; i++) {
226 tmp0_bit[i] = *ecc_nand % 2;
227 *ecc_nand = *ecc_nand / 2;
230 for (i = 0; i < 8; i++) {
231 tmp1_bit[i] = *(ecc_nand + 1) % 2;
232 *(ecc_nand + 1) = *(ecc_nand + 1) / 2;
235 for (i = 0; i < 8; i++) {
236 tmp2_bit[i] = *(ecc_nand + 2) % 2;
237 *(ecc_nand + 2) = *(ecc_nand + 2) / 2;
240 for (i = 0; i < 8; i++) {
241 comp0_bit[i] = *ecc_calc % 2;
242 *ecc_calc = *ecc_calc / 2;
245 for (i = 0; i < 8; i++) {
246 comp1_bit[i] = *(ecc_calc + 1) % 2;
247 *(ecc_calc + 1) = *(ecc_calc + 1) / 2;
250 for (i = 0; i < 8; i++) {
251 comp2_bit[i] = *(ecc_calc + 2) % 2;
252 *(ecc_calc + 2) = *(ecc_calc + 2) / 2;
255 for (i = 0; i< 6; i++)
256 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
258 for (i = 0; i < 8; i++)
259 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
261 for (i = 0; i < 8; i++)
262 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
264 ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
265 ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
267 for (i = 0; i < 24; i++)
268 ecc_sum += ecc_bit[i];
272 /* Not reached because this function is not called if
273 ECC values are equal */
276 /* Uncorrectable error */
277 MTDDEBUG (MTD_DEBUG_LEVEL0,
278 "ECC UNCORRECTED_ERROR 1\n");
281 /* Correctable error */
282 find_byte = (ecc_bit[23] << 8) +
292 find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
294 MTDDEBUG (MTD_DEBUG_LEVEL0, "Correcting single bit ECC "
295 "error at offset: %d, bit: %d\n",
296 find_byte, find_bit);
298 page_data[find_byte] ^= (1 << find_bit);
303 if (ecc_calc[0] == 0 && ecc_calc[1] == 0 && ecc_calc[2] == 0)
306 MTDDEBUG (MTD_DEBUG_LEVEL0,
307 "UNCORRECTED_ERROR default\n");
311 #endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */
313 static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc)
315 struct nand_chip *this = mtd->priv;
316 #ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
317 int block_count = 0, i, rc;
319 block_count = (this->ecc.size/512);
320 for (i = 0; i < block_count; i++) {
321 if (memcmp(read_ecc, calc_ecc, 3) != 0) {
322 rc = nand_davinci_compare_ecc(read_ecc, calc_ecc, dat);
332 u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) |
334 u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) |
336 u_int32_t diff = ecc_calc ^ ecc_nand;
339 if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
340 /* Correctable error */
341 if ((diff >> (12 + 3)) < this->ecc.size) {
342 uint8_t find_bit = 1 << ((diff >> 12) & 7);
343 uint32_t find_byte = diff >> (12 + 3);
345 dat[find_byte] ^= find_bit;
346 MTDDEBUG(MTD_DEBUG_LEVEL0, "Correcting single "
347 "bit ECC error at offset: %d, bit: "
348 "%d\n", find_byte, find_bit);
353 } else if (!(diff & (diff - 1))) {
354 /* Single bit ECC error in the ECC itself,
356 MTDDEBUG(MTD_DEBUG_LEVEL0, "Single bit ECC error in "
360 /* Uncorrectable error */
361 MTDDEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
365 #endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */
368 #endif /* CONFIG_SYS_NAND_HW_ECC */
370 static int nand_davinci_dev_ready(struct mtd_info *mtd)
374 emif_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE;
376 return(emif_addr->NANDFSR & 0x1);
379 static int nand_davinci_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
381 while(!nand_davinci_dev_ready(mtd)) {;}
382 *NAND_CE0CLE = NAND_STATUS;
383 return(*NAND_CE0DATA);
386 static void nand_flash_init(void)
388 u_int32_t acfg1 = 0x3ffffffc;
391 /*------------------------------------------------------------------*
392 * NAND FLASH CHIP TIMEOUT @ 459 MHz *
394 * AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz *
395 * AEMIF.CLK period = 1/76.5 MHz = 13.1 ns *
397 *------------------------------------------------------------------*/
399 | (0 << 31 ) /* selectStrobe */
400 | (0 << 30 ) /* extWait */
401 | (1 << 26 ) /* writeSetup 10 ns */
402 | (3 << 20 ) /* writeStrobe 40 ns */
403 | (1 << 17 ) /* writeHold 10 ns */
404 | (1 << 13 ) /* readSetup 10 ns */
405 | (5 << 7 ) /* readStrobe 60 ns */
406 | (1 << 4 ) /* readHold 10 ns */
407 | (3 << 2 ) /* turnAround ?? ns */
408 | (0 << 0 ) /* asyncSize 8-bit bus */
411 emif_regs = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE;
413 emif_regs->AB1CR = acfg1; /* CS2 */
415 emif_regs->NANDFCR = 0x00000101; /* NAND flash on CS2 */
418 int board_nand_init(struct nand_chip *nand)
420 nand->IO_ADDR_R = (void __iomem *)NAND_CE0DATA;
421 nand->IO_ADDR_W = (void __iomem *)NAND_CE0DATA;
422 nand->chip_delay = 0;
423 nand->select_chip = nand_davinci_select_chip;
424 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
425 nand->options = NAND_USE_FLASH_BBT;
427 #ifdef CONFIG_SYS_NAND_HW_ECC
428 nand->ecc.mode = NAND_ECC_HW;
429 #ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
430 nand->ecc.layout = &davinci_nand_ecclayout;
431 #ifdef CONFIG_SYS_NAND_LARGEPAGE
432 nand->ecc.size = 2048;
433 nand->ecc.bytes = 12;
434 #elif defined(CONFIG_SYS_NAND_SMALLPAGE)
435 nand->ecc.size = 512;
438 #error "Either CONFIG_SYS_NAND_LARGEPAGE or CONFIG_SYS_NAND_SMALLPAGE must be defined!"
441 nand->ecc.size = 512;
443 #endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */
444 nand->ecc.calculate = nand_davinci_calculate_ecc;
445 nand->ecc.correct = nand_davinci_correct_data;
446 nand->ecc.hwctl = nand_davinci_enable_hwecc;
448 nand->ecc.mode = NAND_ECC_SOFT;
449 #endif /* CONFIG_SYS_NAND_HW_ECC */
451 /* Set address of hardware control function */
452 nand->cmd_ctrl = nand_davinci_hwcontrol;
454 nand->dev_ready = nand_davinci_dev_ready;
455 nand->waitfunc = nand_davinci_waitfunc;