2 * NAND driver for TI DaVinci based boards.
4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6 * Based on Linux DaVinci NAND driver by TI. Original copyright follows:
11 * linux/drivers/mtd/nand/nand_davinci.c
15 * Copyright (C) 2006 Texas Instruments.
17 * ----------------------------------------------------------------------------
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License as published by
21 * the Free Software Foundation; either version 2 of the License, or
22 * (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
32 * ----------------------------------------------------------------------------
35 * This is a device driver for the NAND flash device found on the
36 * DaVinci board which utilizes the Samsung k9k2g08 part.
39 ver. 1.0: Feb 2005, Vinod/Sudhakar
47 #include <asm/arch/nand_defs.h>
48 #include <asm/arch/emif_defs.h>
50 /* Definitions for 4-bit hardware ECC */
51 #define NAND_TIMEOUT 10240
52 #define NAND_ECC_BUSY 0xC
53 #define NAND_4BITECC_MASK 0x03FF03FF
54 #define EMIF_NANDFSR_ECC_STATE_MASK 0x00000F00
55 #define ECC_STATE_NO_ERR 0x0
56 #define ECC_STATE_TOO_MANY_ERRS 0x1
57 #define ECC_STATE_ERR_CORR_COMP_P 0x2
58 #define ECC_STATE_ERR_CORR_COMP_N 0x3
60 static emif_registers *const emif_regs = (void *) DAVINCI_ASYNC_EMIF_CNTRL_BASE;
62 static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
64 struct nand_chip *this = mtd->priv;
65 u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
67 IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
69 if (ctrl & NAND_CTRL_CHANGE) {
70 if ( ctrl & NAND_CLE )
71 IO_ADDR_W |= MASK_CLE;
72 if ( ctrl & NAND_ALE )
73 IO_ADDR_W |= MASK_ALE;
74 this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
77 if (cmd != NAND_CMD_NONE)
78 writeb(cmd, this->IO_ADDR_W);
81 #ifdef CONFIG_SYS_NAND_HW_ECC
83 static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
87 dummy = emif_regs->NANDF1ECC;
89 /* FIXME: only chipselect 0 is supported for now */
90 emif_regs->NANDFCR |= 1 << 8;
93 static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
98 ecc = emif_regs->NANDF1ECC;
100 ecc = emif_regs->NANDF2ECC;
101 else if (region == 3)
102 ecc = emif_regs->NANDF3ECC;
103 else if (region == 4)
104 ecc = emif_regs->NANDF4ECC;
109 static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
112 const int region = 1;
114 tmp = nand_davinci_readecc(mtd, region);
116 /* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
117 * and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
118 tmp = (tmp & 0x00000fff) | ((tmp & 0x0fff0000) >> 4);
120 /* Invert so that erased block ECC is correct */
124 *ecc_code++ = tmp >> 8;
125 *ecc_code++ = tmp >> 16;
127 /* NOTE: the above code matches mainline Linux:
128 * .PQR.stu ==> ~PQRstu
130 * MontaVista/TI kernels encode those bytes differently, use
131 * complicated (and allegedly sometimes-wrong) correction code,
132 * and usually shipped with U-Boot that uses software ECC:
133 * .PQR.stu ==> PsQRtu
135 * If you need MV/TI compatible NAND I/O in U-Boot, it should
136 * be possible to (a) change the mangling above, (b) reverse
137 * that mangling in nand_davinci_correct_data() below.
143 static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc)
145 struct nand_chip *this = mtd->priv;
146 u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) |
148 u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) |
150 u_int32_t diff = ecc_calc ^ ecc_nand;
153 if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
154 /* Correctable error */
155 if ((diff >> (12 + 3)) < this->ecc.size) {
156 uint8_t find_bit = 1 << ((diff >> 12) & 7);
157 uint32_t find_byte = diff >> (12 + 3);
159 dat[find_byte] ^= find_bit;
160 MTDDEBUG(MTD_DEBUG_LEVEL0, "Correcting single "
161 "bit ECC error at offset: %d, bit: "
162 "%d\n", find_byte, find_bit);
167 } else if (!(diff & (diff - 1))) {
168 /* Single bit ECC error in the ECC itself,
170 MTDDEBUG(MTD_DEBUG_LEVEL0, "Single bit ECC error in "
174 /* Uncorrectable error */
175 MTDDEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
181 #endif /* CONFIG_SYS_NAND_HW_ECC */
183 #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
184 static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = {
186 * TI uses a different layout for 4K page deviecs. Since the
187 * eccpos filed can hold only a limited number of entries, adding
188 * support for 4K page will result in compilation warnings
189 * 4K Support will be added later
191 #ifdef CONFIG_SYS_NAND_PAGE_2K
195 29, 30, 31, 32, 33, 34, 35, 36, 37, 38,
196 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
197 49, 50, 51, 52, 53, 54, 55, 56, 57, 58,
201 {.offset = 2, .length = 22, },
206 static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
214 * Start a new ECC calculation for reading or writing 512 bytes
217 val = (emif_regs->NANDFCR & ~(3 << 4)) | (1 << 12);
218 emif_regs->NANDFCR = val;
220 case NAND_ECC_READSYN:
221 val = emif_regs->NAND4BITECC1;
228 static u32 nand_davinci_4bit_readecc(struct mtd_info *mtd, unsigned int ecc[4])
230 ecc[0] = emif_regs->NAND4BITECC1 & NAND_4BITECC_MASK;
231 ecc[1] = emif_regs->NAND4BITECC2 & NAND_4BITECC_MASK;
232 ecc[2] = emif_regs->NAND4BITECC3 & NAND_4BITECC_MASK;
233 ecc[3] = emif_regs->NAND4BITECC4 & NAND_4BITECC_MASK;
238 static int nand_davinci_4bit_calculate_ecc(struct mtd_info *mtd,
242 unsigned int hw_4ecc[4] = { 0, 0, 0, 0 };
243 unsigned int const1 = 0, const2 = 0;
244 unsigned char count1 = 0;
246 nand_davinci_4bit_readecc(mtd, hw_4ecc);
248 /*Convert 10 bit ecc value to 8 bit */
249 for (count1 = 0; count1 < 2; count1++) {
253 /* Take first 8 bits from val1 (count1=0) or val5 (count1=1) */
254 ecc_code[const2] = hw_4ecc[const1] & 0xFF;
257 * Take 2 bits as LSB bits from val1 (count1=0) or val5
258 * (count1=1) and 6 bits from val2 (count1=0) or
261 ecc_code[const2 + 1] =
262 ((hw_4ecc[const1] >> 8) & 0x3) | ((hw_4ecc[const1] >> 14) &
266 * Take 4 bits from val2 (count1=0) or val5 (count1=1) and
267 * 4 bits from val3 (count1=0) or val6 (count1=1)
269 ecc_code[const2 + 2] =
270 ((hw_4ecc[const1] >> 22) & 0xF) |
271 ((hw_4ecc[const1 + 1] << 4) & 0xF0);
274 * Take 6 bits from val3(count1=0) or val6 (count1=1) and
275 * 2 bits from val4 (count1=0) or val7 (count1=1)
277 ecc_code[const2 + 3] =
278 ((hw_4ecc[const1 + 1] >> 4) & 0x3F) |
279 ((hw_4ecc[const1 + 1] >> 10) & 0xC0);
281 /* Take 8 bits from val4 (count1=0) or val7 (count1=1) */
282 ecc_code[const2 + 4] = (hw_4ecc[const1 + 1] >> 18) & 0xFF;
288 static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
289 uint8_t *read_ecc, uint8_t *calc_ecc)
291 unsigned short ecc_10bit[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
293 unsigned int hw_4ecc[4] = { 0, 0, 0, 0 }, iserror = 0;
294 unsigned short *pspare = NULL, *pspare1 = NULL;
295 unsigned int numerrors, erroraddress, errorvalue;
299 * Check for an ECC where all bytes are 0xFF. If this is the case, we
300 * will assume we are looking at an erased page and we should ignore
303 for (i = 0; i < 10; i++) {
304 if (read_ecc[i] != 0xFF)
310 /* Convert 8 bit in to 10 bit */
311 pspare = (unsigned short *)&read_ecc[2];
312 pspare1 = (unsigned short *)&read_ecc[0];
314 /* Take 10 bits from 0th and 1st bytes */
315 ecc_10bit[0] = (*pspare1) & 0x3FF;
317 /* Take 6 bits from 1st byte and 4 bits from 2nd byte */
318 ecc_10bit[1] = (((*pspare1) >> 10) & 0x3F)
319 | (((pspare[0]) << 6) & 0x3C0);
321 /* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */
322 ecc_10bit[2] = ((pspare[0]) >> 4) & 0x3FF;
324 /*Take 2 bits from 3rd byte and 8 bits from 4th byte */
325 ecc_10bit[3] = (((pspare[0]) >> 14) & 0x3)
326 | ((((pspare[1])) << 2) & 0x3FC);
328 /* Take 8 bits from 5th byte and 2 bits from 6th byte */
329 ecc_10bit[4] = ((pspare[1]) >> 8)
330 | ((((pspare[2])) << 8) & 0x300);
332 /* Take 6 bits from 6th byte and 4 bits from 7th byte */
333 ecc_10bit[5] = (pspare[2] >> 2) & 0x3FF;
335 /* Take 4 bits from 7th byte and 6 bits from 8th byte */
336 ecc_10bit[6] = (((pspare[2]) >> 12) & 0xF)
337 | ((((pspare[3])) << 4) & 0x3F0);
339 /*Take 2 bits from 8th byte and 8 bits from 9th byte */
340 ecc_10bit[7] = ((pspare[3]) >> 6) & 0x3FF;
343 * Write the parity values in the NAND Flash 4-bit ECC Load register.
344 * Write each parity value one at a time starting from 4bit_ecc_val8
347 for (i = 7; i >= 0; i--)
348 emif_regs->NAND4BITECCLOAD = ecc_10bit[i];
351 * Perform a dummy read to the EMIF Revision Code and Status register.
352 * This is required to ensure time for syndrome calculation after
353 * writing the ECC values in previous step.
356 val = emif_regs->NANDFSR;
359 * Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers.
360 * A syndrome value of 0 means no bit errors. If the syndrome is
361 * non-zero then go further otherwise return.
363 nand_davinci_4bit_readecc(mtd, hw_4ecc);
365 if (hw_4ecc[0] == ECC_STATE_NO_ERR && hw_4ecc[1] == ECC_STATE_NO_ERR &&
366 hw_4ecc[2] == ECC_STATE_NO_ERR && hw_4ecc[3] == ECC_STATE_NO_ERR)
370 * Clear any previous address calculation by doing a dummy read of an
371 * error address register.
373 val = emif_regs->NANDERRADD1;
376 * Set the addr_calc_st bit(bit no 13) in the NAND Flash Control
379 emif_regs->NANDFCR |= 1 << 13;
382 * Wait for the corr_state field (bits 8 to 11)in the
383 * NAND Flash Status register to be equal to 0x0, 0x1, 0x2, or 0x3.
387 val = emif_regs->NANDFSR;
390 } while ((i > 0) && val);
392 iserror = emif_regs->NANDFSR;
393 iserror &= EMIF_NANDFSR_ECC_STATE_MASK;
394 iserror = iserror >> 8;
397 * ECC_STATE_TOO_MANY_ERRS (0x1) means errors cannot be
398 * corrected (five or more errors). The number of errors
399 * calculated (err_num field) differs from the number of errors
400 * searched. ECC_STATE_ERR_CORR_COMP_P (0x2) means error
401 * correction complete (errors on bit 8 or 9).
402 * ECC_STATE_ERR_CORR_COMP_N (0x3) means error correction
403 * complete (error exists).
406 if (iserror == ECC_STATE_NO_ERR) {
407 val = emif_regs->NANDERRVAL1;
409 } else if (iserror == ECC_STATE_TOO_MANY_ERRS) {
410 val = emif_regs->NANDERRVAL1;
414 numerrors = ((emif_regs->NANDFSR >> 16) & 0x3) + 1;
416 /* Read the error address, error value and correct */
417 for (i = 0; i < numerrors; i++) {
420 ((emif_regs->NANDERRADD2 >>
421 (16 * (i & 1))) & 0x3FF);
422 erroraddress = ((512 + 7) - erroraddress);
424 ((emif_regs->NANDERRVAL2 >>
425 (16 * (i & 1))) & 0xFF);
428 ((emif_regs->NANDERRADD1 >>
429 (16 * (i & 1))) & 0x3FF);
430 erroraddress = ((512 + 7) - erroraddress);
432 ((emif_regs->NANDERRVAL1 >>
433 (16 * (i & 1))) & 0xFF);
435 /* xor the corrupt data with error value */
436 if (erroraddress < 512)
437 dat[erroraddress] ^= errorvalue;
442 #endif /* CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST */
444 static int nand_davinci_dev_ready(struct mtd_info *mtd)
446 return emif_regs->NANDFSR & 0x1;
449 static void nand_flash_init(void)
451 /* This is for DM6446 EVM and *very* similar. DO NOT GROW THIS!
452 * Instead, have your board_init() set EMIF timings, based on its
453 * knowledge of the clocks and what devices are hooked up ... and
454 * don't even do that unless no UBL handled it.
456 #ifdef CONFIG_SOC_DM644X
457 u_int32_t acfg1 = 0x3ffffffc;
459 /*------------------------------------------------------------------*
460 * NAND FLASH CHIP TIMEOUT @ 459 MHz *
462 * AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz *
463 * AEMIF.CLK period = 1/76.5 MHz = 13.1 ns *
465 *------------------------------------------------------------------*/
467 | (0 << 31 ) /* selectStrobe */
468 | (0 << 30 ) /* extWait */
469 | (1 << 26 ) /* writeSetup 10 ns */
470 | (3 << 20 ) /* writeStrobe 40 ns */
471 | (1 << 17 ) /* writeHold 10 ns */
472 | (1 << 13 ) /* readSetup 10 ns */
473 | (5 << 7 ) /* readStrobe 60 ns */
474 | (1 << 4 ) /* readHold 10 ns */
475 | (3 << 2 ) /* turnAround ?? ns */
476 | (0 << 0 ) /* asyncSize 8-bit bus */
479 emif_regs->AB1CR = acfg1; /* CS2 */
481 emif_regs->NANDFCR = 0x00000101; /* NAND flash on CS2 */
485 void davinci_nand_init(struct nand_chip *nand)
487 nand->chip_delay = 0;
488 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
489 nand->options |= NAND_USE_FLASH_BBT;
491 #ifdef CONFIG_SYS_NAND_HW_ECC
492 nand->ecc.mode = NAND_ECC_HW;
493 nand->ecc.size = 512;
495 nand->ecc.calculate = nand_davinci_calculate_ecc;
496 nand->ecc.correct = nand_davinci_correct_data;
497 nand->ecc.hwctl = nand_davinci_enable_hwecc;
499 nand->ecc.mode = NAND_ECC_SOFT;
500 #endif /* CONFIG_SYS_NAND_HW_ECC */
501 #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
502 nand->ecc.mode = NAND_ECC_HW_OOB_FIRST;
503 nand->ecc.size = 512;
504 nand->ecc.bytes = 10;
505 nand->ecc.calculate = nand_davinci_4bit_calculate_ecc;
506 nand->ecc.correct = nand_davinci_4bit_correct_data;
507 nand->ecc.hwctl = nand_davinci_4bit_enable_hwecc;
508 nand->ecc.layout = &nand_davinci_4bit_layout_oobfirst;
510 /* Set address of hardware control function */
511 nand->cmd_ctrl = nand_davinci_hwcontrol;
513 nand->dev_ready = nand_davinci_dev_ready;
518 int board_nand_init(struct nand_chip *chip) __attribute__((weak));
520 int board_nand_init(struct nand_chip *chip)
522 davinci_nand_init(chip);