2 * NAND driver for TI DaVinci based boards.
4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6 * Based on Linux DaVinci NAND driver by TI. Original copyright follows:
11 * linux/drivers/mtd/nand/nand_davinci.c
15 * Copyright (C) 2006 Texas Instruments.
17 * ----------------------------------------------------------------------------
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License as published by
21 * the Free Software Foundation; either version 2 of the License, or
22 * (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
32 * ----------------------------------------------------------------------------
35 * This is a device driver for the NAND flash device found on the
36 * DaVinci board which utilizes the Samsung k9k2g08 part.
39 ver. 1.0: Feb 2005, Vinod/Sudhakar
47 #include <asm/arch/nand_defs.h>
48 #include <asm/arch/emif_defs.h>
50 /* Definitions for 4-bit hardware ECC */
51 #define NAND_TIMEOUT 10240
52 #define NAND_ECC_BUSY 0xC
53 #define NAND_4BITECC_MASK 0x03FF03FF
54 #define EMIF_NANDFSR_ECC_STATE_MASK 0x00000F00
55 #define ECC_STATE_NO_ERR 0x0
56 #define ECC_STATE_TOO_MANY_ERRS 0x1
57 #define ECC_STATE_ERR_CORR_COMP_P 0x2
58 #define ECC_STATE_ERR_CORR_COMP_N 0x3
60 static emif_registers *const emif_regs = (void *) DAVINCI_ASYNC_EMIF_CNTRL_BASE;
62 static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
64 struct nand_chip *this = mtd->priv;
65 u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
67 IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
69 if (ctrl & NAND_CTRL_CHANGE) {
70 if ( ctrl & NAND_CLE )
71 IO_ADDR_W |= MASK_CLE;
72 if ( ctrl & NAND_ALE )
73 IO_ADDR_W |= MASK_ALE;
74 this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
77 if (cmd != NAND_CMD_NONE)
78 writeb(cmd, this->IO_ADDR_W);
81 #ifdef CONFIG_SYS_NAND_HW_ECC
83 static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
87 dummy = emif_regs->NANDF1ECC;
89 /* FIXME: only chipselect 0 is supported for now */
90 emif_regs->NANDFCR |= 1 << 8;
93 static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
98 ecc = emif_regs->NANDF1ECC;
100 ecc = emif_regs->NANDF2ECC;
101 else if (region == 3)
102 ecc = emif_regs->NANDF3ECC;
103 else if (region == 4)
104 ecc = emif_regs->NANDF4ECC;
109 static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
112 const int region = 1;
114 tmp = nand_davinci_readecc(mtd, region);
116 /* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
117 * and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
118 tmp = (tmp & 0x00000fff) | ((tmp & 0x0fff0000) >> 4);
120 /* Invert so that erased block ECC is correct */
124 *ecc_code++ = tmp >> 8;
125 *ecc_code++ = tmp >> 16;
127 /* NOTE: the above code matches mainline Linux:
128 * .PQR.stu ==> ~PQRstu
130 * MontaVista/TI kernels encode those bytes differently, use
131 * complicated (and allegedly sometimes-wrong) correction code,
132 * and usually shipped with U-Boot that uses software ECC:
133 * .PQR.stu ==> PsQRtu
135 * If you need MV/TI compatible NAND I/O in U-Boot, it should
136 * be possible to (a) change the mangling above, (b) reverse
137 * that mangling in nand_davinci_correct_data() below.
143 static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc)
145 struct nand_chip *this = mtd->priv;
146 u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) |
148 u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) |
150 u_int32_t diff = ecc_calc ^ ecc_nand;
153 if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
154 /* Correctable error */
155 if ((diff >> (12 + 3)) < this->ecc.size) {
156 uint8_t find_bit = 1 << ((diff >> 12) & 7);
157 uint32_t find_byte = diff >> (12 + 3);
159 dat[find_byte] ^= find_bit;
160 MTDDEBUG(MTD_DEBUG_LEVEL0, "Correcting single "
161 "bit ECC error at offset: %d, bit: "
162 "%d\n", find_byte, find_bit);
167 } else if (!(diff & (diff - 1))) {
168 /* Single bit ECC error in the ECC itself,
170 MTDDEBUG(MTD_DEBUG_LEVEL0, "Single bit ECC error in "
174 /* Uncorrectable error */
175 MTDDEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
181 #endif /* CONFIG_SYS_NAND_HW_ECC */
183 #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
184 static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = {
185 #if defined(CONFIG_SYS_NAND_PAGE_2K)
189 29, 30, 31, 32, 33, 34, 35, 36, 37, 38,
190 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
191 49, 50, 51, 52, 53, 54, 55, 56, 57, 58,
195 {.offset = 2, .length = 22, },
197 #elif defined(CONFIG_SYS_NAND_PAGE_4K)
200 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
201 58, 59, 60, 61, 62, 63, 64, 65, 66, 67,
202 68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
203 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,
204 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,
205 98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
206 108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
207 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
210 {.offset = 2, .length = 46, },
215 static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
223 * Start a new ECC calculation for reading or writing 512 bytes
226 val = (emif_regs->NANDFCR & ~(3 << 4)) | (1 << 12);
227 emif_regs->NANDFCR = val;
229 case NAND_ECC_READSYN:
230 val = emif_regs->NAND4BITECC1;
237 static u32 nand_davinci_4bit_readecc(struct mtd_info *mtd, unsigned int ecc[4])
239 ecc[0] = emif_regs->NAND4BITECC1 & NAND_4BITECC_MASK;
240 ecc[1] = emif_regs->NAND4BITECC2 & NAND_4BITECC_MASK;
241 ecc[2] = emif_regs->NAND4BITECC3 & NAND_4BITECC_MASK;
242 ecc[3] = emif_regs->NAND4BITECC4 & NAND_4BITECC_MASK;
247 static int nand_davinci_4bit_calculate_ecc(struct mtd_info *mtd,
251 unsigned int hw_4ecc[4] = { 0, 0, 0, 0 };
252 unsigned int const1 = 0, const2 = 0;
253 unsigned char count1 = 0;
255 nand_davinci_4bit_readecc(mtd, hw_4ecc);
257 /*Convert 10 bit ecc value to 8 bit */
258 for (count1 = 0; count1 < 2; count1++) {
262 /* Take first 8 bits from val1 (count1=0) or val5 (count1=1) */
263 ecc_code[const2] = hw_4ecc[const1] & 0xFF;
266 * Take 2 bits as LSB bits from val1 (count1=0) or val5
267 * (count1=1) and 6 bits from val2 (count1=0) or
270 ecc_code[const2 + 1] =
271 ((hw_4ecc[const1] >> 8) & 0x3) | ((hw_4ecc[const1] >> 14) &
275 * Take 4 bits from val2 (count1=0) or val5 (count1=1) and
276 * 4 bits from val3 (count1=0) or val6 (count1=1)
278 ecc_code[const2 + 2] =
279 ((hw_4ecc[const1] >> 22) & 0xF) |
280 ((hw_4ecc[const1 + 1] << 4) & 0xF0);
283 * Take 6 bits from val3(count1=0) or val6 (count1=1) and
284 * 2 bits from val4 (count1=0) or val7 (count1=1)
286 ecc_code[const2 + 3] =
287 ((hw_4ecc[const1 + 1] >> 4) & 0x3F) |
288 ((hw_4ecc[const1 + 1] >> 10) & 0xC0);
290 /* Take 8 bits from val4 (count1=0) or val7 (count1=1) */
291 ecc_code[const2 + 4] = (hw_4ecc[const1 + 1] >> 18) & 0xFF;
297 static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
298 uint8_t *read_ecc, uint8_t *calc_ecc)
300 unsigned short ecc_10bit[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
302 unsigned int hw_4ecc[4] = { 0, 0, 0, 0 }, iserror = 0;
303 unsigned short *pspare = NULL, *pspare1 = NULL;
304 unsigned int numerrors, erroraddress, errorvalue;
308 * Check for an ECC where all bytes are 0xFF. If this is the case, we
309 * will assume we are looking at an erased page and we should ignore
312 for (i = 0; i < 10; i++) {
313 if (read_ecc[i] != 0xFF)
319 /* Convert 8 bit in to 10 bit */
320 pspare = (unsigned short *)&read_ecc[2];
321 pspare1 = (unsigned short *)&read_ecc[0];
323 /* Take 10 bits from 0th and 1st bytes */
324 ecc_10bit[0] = (*pspare1) & 0x3FF;
326 /* Take 6 bits from 1st byte and 4 bits from 2nd byte */
327 ecc_10bit[1] = (((*pspare1) >> 10) & 0x3F)
328 | (((pspare[0]) << 6) & 0x3C0);
330 /* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */
331 ecc_10bit[2] = ((pspare[0]) >> 4) & 0x3FF;
333 /*Take 2 bits from 3rd byte and 8 bits from 4th byte */
334 ecc_10bit[3] = (((pspare[0]) >> 14) & 0x3)
335 | ((((pspare[1])) << 2) & 0x3FC);
337 /* Take 8 bits from 5th byte and 2 bits from 6th byte */
338 ecc_10bit[4] = ((pspare[1]) >> 8)
339 | ((((pspare[2])) << 8) & 0x300);
341 /* Take 6 bits from 6th byte and 4 bits from 7th byte */
342 ecc_10bit[5] = (pspare[2] >> 2) & 0x3FF;
344 /* Take 4 bits from 7th byte and 6 bits from 8th byte */
345 ecc_10bit[6] = (((pspare[2]) >> 12) & 0xF)
346 | ((((pspare[3])) << 4) & 0x3F0);
348 /*Take 2 bits from 8th byte and 8 bits from 9th byte */
349 ecc_10bit[7] = ((pspare[3]) >> 6) & 0x3FF;
352 * Write the parity values in the NAND Flash 4-bit ECC Load register.
353 * Write each parity value one at a time starting from 4bit_ecc_val8
356 for (i = 7; i >= 0; i--)
357 emif_regs->NAND4BITECCLOAD = ecc_10bit[i];
360 * Perform a dummy read to the EMIF Revision Code and Status register.
361 * This is required to ensure time for syndrome calculation after
362 * writing the ECC values in previous step.
365 val = emif_regs->NANDFSR;
368 * Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers.
369 * A syndrome value of 0 means no bit errors. If the syndrome is
370 * non-zero then go further otherwise return.
372 nand_davinci_4bit_readecc(mtd, hw_4ecc);
374 if (hw_4ecc[0] == ECC_STATE_NO_ERR && hw_4ecc[1] == ECC_STATE_NO_ERR &&
375 hw_4ecc[2] == ECC_STATE_NO_ERR && hw_4ecc[3] == ECC_STATE_NO_ERR)
379 * Clear any previous address calculation by doing a dummy read of an
380 * error address register.
382 val = emif_regs->NANDERRADD1;
385 * Set the addr_calc_st bit(bit no 13) in the NAND Flash Control
388 emif_regs->NANDFCR |= 1 << 13;
391 * Wait for the corr_state field (bits 8 to 11)in the
392 * NAND Flash Status register to be equal to 0x0, 0x1, 0x2, or 0x3.
396 val = emif_regs->NANDFSR;
399 } while ((i > 0) && val);
401 iserror = emif_regs->NANDFSR;
402 iserror &= EMIF_NANDFSR_ECC_STATE_MASK;
403 iserror = iserror >> 8;
406 * ECC_STATE_TOO_MANY_ERRS (0x1) means errors cannot be
407 * corrected (five or more errors). The number of errors
408 * calculated (err_num field) differs from the number of errors
409 * searched. ECC_STATE_ERR_CORR_COMP_P (0x2) means error
410 * correction complete (errors on bit 8 or 9).
411 * ECC_STATE_ERR_CORR_COMP_N (0x3) means error correction
412 * complete (error exists).
415 if (iserror == ECC_STATE_NO_ERR) {
416 val = emif_regs->NANDERRVAL1;
418 } else if (iserror == ECC_STATE_TOO_MANY_ERRS) {
419 val = emif_regs->NANDERRVAL1;
423 numerrors = ((emif_regs->NANDFSR >> 16) & 0x3) + 1;
425 /* Read the error address, error value and correct */
426 for (i = 0; i < numerrors; i++) {
429 ((emif_regs->NANDERRADD2 >>
430 (16 * (i & 1))) & 0x3FF);
431 erroraddress = ((512 + 7) - erroraddress);
433 ((emif_regs->NANDERRVAL2 >>
434 (16 * (i & 1))) & 0xFF);
437 ((emif_regs->NANDERRADD1 >>
438 (16 * (i & 1))) & 0x3FF);
439 erroraddress = ((512 + 7) - erroraddress);
441 ((emif_regs->NANDERRVAL1 >>
442 (16 * (i & 1))) & 0xFF);
444 /* xor the corrupt data with error value */
445 if (erroraddress < 512)
446 dat[erroraddress] ^= errorvalue;
451 #endif /* CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST */
453 static int nand_davinci_dev_ready(struct mtd_info *mtd)
455 return emif_regs->NANDFSR & 0x1;
458 static void nand_flash_init(void)
460 /* This is for DM6446 EVM and *very* similar. DO NOT GROW THIS!
461 * Instead, have your board_init() set EMIF timings, based on its
462 * knowledge of the clocks and what devices are hooked up ... and
463 * don't even do that unless no UBL handled it.
465 #ifdef CONFIG_SOC_DM644X
466 u_int32_t acfg1 = 0x3ffffffc;
468 /*------------------------------------------------------------------*
469 * NAND FLASH CHIP TIMEOUT @ 459 MHz *
471 * AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz *
472 * AEMIF.CLK period = 1/76.5 MHz = 13.1 ns *
474 *------------------------------------------------------------------*/
476 | (0 << 31 ) /* selectStrobe */
477 | (0 << 30 ) /* extWait */
478 | (1 << 26 ) /* writeSetup 10 ns */
479 | (3 << 20 ) /* writeStrobe 40 ns */
480 | (1 << 17 ) /* writeHold 10 ns */
481 | (1 << 13 ) /* readSetup 10 ns */
482 | (5 << 7 ) /* readStrobe 60 ns */
483 | (1 << 4 ) /* readHold 10 ns */
484 | (3 << 2 ) /* turnAround ?? ns */
485 | (0 << 0 ) /* asyncSize 8-bit bus */
488 emif_regs->AB1CR = acfg1; /* CS2 */
490 emif_regs->NANDFCR = 0x00000101; /* NAND flash on CS2 */
494 void davinci_nand_init(struct nand_chip *nand)
496 nand->chip_delay = 0;
497 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
498 nand->options |= NAND_USE_FLASH_BBT;
500 #ifdef CONFIG_SYS_NAND_HW_ECC
501 nand->ecc.mode = NAND_ECC_HW;
502 nand->ecc.size = 512;
504 nand->ecc.calculate = nand_davinci_calculate_ecc;
505 nand->ecc.correct = nand_davinci_correct_data;
506 nand->ecc.hwctl = nand_davinci_enable_hwecc;
508 nand->ecc.mode = NAND_ECC_SOFT;
509 #endif /* CONFIG_SYS_NAND_HW_ECC */
510 #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
511 nand->ecc.mode = NAND_ECC_HW_OOB_FIRST;
512 nand->ecc.size = 512;
513 nand->ecc.bytes = 10;
514 nand->ecc.calculate = nand_davinci_4bit_calculate_ecc;
515 nand->ecc.correct = nand_davinci_4bit_correct_data;
516 nand->ecc.hwctl = nand_davinci_4bit_enable_hwecc;
517 nand->ecc.layout = &nand_davinci_4bit_layout_oobfirst;
519 /* Set address of hardware control function */
520 nand->cmd_ctrl = nand_davinci_hwcontrol;
522 nand->dev_ready = nand_davinci_dev_ready;
527 int board_nand_init(struct nand_chip *chip) __attribute__((weak));
529 int board_nand_init(struct nand_chip *chip)
531 davinci_nand_init(chip);