Merge branch 'master' into for-next
[platform/adaptation/renesas_rcar/renesas_kernel.git] / drivers / mtd / nand / bf5xx_nand.c
1 /* linux/drivers/mtd/nand/bf5xx_nand.c
2  *
3  * Copyright 2006-2008 Analog Devices Inc.
4  *      http://blackfin.uclinux.org/
5  *      Bryan Wu <bryan.wu@analog.com>
6  *
7  * Blackfin BF5xx on-chip NAND flash controller driver
8  *
9  * Derived from drivers/mtd/nand/s3c2410.c
10  * Copyright (c) 2007 Ben Dooks <ben@simtec.co.uk>
11  *
12  * Derived from drivers/mtd/nand/cafe.c
13  * Copyright © 2006 Red Hat, Inc.
14  * Copyright © 2006 David Woodhouse <dwmw2@infradead.org>
15  *
16  * Changelog:
17  *      12-Jun-2007  Bryan Wu:  Initial version
18  *      18-Jul-2007  Bryan Wu:
19  *              - ECC_HW and ECC_SW supported
20  *              - DMA supported in ECC_HW
21  *              - YAFFS tested as rootfs in both ECC_HW and ECC_SW
22  *
23  * This program is free software; you can redistribute it and/or modify
24  * it under the terms of the GNU General Public License as published by
25  * the Free Software Foundation; either version 2 of the License, or
26  * (at your option) any later version.
27  *
28  * This program is distributed in the hope that it will be useful,
29  * but WITHOUT ANY WARRANTY; without even the implied warranty of
30  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
31  * GNU General Public License for more details.
32  *
33  * You should have received a copy of the GNU General Public License
34  * along with this program; if not, write to the Free Software
35  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
36 */
37
38 #include <linux/module.h>
39 #include <linux/types.h>
40 #include <linux/init.h>
41 #include <linux/kernel.h>
42 #include <linux/string.h>
43 #include <linux/ioport.h>
44 #include <linux/platform_device.h>
45 #include <linux/delay.h>
46 #include <linux/dma-mapping.h>
47 #include <linux/err.h>
48 #include <linux/slab.h>
49 #include <linux/io.h>
50 #include <linux/bitops.h>
51
52 #include <linux/mtd/mtd.h>
53 #include <linux/mtd/nand.h>
54 #include <linux/mtd/nand_ecc.h>
55 #include <linux/mtd/partitions.h>
56
57 #include <asm/blackfin.h>
58 #include <asm/dma.h>
59 #include <asm/cacheflush.h>
60 #include <asm/nand.h>
61 #include <asm/portmux.h>
62
63 #define DRV_NAME        "bf5xx-nand"
64 #define DRV_VERSION     "1.2"
65 #define DRV_AUTHOR      "Bryan Wu <bryan.wu@analog.com>"
66 #define DRV_DESC        "BF5xx on-chip NAND FLash Controller Driver"
67
68 /* NFC_STAT Masks */
69 #define NBUSY       0x01  /* Not Busy */
70 #define WB_FULL     0x02  /* Write Buffer Full */
71 #define PG_WR_STAT  0x04  /* Page Write Pending */
72 #define PG_RD_STAT  0x08  /* Page Read Pending */
73 #define WB_EMPTY    0x10  /* Write Buffer Empty */
74
75 /* NFC_IRQSTAT Masks */
76 #define NBUSYIRQ    0x01  /* Not Busy IRQ */
77 #define WB_OVF      0x02  /* Write Buffer Overflow */
78 #define WB_EDGE     0x04  /* Write Buffer Edge Detect */
79 #define RD_RDY      0x08  /* Read Data Ready */
80 #define WR_DONE     0x10  /* Page Write Done */
81
82 /* NFC_RST Masks */
83 #define ECC_RST     0x01  /* ECC (and NFC counters) Reset */
84
85 /* NFC_PGCTL Masks */
86 #define PG_RD_START 0x01  /* Page Read Start */
87 #define PG_WR_START 0x02  /* Page Write Start */
88
89 #ifdef CONFIG_MTD_NAND_BF5XX_HWECC
90 static int hardware_ecc = 1;
91 #else
92 static int hardware_ecc;
93 #endif
94
95 static const unsigned short bfin_nfc_pin_req[] =
96         {P_NAND_CE,
97          P_NAND_RB,
98          P_NAND_D0,
99          P_NAND_D1,
100          P_NAND_D2,
101          P_NAND_D3,
102          P_NAND_D4,
103          P_NAND_D5,
104          P_NAND_D6,
105          P_NAND_D7,
106          P_NAND_WE,
107          P_NAND_RE,
108          P_NAND_CLE,
109          P_NAND_ALE,
110          0};
111
112 #ifdef CONFIG_MTD_NAND_BF5XX_BOOTROM_ECC
113 static struct nand_ecclayout bootrom_ecclayout = {
114         .eccbytes = 24,
115         .eccpos = {
116                 0x8 * 0, 0x8 * 0 + 1, 0x8 * 0 + 2,
117                 0x8 * 1, 0x8 * 1 + 1, 0x8 * 1 + 2,
118                 0x8 * 2, 0x8 * 2 + 1, 0x8 * 2 + 2,
119                 0x8 * 3, 0x8 * 3 + 1, 0x8 * 3 + 2,
120                 0x8 * 4, 0x8 * 4 + 1, 0x8 * 4 + 2,
121                 0x8 * 5, 0x8 * 5 + 1, 0x8 * 5 + 2,
122                 0x8 * 6, 0x8 * 6 + 1, 0x8 * 6 + 2,
123                 0x8 * 7, 0x8 * 7 + 1, 0x8 * 7 + 2
124         },
125         .oobfree = {
126                 { 0x8 * 0 + 3, 5 },
127                 { 0x8 * 1 + 3, 5 },
128                 { 0x8 * 2 + 3, 5 },
129                 { 0x8 * 3 + 3, 5 },
130                 { 0x8 * 4 + 3, 5 },
131                 { 0x8 * 5 + 3, 5 },
132                 { 0x8 * 6 + 3, 5 },
133                 { 0x8 * 7 + 3, 5 },
134         }
135 };
136 #endif
137
138 /*
139  * Data structures for bf5xx nand flash controller driver
140  */
141
142 /* bf5xx nand info */
143 struct bf5xx_nand_info {
144         /* mtd info */
145         struct nand_hw_control          controller;
146         struct mtd_info                 mtd;
147         struct nand_chip                chip;
148
149         /* platform info */
150         struct bf5xx_nand_platform      *platform;
151
152         /* device info */
153         struct device                   *device;
154
155         /* DMA stuff */
156         struct completion               dma_completion;
157 };
158
159 /*
160  * Conversion functions
161  */
162 static struct bf5xx_nand_info *mtd_to_nand_info(struct mtd_info *mtd)
163 {
164         return container_of(mtd, struct bf5xx_nand_info, mtd);
165 }
166
167 static struct bf5xx_nand_info *to_nand_info(struct platform_device *pdev)
168 {
169         return platform_get_drvdata(pdev);
170 }
171
172 static struct bf5xx_nand_platform *to_nand_plat(struct platform_device *pdev)
173 {
174         return dev_get_platdata(&pdev->dev);
175 }
176
177 /*
178  * struct nand_chip interface function pointers
179  */
180
181 /*
182  * bf5xx_nand_hwcontrol
183  *
184  * Issue command and address cycles to the chip
185  */
186 static void bf5xx_nand_hwcontrol(struct mtd_info *mtd, int cmd,
187                                    unsigned int ctrl)
188 {
189         if (cmd == NAND_CMD_NONE)
190                 return;
191
192         while (bfin_read_NFC_STAT() & WB_FULL)
193                 cpu_relax();
194
195         if (ctrl & NAND_CLE)
196                 bfin_write_NFC_CMD(cmd);
197         else if (ctrl & NAND_ALE)
198                 bfin_write_NFC_ADDR(cmd);
199         SSYNC();
200 }
201
202 /*
203  * bf5xx_nand_devready()
204  *
205  * returns 0 if the nand is busy, 1 if it is ready
206  */
207 static int bf5xx_nand_devready(struct mtd_info *mtd)
208 {
209         unsigned short val = bfin_read_NFC_STAT();
210
211         if ((val & NBUSY) == NBUSY)
212                 return 1;
213         else
214                 return 0;
215 }
216
217 /*
218  * ECC functions
219  * These allow the bf5xx to use the controller's ECC
220  * generator block to ECC the data as it passes through
221  */
222
223 /*
224  * ECC error correction function
225  */
226 static int bf5xx_nand_correct_data_256(struct mtd_info *mtd, u_char *dat,
227                                         u_char *read_ecc, u_char *calc_ecc)
228 {
229         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
230         u32 syndrome[5];
231         u32 calced, stored;
232         int i;
233         unsigned short failing_bit, failing_byte;
234         u_char data;
235
236         calced = calc_ecc[0] | (calc_ecc[1] << 8) | (calc_ecc[2] << 16);
237         stored = read_ecc[0] | (read_ecc[1] << 8) | (read_ecc[2] << 16);
238
239         syndrome[0] = (calced ^ stored);
240
241         /*
242          * syndrome 0: all zero
243          * No error in data
244          * No action
245          */
246         if (!syndrome[0] || !calced || !stored)
247                 return 0;
248
249         /*
250          * sysdrome 0: only one bit is one
251          * ECC data was incorrect
252          * No action
253          */
254         if (hweight32(syndrome[0]) == 1) {
255                 dev_err(info->device, "ECC data was incorrect!\n");
256                 return 1;
257         }
258
259         syndrome[1] = (calced & 0x7FF) ^ (stored & 0x7FF);
260         syndrome[2] = (calced & 0x7FF) ^ ((calced >> 11) & 0x7FF);
261         syndrome[3] = (stored & 0x7FF) ^ ((stored >> 11) & 0x7FF);
262         syndrome[4] = syndrome[2] ^ syndrome[3];
263
264         for (i = 0; i < 5; i++)
265                 dev_info(info->device, "syndrome[%d] 0x%08x\n", i, syndrome[i]);
266
267         dev_info(info->device,
268                 "calced[0x%08x], stored[0x%08x]\n",
269                 calced, stored);
270
271         /*
272          * sysdrome 0: exactly 11 bits are one, each parity
273          * and parity' pair is 1 & 0 or 0 & 1.
274          * 1-bit correctable error
275          * Correct the error
276          */
277         if (hweight32(syndrome[0]) == 11 && syndrome[4] == 0x7FF) {
278                 dev_info(info->device,
279                         "1-bit correctable error, correct it.\n");
280                 dev_info(info->device,
281                         "syndrome[1] 0x%08x\n", syndrome[1]);
282
283                 failing_bit = syndrome[1] & 0x7;
284                 failing_byte = syndrome[1] >> 0x3;
285                 data = *(dat + failing_byte);
286                 data = data ^ (0x1 << failing_bit);
287                 *(dat + failing_byte) = data;
288
289                 return 0;
290         }
291
292         /*
293          * sysdrome 0: random data
294          * More than 1-bit error, non-correctable error
295          * Discard data, mark bad block
296          */
297         dev_err(info->device,
298                 "More than 1-bit error, non-correctable error.\n");
299         dev_err(info->device,
300                 "Please discard data, mark bad block\n");
301
302         return 1;
303 }
304
305 static int bf5xx_nand_correct_data(struct mtd_info *mtd, u_char *dat,
306                                         u_char *read_ecc, u_char *calc_ecc)
307 {
308         struct nand_chip *chip = mtd->priv;
309         int ret;
310
311         ret = bf5xx_nand_correct_data_256(mtd, dat, read_ecc, calc_ecc);
312
313         /* If ecc size is 512, correct second 256 bytes */
314         if (chip->ecc.size == 512) {
315                 dat += 256;
316                 read_ecc += 3;
317                 calc_ecc += 3;
318                 ret |= bf5xx_nand_correct_data_256(mtd, dat, read_ecc, calc_ecc);
319         }
320
321         return ret;
322 }
323
324 static void bf5xx_nand_enable_hwecc(struct mtd_info *mtd, int mode)
325 {
326         return;
327 }
328
329 static int bf5xx_nand_calculate_ecc(struct mtd_info *mtd,
330                 const u_char *dat, u_char *ecc_code)
331 {
332         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
333         struct nand_chip *chip = mtd->priv;
334         u16 ecc0, ecc1;
335         u32 code[2];
336         u8 *p;
337
338         /* first 3 bytes ECC code for 256 page size */
339         ecc0 = bfin_read_NFC_ECC0();
340         ecc1 = bfin_read_NFC_ECC1();
341
342         code[0] = (ecc0 & 0x7ff) | ((ecc1 & 0x7ff) << 11);
343
344         dev_dbg(info->device, "returning ecc 0x%08x\n", code[0]);
345
346         p = (u8 *) code;
347         memcpy(ecc_code, p, 3);
348
349         /* second 3 bytes ECC code for 512 ecc size */
350         if (chip->ecc.size == 512) {
351                 ecc0 = bfin_read_NFC_ECC2();
352                 ecc1 = bfin_read_NFC_ECC3();
353                 code[1] = (ecc0 & 0x7ff) | ((ecc1 & 0x7ff) << 11);
354
355                 /* second 3 bytes in ecc_code for second 256
356                  * bytes of 512 page size
357                  */
358                 p = (u8 *) (code + 1);
359                 memcpy((ecc_code + 3), p, 3);
360                 dev_dbg(info->device, "returning ecc 0x%08x\n", code[1]);
361         }
362
363         return 0;
364 }
365
366 /*
367  * PIO mode for buffer writing and reading
368  */
369 static void bf5xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
370 {
371         int i;
372         unsigned short val;
373
374         /*
375          * Data reads are requested by first writing to NFC_DATA_RD
376          * and then reading back from NFC_READ.
377          */
378         for (i = 0; i < len; i++) {
379                 while (bfin_read_NFC_STAT() & WB_FULL)
380                         cpu_relax();
381
382                 /* Contents do not matter */
383                 bfin_write_NFC_DATA_RD(0x0000);
384                 SSYNC();
385
386                 while ((bfin_read_NFC_IRQSTAT() & RD_RDY) != RD_RDY)
387                         cpu_relax();
388
389                 buf[i] = bfin_read_NFC_READ();
390
391                 val = bfin_read_NFC_IRQSTAT();
392                 val |= RD_RDY;
393                 bfin_write_NFC_IRQSTAT(val);
394                 SSYNC();
395         }
396 }
397
398 static uint8_t bf5xx_nand_read_byte(struct mtd_info *mtd)
399 {
400         uint8_t val;
401
402         bf5xx_nand_read_buf(mtd, &val, 1);
403
404         return val;
405 }
406
407 static void bf5xx_nand_write_buf(struct mtd_info *mtd,
408                                 const uint8_t *buf, int len)
409 {
410         int i;
411
412         for (i = 0; i < len; i++) {
413                 while (bfin_read_NFC_STAT() & WB_FULL)
414                         cpu_relax();
415
416                 bfin_write_NFC_DATA_WR(buf[i]);
417                 SSYNC();
418         }
419 }
420
421 static void bf5xx_nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
422 {
423         int i;
424         u16 *p = (u16 *) buf;
425         len >>= 1;
426
427         /*
428          * Data reads are requested by first writing to NFC_DATA_RD
429          * and then reading back from NFC_READ.
430          */
431         bfin_write_NFC_DATA_RD(0x5555);
432
433         SSYNC();
434
435         for (i = 0; i < len; i++)
436                 p[i] = bfin_read_NFC_READ();
437 }
438
439 static void bf5xx_nand_write_buf16(struct mtd_info *mtd,
440                                 const uint8_t *buf, int len)
441 {
442         int i;
443         u16 *p = (u16 *) buf;
444         len >>= 1;
445
446         for (i = 0; i < len; i++)
447                 bfin_write_NFC_DATA_WR(p[i]);
448
449         SSYNC();
450 }
451
452 /*
453  * DMA functions for buffer writing and reading
454  */
455 static irqreturn_t bf5xx_nand_dma_irq(int irq, void *dev_id)
456 {
457         struct bf5xx_nand_info *info = dev_id;
458
459         clear_dma_irqstat(CH_NFC);
460         disable_dma(CH_NFC);
461         complete(&info->dma_completion);
462
463         return IRQ_HANDLED;
464 }
465
466 static void bf5xx_nand_dma_rw(struct mtd_info *mtd,
467                                 uint8_t *buf, int is_read)
468 {
469         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
470         struct nand_chip *chip = mtd->priv;
471         unsigned short val;
472
473         dev_dbg(info->device, " mtd->%p, buf->%p, is_read %d\n",
474                         mtd, buf, is_read);
475
476         /*
477          * Before starting a dma transfer, be sure to invalidate/flush
478          * the cache over the address range of your DMA buffer to
479          * prevent cache coherency problems. Otherwise very subtle bugs
480          * can be introduced to your driver.
481          */
482         if (is_read)
483                 invalidate_dcache_range((unsigned int)buf,
484                                 (unsigned int)(buf + chip->ecc.size));
485         else
486                 flush_dcache_range((unsigned int)buf,
487                                 (unsigned int)(buf + chip->ecc.size));
488
489         /*
490          * This register must be written before each page is
491          * transferred to generate the correct ECC register
492          * values.
493          */
494         bfin_write_NFC_RST(ECC_RST);
495         SSYNC();
496         while (bfin_read_NFC_RST() & ECC_RST)
497                 cpu_relax();
498
499         disable_dma(CH_NFC);
500         clear_dma_irqstat(CH_NFC);
501
502         /* setup DMA register with Blackfin DMA API */
503         set_dma_config(CH_NFC, 0x0);
504         set_dma_start_addr(CH_NFC, (unsigned long) buf);
505
506         /* The DMAs have different size on BF52x and BF54x */
507 #ifdef CONFIG_BF52x
508         set_dma_x_count(CH_NFC, (chip->ecc.size >> 1));
509         set_dma_x_modify(CH_NFC, 2);
510         val = DI_EN | WDSIZE_16;
511 #endif
512
513 #ifdef CONFIG_BF54x
514         set_dma_x_count(CH_NFC, (chip->ecc.size >> 2));
515         set_dma_x_modify(CH_NFC, 4);
516         val = DI_EN | WDSIZE_32;
517 #endif
518         /* setup write or read operation */
519         if (is_read)
520                 val |= WNR;
521         set_dma_config(CH_NFC, val);
522         enable_dma(CH_NFC);
523
524         /* Start PAGE read/write operation */
525         if (is_read)
526                 bfin_write_NFC_PGCTL(PG_RD_START);
527         else
528                 bfin_write_NFC_PGCTL(PG_WR_START);
529         wait_for_completion(&info->dma_completion);
530 }
531
532 static void bf5xx_nand_dma_read_buf(struct mtd_info *mtd,
533                                         uint8_t *buf, int len)
534 {
535         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
536         struct nand_chip *chip = mtd->priv;
537
538         dev_dbg(info->device, "mtd->%p, buf->%p, int %d\n", mtd, buf, len);
539
540         if (len == chip->ecc.size)
541                 bf5xx_nand_dma_rw(mtd, buf, 1);
542         else
543                 bf5xx_nand_read_buf(mtd, buf, len);
544 }
545
546 static void bf5xx_nand_dma_write_buf(struct mtd_info *mtd,
547                                 const uint8_t *buf, int len)
548 {
549         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
550         struct nand_chip *chip = mtd->priv;
551
552         dev_dbg(info->device, "mtd->%p, buf->%p, len %d\n", mtd, buf, len);
553
554         if (len == chip->ecc.size)
555                 bf5xx_nand_dma_rw(mtd, (uint8_t *)buf, 0);
556         else
557                 bf5xx_nand_write_buf(mtd, buf, len);
558 }
559
560 static int bf5xx_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
561                 uint8_t *buf, int oob_required, int page)
562 {
563         bf5xx_nand_read_buf(mtd, buf, mtd->writesize);
564         bf5xx_nand_read_buf(mtd, chip->oob_poi, mtd->oobsize);
565
566         return 0;
567 }
568
569 static int bf5xx_nand_write_page_raw(struct mtd_info *mtd,
570                 struct nand_chip *chip, const uint8_t *buf, int oob_required)
571 {
572         bf5xx_nand_write_buf(mtd, buf, mtd->writesize);
573         bf5xx_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
574
575         return 0;
576 }
577
578 /*
579  * System initialization functions
580  */
581 static int bf5xx_nand_dma_init(struct bf5xx_nand_info *info)
582 {
583         int ret;
584
585         /* Do not use dma */
586         if (!hardware_ecc)
587                 return 0;
588
589         init_completion(&info->dma_completion);
590
591         /* Request NFC DMA channel */
592         ret = request_dma(CH_NFC, "BF5XX NFC driver");
593         if (ret < 0) {
594                 dev_err(info->device, " unable to get DMA channel\n");
595                 return ret;
596         }
597
598 #ifdef CONFIG_BF54x
599         /* Setup DMAC1 channel mux for NFC which shared with SDH */
600         bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() & ~1);
601         SSYNC();
602 #endif
603
604         set_dma_callback(CH_NFC, bf5xx_nand_dma_irq, info);
605
606         /* Turn off the DMA channel first */
607         disable_dma(CH_NFC);
608         return 0;
609 }
610
611 static void bf5xx_nand_dma_remove(struct bf5xx_nand_info *info)
612 {
613         /* Free NFC DMA channel */
614         if (hardware_ecc)
615                 free_dma(CH_NFC);
616 }
617
618 /*
619  * BF5XX NFC hardware initialization
620  *  - pin mux setup
621  *  - clear interrupt status
622  */
623 static int bf5xx_nand_hw_init(struct bf5xx_nand_info *info)
624 {
625         int err = 0;
626         unsigned short val;
627         struct bf5xx_nand_platform *plat = info->platform;
628
629         /* setup NFC_CTL register */
630         dev_info(info->device,
631                 "data_width=%d, wr_dly=%d, rd_dly=%d\n",
632                 (plat->data_width ? 16 : 8),
633                 plat->wr_dly, plat->rd_dly);
634
635         val = (1 << NFC_PG_SIZE_OFFSET) |
636                 (plat->data_width << NFC_NWIDTH_OFFSET) |
637                 (plat->rd_dly << NFC_RDDLY_OFFSET) |
638                 (plat->wr_dly << NFC_WRDLY_OFFSET);
639         dev_dbg(info->device, "NFC_CTL is 0x%04x\n", val);
640
641         bfin_write_NFC_CTL(val);
642         SSYNC();
643
644         /* clear interrupt status */
645         bfin_write_NFC_IRQMASK(0x0);
646         SSYNC();
647         val = bfin_read_NFC_IRQSTAT();
648         bfin_write_NFC_IRQSTAT(val);
649         SSYNC();
650
651         /* DMA initialization  */
652         if (bf5xx_nand_dma_init(info))
653                 err = -ENXIO;
654
655         return err;
656 }
657
658 /*
659  * Device management interface
660  */
661 static int bf5xx_nand_add_partition(struct bf5xx_nand_info *info)
662 {
663         struct mtd_info *mtd = &info->mtd;
664         struct mtd_partition *parts = info->platform->partitions;
665         int nr = info->platform->nr_partitions;
666
667         return mtd_device_register(mtd, parts, nr);
668 }
669
670 static int bf5xx_nand_remove(struct platform_device *pdev)
671 {
672         struct bf5xx_nand_info *info = to_nand_info(pdev);
673
674         /* first thing we need to do is release all our mtds
675          * and their partitions, then go through freeing the
676          * resources used
677          */
678         nand_release(&info->mtd);
679
680         peripheral_free_list(bfin_nfc_pin_req);
681         bf5xx_nand_dma_remove(info);
682
683         /* free the common resources */
684         kfree(info);
685
686         return 0;
687 }
688
689 static int bf5xx_nand_scan(struct mtd_info *mtd)
690 {
691         struct nand_chip *chip = mtd->priv;
692         int ret;
693
694         ret = nand_scan_ident(mtd, 1, NULL);
695         if (ret)
696                 return ret;
697
698         if (hardware_ecc) {
699                 /*
700                  * for nand with page size > 512B, think it as several sections with 512B
701                  */
702                 if (likely(mtd->writesize >= 512)) {
703                         chip->ecc.size = 512;
704                         chip->ecc.bytes = 6;
705                         chip->ecc.strength = 2;
706                 } else {
707                         chip->ecc.size = 256;
708                         chip->ecc.bytes = 3;
709                         chip->ecc.strength = 1;
710                         bfin_write_NFC_CTL(bfin_read_NFC_CTL() & ~(1 << NFC_PG_SIZE_OFFSET));
711                         SSYNC();
712                 }
713         }
714
715         return  nand_scan_tail(mtd);
716 }
717
718 /*
719  * bf5xx_nand_probe
720  *
721  * called by device layer when it finds a device matching
722  * one our driver can handled. This code checks to see if
723  * it can allocate all necessary resources then calls the
724  * nand layer to look for devices
725  */
726 static int bf5xx_nand_probe(struct platform_device *pdev)
727 {
728         struct bf5xx_nand_platform *plat = to_nand_plat(pdev);
729         struct bf5xx_nand_info *info = NULL;
730         struct nand_chip *chip = NULL;
731         struct mtd_info *mtd = NULL;
732         int err = 0;
733
734         dev_dbg(&pdev->dev, "(%p)\n", pdev);
735
736         if (!plat) {
737                 dev_err(&pdev->dev, "no platform specific information\n");
738                 return -EINVAL;
739         }
740
741         if (peripheral_request_list(bfin_nfc_pin_req, DRV_NAME)) {
742                 dev_err(&pdev->dev, "requesting Peripherals failed\n");
743                 return -EFAULT;
744         }
745
746         info = kzalloc(sizeof(*info), GFP_KERNEL);
747         if (info == NULL) {
748                 dev_err(&pdev->dev, "no memory for flash info\n");
749                 err = -ENOMEM;
750                 goto out_err_kzalloc;
751         }
752
753         platform_set_drvdata(pdev, info);
754
755         spin_lock_init(&info->controller.lock);
756         init_waitqueue_head(&info->controller.wq);
757
758         info->device     = &pdev->dev;
759         info->platform   = plat;
760
761         /* initialise chip data struct */
762         chip = &info->chip;
763
764         if (plat->data_width)
765                 chip->options |= NAND_BUSWIDTH_16;
766
767         chip->options |= NAND_CACHEPRG | NAND_SKIP_BBTSCAN;
768
769         chip->read_buf = (plat->data_width) ?
770                 bf5xx_nand_read_buf16 : bf5xx_nand_read_buf;
771         chip->write_buf = (plat->data_width) ?
772                 bf5xx_nand_write_buf16 : bf5xx_nand_write_buf;
773
774         chip->read_byte    = bf5xx_nand_read_byte;
775
776         chip->cmd_ctrl     = bf5xx_nand_hwcontrol;
777         chip->dev_ready    = bf5xx_nand_devready;
778
779         chip->priv         = &info->mtd;
780         chip->controller   = &info->controller;
781
782         chip->IO_ADDR_R    = (void __iomem *) NFC_READ;
783         chip->IO_ADDR_W    = (void __iomem *) NFC_DATA_WR;
784
785         chip->chip_delay   = 0;
786
787         /* initialise mtd info data struct */
788         mtd             = &info->mtd;
789         mtd->priv       = chip;
790         mtd->owner      = THIS_MODULE;
791
792         /* initialise the hardware */
793         err = bf5xx_nand_hw_init(info);
794         if (err)
795                 goto out_err_hw_init;
796
797         /* setup hardware ECC data struct */
798         if (hardware_ecc) {
799 #ifdef CONFIG_MTD_NAND_BF5XX_BOOTROM_ECC
800                 chip->ecc.layout = &bootrom_ecclayout;
801 #endif
802                 chip->read_buf      = bf5xx_nand_dma_read_buf;
803                 chip->write_buf     = bf5xx_nand_dma_write_buf;
804                 chip->ecc.calculate = bf5xx_nand_calculate_ecc;
805                 chip->ecc.correct   = bf5xx_nand_correct_data;
806                 chip->ecc.mode      = NAND_ECC_HW;
807                 chip->ecc.hwctl     = bf5xx_nand_enable_hwecc;
808                 chip->ecc.read_page_raw = bf5xx_nand_read_page_raw;
809                 chip->ecc.write_page_raw = bf5xx_nand_write_page_raw;
810         } else {
811                 chip->ecc.mode      = NAND_ECC_SOFT;
812         }
813
814         /* scan hardware nand chip and setup mtd info data struct */
815         if (bf5xx_nand_scan(mtd)) {
816                 err = -ENXIO;
817                 goto out_err_nand_scan;
818         }
819
820 #ifdef CONFIG_MTD_NAND_BF5XX_BOOTROM_ECC
821         chip->badblockpos = 63;
822 #endif
823
824         /* add NAND partition */
825         bf5xx_nand_add_partition(info);
826
827         dev_dbg(&pdev->dev, "initialised ok\n");
828         return 0;
829
830 out_err_nand_scan:
831         bf5xx_nand_dma_remove(info);
832 out_err_hw_init:
833         kfree(info);
834 out_err_kzalloc:
835         peripheral_free_list(bfin_nfc_pin_req);
836
837         return err;
838 }
839
840 /* PM Support */
841 #ifdef CONFIG_PM
842
843 static int bf5xx_nand_suspend(struct platform_device *dev, pm_message_t pm)
844 {
845         struct bf5xx_nand_info *info = platform_get_drvdata(dev);
846
847         return 0;
848 }
849
850 static int bf5xx_nand_resume(struct platform_device *dev)
851 {
852         struct bf5xx_nand_info *info = platform_get_drvdata(dev);
853
854         return 0;
855 }
856
857 #else
858 #define bf5xx_nand_suspend NULL
859 #define bf5xx_nand_resume NULL
860 #endif
861
862 /* driver device registration */
863 static struct platform_driver bf5xx_nand_driver = {
864         .probe          = bf5xx_nand_probe,
865         .remove         = bf5xx_nand_remove,
866         .suspend        = bf5xx_nand_suspend,
867         .resume         = bf5xx_nand_resume,
868         .driver         = {
869                 .name   = DRV_NAME,
870                 .owner  = THIS_MODULE,
871         },
872 };
873
874 module_platform_driver(bf5xx_nand_driver);
875
876 MODULE_LICENSE("GPL");
877 MODULE_AUTHOR(DRV_AUTHOR);
878 MODULE_DESCRIPTION(DRV_DESC);
879 MODULE_ALIAS("platform:" DRV_NAME);