drivers/mtd/nand/bf5xx_nand.c

   1 /* linux/drivers/mtd/nand/bf5xx_nand.c
   2  *
   3  * Copyright 2006-2008 Analog Devices Inc.
   4  *      http://blackfin.uclinux.org/
   5  *      Bryan Wu <bryan.wu@analog.com>
   6  *
   7  * Blackfin BF5xx on-chip NAND flash controller driver
   8  *
   9  * Derived from drivers/mtd/nand/s3c2410.c
  10  * Copyright (c) 2007 Ben Dooks <ben@simtec.co.uk>
  11  *
  12  * Derived from drivers/mtd/nand/cafe.c
  13  * Copyright © 2006 Red Hat, Inc.
  14  * Copyright © 2006 David Woodhouse <dwmw2@infradead.org>
  15  *
  16  * Changelog:
  17  *      12-Jun-2007  Bryan Wu:  Initial version
  18  *      18-Jul-2007  Bryan Wu:
  19  *              - ECC_HW and ECC_SW supported
  20  *              - DMA supported in ECC_HW
  21  *              - YAFFS tested as rootfs in both ECC_HW and ECC_SW
  22  *
  23  * This program is free software; you can redistribute it and/or modify
  24  * it under the terms of the GNU General Public License as published by
  25  * the Free Software Foundation; either version 2 of the License, or
  26  * (at your option) any later version.
  27  *
  28  * This program is distributed in the hope that it will be useful,
  29  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  30  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  31  * GNU General Public License for more details.
  32  *
  33  * You should have received a copy of the GNU General Public License
  34  * along with this program; if not, write to the Free Software
  35  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  36 */
  37
  38 #include <linux/module.h>
  39 #include <linux/types.h>
  40 #include <linux/init.h>
  41 #include <linux/kernel.h>
  42 #include <linux/string.h>
  43 #include <linux/ioport.h>
  44 #include <linux/platform_device.h>
  45 #include <linux/delay.h>
  46 #include <linux/dma-mapping.h>
  47 #include <linux/err.h>
  48 #include <linux/slab.h>
  49 #include <linux/io.h>
  50 #include <linux/bitops.h>
  51
  52 #include <linux/mtd/mtd.h>
  53 #include <linux/mtd/nand.h>
  54 #include <linux/mtd/nand_ecc.h>
  55 #include <linux/mtd/partitions.h>
  56
  57 #include <asm/blackfin.h>
  58 #include <asm/dma.h>
  59 #include <asm/cacheflush.h>
  60 #include <asm/nand.h>
  61 #include <asm/portmux.h>
  62
  63 #define DRV_NAME        "bf5xx-nand"
  64 #define DRV_VERSION     "1.2"
  65 #define DRV_AUTHOR      "Bryan Wu <bryan.wu@analog.com>"
  66 #define DRV_DESC        "BF5xx on-chip NAND FLash Controller Driver"
  67
  68 /* NFC_STAT Masks */
  69 #define NBUSY       0x01  /* Not Busy */
  70 #define WB_FULL     0x02  /* Write Buffer Full */
  71 #define PG_WR_STAT  0x04  /* Page Write Pending */
  72 #define PG_RD_STAT  0x08  /* Page Read Pending */
  73 #define WB_EMPTY    0x10  /* Write Buffer Empty */
  74
  75 /* NFC_IRQSTAT Masks */
  76 #define NBUSYIRQ    0x01  /* Not Busy IRQ */
  77 #define WB_OVF      0x02  /* Write Buffer Overflow */
  78 #define WB_EDGE     0x04  /* Write Buffer Edge Detect */
  79 #define RD_RDY      0x08  /* Read Data Ready */
  80 #define WR_DONE     0x10  /* Page Write Done */
  81
  82 /* NFC_RST Masks */
  83 #define ECC_RST     0x01  /* ECC (and NFC counters) Reset */
  84
  85 /* NFC_PGCTL Masks */
  86 #define PG_RD_START 0x01  /* Page Read Start */
  87 #define PG_WR_START 0x02  /* Page Write Start */
  88
  89 #ifdef CONFIG_MTD_NAND_BF5XX_HWECC
  90 static int hardware_ecc = 1;
  91 #else
  92 static int hardware_ecc;
  93 #endif
  94
  95 static const unsigned short bfin_nfc_pin_req[] =
  96         {P_NAND_CE,
  97          P_NAND_RB,
  98          P_NAND_D0,
  99          P_NAND_D1,
 100          P_NAND_D2,
 101          P_NAND_D3,
 102          P_NAND_D4,
 103          P_NAND_D5,
 104          P_NAND_D6,
 105          P_NAND_D7,
 106          P_NAND_WE,
 107          P_NAND_RE,
 108          P_NAND_CLE,
 109          P_NAND_ALE,
 110          0};
 111
 112 #ifdef CONFIG_MTD_NAND_BF5XX_BOOTROM_ECC
 113 static uint8_t bbt_pattern[] = { 0xff };
 114
 115 static struct nand_bbt_descr bootrom_bbt = {
 116         .options = 0,
 117         .offs = 63,
 118         .len = 1,
 119         .pattern = bbt_pattern,
 120 };
 121
 122 static struct nand_ecclayout bootrom_ecclayout = {
 123         .eccbytes = 24,
 124         .eccpos = {
 125                 0x8 * 0, 0x8 * 0 + 1, 0x8 * 0 + 2,
 126                 0x8 * 1, 0x8 * 1 + 1, 0x8 * 1 + 2,
 127                 0x8 * 2, 0x8 * 2 + 1, 0x8 * 2 + 2,
 128                 0x8 * 3, 0x8 * 3 + 1, 0x8 * 3 + 2,
 129                 0x8 * 4, 0x8 * 4 + 1, 0x8 * 4 + 2,
 130                 0x8 * 5, 0x8 * 5 + 1, 0x8 * 5 + 2,
 131                 0x8 * 6, 0x8 * 6 + 1, 0x8 * 6 + 2,
 132                 0x8 * 7, 0x8 * 7 + 1, 0x8 * 7 + 2
 133         },
 134         .oobfree = {
 135                 { 0x8 * 0 + 3, 5 },
 136                 { 0x8 * 1 + 3, 5 },
 137                 { 0x8 * 2 + 3, 5 },
 138                 { 0x8 * 3 + 3, 5 },
 139                 { 0x8 * 4 + 3, 5 },
 140                 { 0x8 * 5 + 3, 5 },
 141                 { 0x8 * 6 + 3, 5 },
 142                 { 0x8 * 7 + 3, 5 },
 143         }
 144 };
 145 #endif
 146
 147 /*
 148  * Data structures for bf5xx nand flash controller driver
 149  */
 150
 151 /* bf5xx nand info */
 152 struct bf5xx_nand_info {
 153         /* mtd info */
 154         struct nand_hw_control          controller;
 155         struct mtd_info                 mtd;
 156         struct nand_chip                chip;
 157
 158         /* platform info */
 159         struct bf5xx_nand_platform      *platform;
 160
 161         /* device info */
 162         struct device                   *device;
 163
 164         /* DMA stuff */
 165         struct completion               dma_completion;
 166 };
 167
 168 /*
 169  * Conversion functions
 170  */
 171 static struct bf5xx_nand_info *mtd_to_nand_info(struct mtd_info *mtd)
 172 {
 173         return container_of(mtd, struct bf5xx_nand_info, mtd);
 174 }
 175
 176 static struct bf5xx_nand_info *to_nand_info(struct platform_device *pdev)
 177 {
 178         return platform_get_drvdata(pdev);
 179 }
 180
 181 static struct bf5xx_nand_platform *to_nand_plat(struct platform_device *pdev)
 182 {
 183         return pdev->dev.platform_data;
 184 }
 185
 186 /*
 187  * struct nand_chip interface function pointers
 188  */
 189
 190 /*
 191  * bf5xx_nand_hwcontrol
 192  *
 193  * Issue command and address cycles to the chip
 194  */
 195 static void bf5xx_nand_hwcontrol(struct mtd_info *mtd, int cmd,
 196                                    unsigned int ctrl)
 197 {
 198         if (cmd == NAND_CMD_NONE)
 199                 return;
 200
 201         while (bfin_read_NFC_STAT() & WB_FULL)
 202                 cpu_relax();
 203
 204         if (ctrl & NAND_CLE)
 205                 bfin_write_NFC_CMD(cmd);
 206         else if (ctrl & NAND_ALE)
 207                 bfin_write_NFC_ADDR(cmd);
 208         SSYNC();
 209 }
 210
 211 /*
 212  * bf5xx_nand_devready()
 213  *
 214  * returns 0 if the nand is busy, 1 if it is ready
 215  */
 216 static int bf5xx_nand_devready(struct mtd_info *mtd)
 217 {
 218         unsigned short val = bfin_read_NFC_STAT();
 219
 220         if ((val & NBUSY) == NBUSY)
 221                 return 1;
 222         else
 223                 return 0;
 224 }
 225
 226 /*
 227  * ECC functions
 228  * These allow the bf5xx to use the controller's ECC
 229  * generator block to ECC the data as it passes through
 230  */
 231
 232 /*
 233  * ECC error correction function
 234  */
 235 static int bf5xx_nand_correct_data_256(struct mtd_info *mtd, u_char *dat,
 236                                         u_char *read_ecc, u_char *calc_ecc)
 237 {
 238         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
 239         u32 syndrome[5];
 240         u32 calced, stored;
 241         int i;
 242         unsigned short failing_bit, failing_byte;
 243         u_char data;
 244
 245         calced = calc_ecc[0] | (calc_ecc[1] << 8) | (calc_ecc[2] << 16);
 246         stored = read_ecc[0] | (read_ecc[1] << 8) | (read_ecc[2] << 16);
 247
 248         syndrome[0] = (calced ^ stored);
 249
 250         /*
 251          * syndrome 0: all zero
 252          * No error in data
 253          * No action
 254          */
 255         if (!syndrome[0] || !calced || !stored)
 256                 return 0;
 257
 258         /*
 259          * sysdrome 0: only one bit is one
 260          * ECC data was incorrect
 261          * No action
 262          */
 263         if (hweight32(syndrome[0]) == 1) {
 264                 dev_err(info->device, "ECC data was incorrect!\n");
 265                 return 1;
 266         }
 267
 268         syndrome[1] = (calced & 0x7FF) ^ (stored & 0x7FF);
 269         syndrome[2] = (calced & 0x7FF) ^ ((calced >> 11) & 0x7FF);
 270         syndrome[3] = (stored & 0x7FF) ^ ((stored >> 11) & 0x7FF);
 271         syndrome[4] = syndrome[2] ^ syndrome[3];
 272
 273         for (i = 0; i < 5; i++)
 274                 dev_info(info->device, "syndrome[%d] 0x%08x\n", i, syndrome[i]);
 275
 276         dev_info(info->device,
 277                 "calced[0x%08x], stored[0x%08x]\n",
 278                 calced, stored);
 279
 280         /*
 281          * sysdrome 0: exactly 11 bits are one, each parity
 282          * and parity' pair is 1 & 0 or 0 & 1.
 283          * 1-bit correctable error
 284          * Correct the error
 285          */
 286         if (hweight32(syndrome[0]) == 11 && syndrome[4] == 0x7FF) {
 287                 dev_info(info->device,
 288                         "1-bit correctable error, correct it.\n");
 289                 dev_info(info->device,
 290                         "syndrome[1] 0x%08x\n", syndrome[1]);
 291
 292                 failing_bit = syndrome[1] & 0x7;
 293                 failing_byte = syndrome[1] >> 0x3;
 294                 data = *(dat + failing_byte);
 295                 data = data ^ (0x1 << failing_bit);
 296                 *(dat + failing_byte) = data;
 297
 298                 return 0;
 299         }
 300
 301         /*
 302          * sysdrome 0: random data
 303          * More than 1-bit error, non-correctable error
 304          * Discard data, mark bad block
 305          */
 306         dev_err(info->device,
 307                 "More than 1-bit error, non-correctable error.\n");
 308         dev_err(info->device,
 309                 "Please discard data, mark bad block\n");
 310
 311         return 1;
 312 }
 313
 314 static int bf5xx_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 315                                         u_char *read_ecc, u_char *calc_ecc)
 316 {
 317         struct nand_chip *chip = mtd->priv;
 318         int ret;
 319
 320         ret = bf5xx_nand_correct_data_256(mtd, dat, read_ecc, calc_ecc);
 321
 322         /* If ecc size is 512, correct second 256 bytes */
 323         if (chip->ecc.size == 512) {
 324                 dat += 256;
 325                 read_ecc += 3;
 326                 calc_ecc += 3;
 327                 ret |= bf5xx_nand_correct_data_256(mtd, dat, read_ecc, calc_ecc);
 328         }
 329
 330         return ret;
 331 }
 332
 333 static void bf5xx_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 334 {
 335         return;
 336 }
 337
 338 static int bf5xx_nand_calculate_ecc(struct mtd_info *mtd,
 339                 const u_char *dat, u_char *ecc_code)
 340 {
 341         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
 342         struct nand_chip *chip = mtd->priv;
 343         u16 ecc0, ecc1;
 344         u32 code[2];
 345         u8 *p;
 346
 347         /* first 3 bytes ECC code for 256 page size */
 348         ecc0 = bfin_read_NFC_ECC0();
 349         ecc1 = bfin_read_NFC_ECC1();
 350
 351         code[0] = (ecc0 & 0x7ff) | ((ecc1 & 0x7ff) << 11);
 352
 353         dev_dbg(info->device, "returning ecc 0x%08x\n", code[0]);
 354
 355         p = (u8 *) code;
 356         memcpy(ecc_code, p, 3);
 357
 358         /* second 3 bytes ECC code for 512 ecc size */
 359         if (chip->ecc.size == 512) {
 360                 ecc0 = bfin_read_NFC_ECC2();
 361                 ecc1 = bfin_read_NFC_ECC3();
 362                 code[1] = (ecc0 & 0x7ff) | ((ecc1 & 0x7ff) << 11);
 363
 364                 /* second 3 bytes in ecc_code for second 256
 365                  * bytes of 512 page size
 366                  */
 367                 p = (u8 *) (code + 1);
 368                 memcpy((ecc_code + 3), p, 3);
 369                 dev_dbg(info->device, "returning ecc 0x%08x\n", code[1]);
 370         }
 371
 372         return 0;
 373 }
 374
 375 /*
 376  * PIO mode for buffer writing and reading
 377  */
 378 static void bf5xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 379 {
 380         int i;
 381         unsigned short val;
 382
 383         /*
 384          * Data reads are requested by first writing to NFC_DATA_RD
 385          * and then reading back from NFC_READ.
 386          */
 387         for (i = 0; i < len; i++) {
 388                 while (bfin_read_NFC_STAT() & WB_FULL)
 389                         cpu_relax();
 390
 391                 /* Contents do not matter */
 392                 bfin_write_NFC_DATA_RD(0x0000);
 393                 SSYNC();
 394
 395                 while ((bfin_read_NFC_IRQSTAT() & RD_RDY) != RD_RDY)
 396                         cpu_relax();
 397
 398                 buf[i] = bfin_read_NFC_READ();
 399
 400                 val = bfin_read_NFC_IRQSTAT();
 401                 val |= RD_RDY;
 402                 bfin_write_NFC_IRQSTAT(val);
 403                 SSYNC();
 404         }
 405 }
 406
 407 static uint8_t bf5xx_nand_read_byte(struct mtd_info *mtd)
 408 {
 409         uint8_t val;
 410
 411         bf5xx_nand_read_buf(mtd, &val, 1);
 412
 413         return val;
 414 }
 415
 416 static void bf5xx_nand_write_buf(struct mtd_info *mtd,
 417                                 const uint8_t *buf, int len)
 418 {
 419         int i;
 420
 421         for (i = 0; i < len; i++) {
 422                 while (bfin_read_NFC_STAT() & WB_FULL)
 423                         cpu_relax();
 424
 425                 bfin_write_NFC_DATA_WR(buf[i]);
 426                 SSYNC();
 427         }
 428 }
 429
 430 static void bf5xx_nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 431 {
 432         int i;
 433         u16 *p = (u16 *) buf;
 434         len >>= 1;
 435
 436         /*
 437          * Data reads are requested by first writing to NFC_DATA_RD
 438          * and then reading back from NFC_READ.
 439          */
 440         bfin_write_NFC_DATA_RD(0x5555);
 441
 442         SSYNC();
 443
 444         for (i = 0; i < len; i++)
 445                 p[i] = bfin_read_NFC_READ();
 446 }
 447
 448 static void bf5xx_nand_write_buf16(struct mtd_info *mtd,
 449                                 const uint8_t *buf, int len)
 450 {
 451         int i;
 452         u16 *p = (u16 *) buf;
 453         len >>= 1;
 454
 455         for (i = 0; i < len; i++)
 456                 bfin_write_NFC_DATA_WR(p[i]);
 457
 458         SSYNC();
 459 }
 460
 461 /*
 462  * DMA functions for buffer writing and reading
 463  */
 464 static irqreturn_t bf5xx_nand_dma_irq(int irq, void *dev_id)
 465 {
 466         struct bf5xx_nand_info *info = dev_id;
 467
 468         clear_dma_irqstat(CH_NFC);
 469         disable_dma(CH_NFC);
 470         complete(&info->dma_completion);
 471
 472         return IRQ_HANDLED;
 473 }
 474
 475 static void bf5xx_nand_dma_rw(struct mtd_info *mtd,
 476                                 uint8_t *buf, int is_read)
 477 {
 478         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
 479         struct nand_chip *chip = mtd->priv;
 480         unsigned short val;
 481
 482         dev_dbg(info->device, " mtd->%p, buf->%p, is_read %d\n",
 483                         mtd, buf, is_read);
 484
 485         /*
 486          * Before starting a dma transfer, be sure to invalidate/flush
 487          * the cache over the address range of your DMA buffer to
 488          * prevent cache coherency problems. Otherwise very subtle bugs
 489          * can be introduced to your driver.
 490          */
 491         if (is_read)
 492                 invalidate_dcache_range((unsigned int)buf,
 493                                 (unsigned int)(buf + chip->ecc.size));
 494         else
 495                 flush_dcache_range((unsigned int)buf,
 496                                 (unsigned int)(buf + chip->ecc.size));
 497
 498         /*
 499          * This register must be written before each page is
 500          * transferred to generate the correct ECC register
 501          * values.
 502          */
 503         bfin_write_NFC_RST(ECC_RST);
 504         SSYNC();
 505         while (bfin_read_NFC_RST() & ECC_RST)
 506                 cpu_relax();
 507
 508         disable_dma(CH_NFC);
 509         clear_dma_irqstat(CH_NFC);
 510
 511         /* setup DMA register with Blackfin DMA API */
 512         set_dma_config(CH_NFC, 0x0);
 513         set_dma_start_addr(CH_NFC, (unsigned long) buf);
 514
 515         /* The DMAs have different size on BF52x and BF54x */
 516 #ifdef CONFIG_BF52x
 517         set_dma_x_count(CH_NFC, (chip->ecc.size >> 1));
 518         set_dma_x_modify(CH_NFC, 2);
 519         val = DI_EN | WDSIZE_16;
 520 #endif
 521
 522 #ifdef CONFIG_BF54x
 523         set_dma_x_count(CH_NFC, (chip->ecc.size >> 2));
 524         set_dma_x_modify(CH_NFC, 4);
 525         val = DI_EN | WDSIZE_32;
 526 #endif
 527         /* setup write or read operation */
 528         if (is_read)
 529                 val |= WNR;
 530         set_dma_config(CH_NFC, val);
 531         enable_dma(CH_NFC);
 532
 533         /* Start PAGE read/write operation */
 534         if (is_read)
 535                 bfin_write_NFC_PGCTL(PG_RD_START);
 536         else
 537                 bfin_write_NFC_PGCTL(PG_WR_START);
 538         wait_for_completion(&info->dma_completion);
 539 }
 540
 541 static void bf5xx_nand_dma_read_buf(struct mtd_info *mtd,
 542                                         uint8_t *buf, int len)
 543 {
 544         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
 545         struct nand_chip *chip = mtd->priv;
 546
 547         dev_dbg(info->device, "mtd->%p, buf->%p, int %d\n", mtd, buf, len);
 548
 549         if (len == chip->ecc.size)
 550                 bf5xx_nand_dma_rw(mtd, buf, 1);
 551         else
 552                 bf5xx_nand_read_buf(mtd, buf, len);
 553 }
 554
 555 static void bf5xx_nand_dma_write_buf(struct mtd_info *mtd,
 556                                 const uint8_t *buf, int len)
 557 {
 558         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
 559         struct nand_chip *chip = mtd->priv;
 560
 561         dev_dbg(info->device, "mtd->%p, buf->%p, len %d\n", mtd, buf, len);
 562
 563         if (len == chip->ecc.size)
 564                 bf5xx_nand_dma_rw(mtd, (uint8_t *)buf, 0);
 565         else
 566                 bf5xx_nand_write_buf(mtd, buf, len);
 567 }
 568
 569 static int bf5xx_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
 570                 uint8_t *buf, int page)
 571 {
 572         bf5xx_nand_read_buf(mtd, buf, mtd->writesize);
 573         bf5xx_nand_read_buf(mtd, chip->oob_poi, mtd->oobsize);
 574
 575         return 0;
 576 }
 577
 578 static void bf5xx_nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
 579                 const uint8_t *buf)
 580 {
 581         bf5xx_nand_write_buf(mtd, buf, mtd->writesize);
 582         bf5xx_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 583 }
 584
 585 /*
 586  * System initialization functions
 587  */
 588 static int bf5xx_nand_dma_init(struct bf5xx_nand_info *info)
 589 {
 590         int ret;
 591
 592         /* Do not use dma */
 593         if (!hardware_ecc)
 594                 return 0;
 595
 596         init_completion(&info->dma_completion);
 597
 598         /* Request NFC DMA channel */
 599         ret = request_dma(CH_NFC, "BF5XX NFC driver");
 600         if (ret < 0) {
 601                 dev_err(info->device, " unable to get DMA channel\n");
 602                 return ret;
 603         }
 604
 605 #ifdef CONFIG_BF54x
 606         /* Setup DMAC1 channel mux for NFC which shared with SDH */
 607         bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() & ~1);
 608         SSYNC();
 609 #endif
 610
 611         set_dma_callback(CH_NFC, bf5xx_nand_dma_irq, info);
 612
 613         /* Turn off the DMA channel first */
 614         disable_dma(CH_NFC);
 615         return 0;
 616 }
 617
 618 static void bf5xx_nand_dma_remove(struct bf5xx_nand_info *info)
 619 {
 620         /* Free NFC DMA channel */
 621         if (hardware_ecc)
 622                 free_dma(CH_NFC);
 623 }
 624
 625 /*
 626  * BF5XX NFC hardware initialization
 627  *  - pin mux setup
 628  *  - clear interrupt status
 629  */
 630 static int bf5xx_nand_hw_init(struct bf5xx_nand_info *info)
 631 {
 632         int err = 0;
 633         unsigned short val;
 634         struct bf5xx_nand_platform *plat = info->platform;
 635
 636         /* setup NFC_CTL register */
 637         dev_info(info->device,
 638                 "data_width=%d, wr_dly=%d, rd_dly=%d\n",
 639                 (plat->data_width ? 16 : 8),
 640                 plat->wr_dly, plat->rd_dly);
 641
 642         val = (1 << NFC_PG_SIZE_OFFSET) |
 643                 (plat->data_width << NFC_NWIDTH_OFFSET) |
 644                 (plat->rd_dly << NFC_RDDLY_OFFSET) |
 645                 (plat->wr_dly << NFC_WRDLY_OFFSET);
 646         dev_dbg(info->device, "NFC_CTL is 0x%04x\n", val);
 647
 648         bfin_write_NFC_CTL(val);
 649         SSYNC();
 650
 651         /* clear interrupt status */
 652         bfin_write_NFC_IRQMASK(0x0);
 653         SSYNC();
 654         val = bfin_read_NFC_IRQSTAT();
 655         bfin_write_NFC_IRQSTAT(val);
 656         SSYNC();
 657
 658         /* DMA initialization  */
 659         if (bf5xx_nand_dma_init(info))
 660                 err = -ENXIO;
 661
 662         return err;
 663 }
 664
 665 /*
 666  * Device management interface
 667  */
 668 static int __devinit bf5xx_nand_add_partition(struct bf5xx_nand_info *info)
 669 {
 670         struct mtd_info *mtd = &info->mtd;
 671
 672 #ifdef CONFIG_MTD_PARTITIONS
 673         struct mtd_partition *parts = info->platform->partitions;
 674         int nr = info->platform->nr_partitions;
 675
 676         return add_mtd_partitions(mtd, parts, nr);
 677 #else
 678         return add_mtd_device(mtd);
 679 #endif
 680 }
 681
 682 static int __devexit bf5xx_nand_remove(struct platform_device *pdev)
 683 {
 684         struct bf5xx_nand_info *info = to_nand_info(pdev);
 685         struct mtd_info *mtd = NULL;
 686
 687         platform_set_drvdata(pdev, NULL);
 688
 689         /* first thing we need to do is release all our mtds
 690          * and their partitions, then go through freeing the
 691          * resources used
 692          */
 693         mtd = &info->mtd;
 694         if (mtd) {
 695                 nand_release(mtd);
 696                 kfree(mtd);
 697         }
 698
 699         peripheral_free_list(bfin_nfc_pin_req);
 700         bf5xx_nand_dma_remove(info);
 701
 702         /* free the common resources */
 703         kfree(info);
 704
 705         return 0;
 706 }
 707
 708 static int bf5xx_nand_scan(struct mtd_info *mtd)
 709 {
 710         struct nand_chip *chip = mtd->priv;
 711         int ret;
 712
 713         ret = nand_scan_ident(mtd, 1);
 714         if (ret)
 715                 return ret;
 716
 717         if (hardware_ecc) {
 718                 /*
 719                  * for nand with page size > 512B, think it as several sections with 512B
 720                  */
 721                 if (likely(mtd->writesize >= 512)) {
 722                         chip->ecc.size = 512;
 723                         chip->ecc.bytes = 6;
 724                 } else {
 725                         chip->ecc.size = 256;
 726                         chip->ecc.bytes = 3;
 727                         bfin_write_NFC_CTL(bfin_read_NFC_CTL() & ~(1 << NFC_PG_SIZE_OFFSET));
 728                         SSYNC();
 729                 }
 730         }
 731
 732         return  nand_scan_tail(mtd);
 733 }
 734
 735 /*
 736  * bf5xx_nand_probe
 737  *
 738  * called by device layer when it finds a device matching
 739  * one our driver can handled. This code checks to see if
 740  * it can allocate all necessary resources then calls the
 741  * nand layer to look for devices
 742  */
 743 static int __devinit bf5xx_nand_probe(struct platform_device *pdev)
 744 {
 745         struct bf5xx_nand_platform *plat = to_nand_plat(pdev);
 746         struct bf5xx_nand_info *info = NULL;
 747         struct nand_chip *chip = NULL;
 748         struct mtd_info *mtd = NULL;
 749         int err = 0;
 750
 751         dev_dbg(&pdev->dev, "(%p)\n", pdev);
 752
 753         if (!plat) {
 754                 dev_err(&pdev->dev, "no platform specific information\n");
 755                 return -EINVAL;
 756         }
 757
 758         if (peripheral_request_list(bfin_nfc_pin_req, DRV_NAME)) {
 759                 dev_err(&pdev->dev, "requesting Peripherals failed\n");
 760                 return -EFAULT;
 761         }
 762
 763         info = kzalloc(sizeof(*info), GFP_KERNEL);
 764         if (info == NULL) {
 765                 dev_err(&pdev->dev, "no memory for flash info\n");
 766                 err = -ENOMEM;
 767                 goto out_err_kzalloc;
 768         }
 769
 770         platform_set_drvdata(pdev, info);
 771
 772         spin_lock_init(&info->controller.lock);
 773         init_waitqueue_head(&info->controller.wq);
 774
 775         info->device     = &pdev->dev;
 776         info->platform   = plat;
 777
 778         /* initialise chip data struct */
 779         chip = &info->chip;
 780
 781         if (plat->data_width)
 782                 chip->options |= NAND_BUSWIDTH_16;
 783
 784         chip->options |= NAND_CACHEPRG | NAND_SKIP_BBTSCAN;
 785
 786         chip->read_buf = (plat->data_width) ?
 787                 bf5xx_nand_read_buf16 : bf5xx_nand_read_buf;
 788         chip->write_buf = (plat->data_width) ?
 789                 bf5xx_nand_write_buf16 : bf5xx_nand_write_buf;
 790
 791         chip->read_byte    = bf5xx_nand_read_byte;
 792
 793         chip->cmd_ctrl     = bf5xx_nand_hwcontrol;
 794         chip->dev_ready    = bf5xx_nand_devready;
 795
 796         chip->priv         = &info->mtd;
 797         chip->controller   = &info->controller;
 798
 799         chip->IO_ADDR_R    = (void __iomem *) NFC_READ;
 800         chip->IO_ADDR_W    = (void __iomem *) NFC_DATA_WR;
 801
 802         chip->chip_delay   = 0;
 803
 804         /* initialise mtd info data struct */
 805         mtd             = &info->mtd;
 806         mtd->priv       = chip;
 807         mtd->owner      = THIS_MODULE;
 808
 809         /* initialise the hardware */
 810         err = bf5xx_nand_hw_init(info);
 811         if (err)
 812                 goto out_err_hw_init;
 813
 814         /* setup hardware ECC data struct */
 815         if (hardware_ecc) {
 816 #ifdef CONFIG_MTD_NAND_BF5XX_BOOTROM_ECC
 817                 chip->badblock_pattern = &bootrom_bbt;
 818                 chip->ecc.layout = &bootrom_ecclayout;
 819 #endif
 820                 chip->read_buf      = bf5xx_nand_dma_read_buf;
 821                 chip->write_buf     = bf5xx_nand_dma_write_buf;
 822                 chip->ecc.calculate = bf5xx_nand_calculate_ecc;
 823                 chip->ecc.correct   = bf5xx_nand_correct_data;
 824                 chip->ecc.mode      = NAND_ECC_HW;
 825                 chip->ecc.hwctl     = bf5xx_nand_enable_hwecc;
 826                 chip->ecc.read_page_raw = bf5xx_nand_read_page_raw;
 827                 chip->ecc.write_page_raw = bf5xx_nand_write_page_raw;
 828         } else {
 829                 chip->ecc.mode      = NAND_ECC_SOFT;
 830         }
 831
 832         /* scan hardware nand chip and setup mtd info data struct */
 833         if (bf5xx_nand_scan(mtd)) {
 834                 err = -ENXIO;
 835                 goto out_err_nand_scan;
 836         }
 837
 838         /* add NAND partition */
 839         bf5xx_nand_add_partition(info);
 840
 841         dev_dbg(&pdev->dev, "initialised ok\n");
 842         return 0;
 843
 844 out_err_nand_scan:
 845         bf5xx_nand_dma_remove(info);
 846 out_err_hw_init:
 847         platform_set_drvdata(pdev, NULL);
 848         kfree(info);
 849 out_err_kzalloc:
 850         peripheral_free_list(bfin_nfc_pin_req);
 851
 852         return err;
 853 }
 854
 855 /* PM Support */
 856 #ifdef CONFIG_PM
 857
 858 static int bf5xx_nand_suspend(struct platform_device *dev, pm_message_t pm)
 859 {
 860         struct bf5xx_nand_info *info = platform_get_drvdata(dev);
 861
 862         return 0;
 863 }
 864
 865 static int bf5xx_nand_resume(struct platform_device *dev)
 866 {
 867         struct bf5xx_nand_info *info = platform_get_drvdata(dev);
 868
 869         return 0;
 870 }
 871
 872 #else
 873 #define bf5xx_nand_suspend NULL
 874 #define bf5xx_nand_resume NULL
 875 #endif
 876
 877 /* driver device registration */
 878 static struct platform_driver bf5xx_nand_driver = {
 879         .probe          = bf5xx_nand_probe,
 880         .remove         = __devexit_p(bf5xx_nand_remove),
 881         .suspend        = bf5xx_nand_suspend,
 882         .resume         = bf5xx_nand_resume,
 883         .driver         = {
 884                 .name   = DRV_NAME,
 885                 .owner  = THIS_MODULE,
 886         },
 887 };
 888
 889 static int __init bf5xx_nand_init(void)
 890 {
 891         printk(KERN_INFO "%s, Version %s (c) 2007 Analog Devices, Inc.\n",
 892                 DRV_DESC, DRV_VERSION);
 893
 894         return platform_driver_register(&bf5xx_nand_driver);
 895 }
 896
 897 static void __exit bf5xx_nand_exit(void)
 898 {
 899         platform_driver_unregister(&bf5xx_nand_driver);
 900 }
 901
 902 module_init(bf5xx_nand_init);
 903 module_exit(bf5xx_nand_exit);
 904
 905 MODULE_LICENSE("GPL");
 906 MODULE_AUTHOR(DRV_AUTHOR);
 907 MODULE_DESCRIPTION(DRV_DESC);
 908 MODULE_ALIAS("platform:" DRV_NAME);