2 * MTD SPI driver for ST M25Pxx (and similar) serial flash chips
4 * Author: Mike Lavender, mike@steroidmicros.com
6 * Copyright (c) 2005, Intec Automation Inc.
8 * Some parts are based on lart.c by Abraham Van Der Merwe
10 * Cleaned up and generalized based on mtd_dataflash.c
12 * This code is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
18 #include <linux/init.h>
19 #include <linux/err.h>
20 #include <linux/errno.h>
21 #include <linux/module.h>
22 #include <linux/device.h>
23 #include <linux/interrupt.h>
24 #include <linux/mutex.h>
25 #include <linux/math64.h>
26 #include <linux/slab.h>
27 #include <linux/sched.h>
28 #include <linux/mod_devicetable.h>
30 #include <linux/mtd/cfi.h>
31 #include <linux/mtd/mtd.h>
32 #include <linux/mtd/partitions.h>
33 #include <linux/of_platform.h>
35 #include <linux/spi/spi.h>
36 #include <linux/spi/flash.h>
39 #define OPCODE_WREN 0x06 /* Write enable */
40 #define OPCODE_RDSR 0x05 /* Read status register */
41 #define OPCODE_WRSR 0x01 /* Write status register 1 byte */
42 #define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */
43 #define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */
44 #define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */
45 #define OPCODE_BE_4K 0x20 /* Erase 4KiB block */
46 #define OPCODE_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
47 #define OPCODE_BE_32K 0x52 /* Erase 32KiB block */
48 #define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */
49 #define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */
50 #define OPCODE_RDID 0x9f /* Read JEDEC ID */
52 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
53 #define OPCODE_NORM_READ_4B 0x13 /* Read data bytes (low frequency) */
54 #define OPCODE_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */
55 #define OPCODE_PP_4B 0x12 /* Page program (up to 256 bytes) */
56 #define OPCODE_SE_4B 0xdc /* Sector erase (usually 64KiB) */
58 /* Used for SST flashes only. */
59 #define OPCODE_BP 0x02 /* Byte program */
60 #define OPCODE_WRDI 0x04 /* Write disable */
61 #define OPCODE_AAI_WP 0xad /* Auto address increment word program */
63 /* Used for Macronix and Winbond flashes. */
64 #define OPCODE_EN4B 0xb7 /* Enter 4-byte mode */
65 #define OPCODE_EX4B 0xe9 /* Exit 4-byte mode */
67 /* Used for Spansion flashes only. */
68 #define OPCODE_BRWR 0x17 /* Bank register write */
70 /* Status Register bits. */
71 #define SR_WIP 1 /* Write in progress */
72 #define SR_WEL 2 /* Write enable latch */
73 /* meaning of other SR_* bits may differ between vendors */
74 #define SR_BP0 4 /* Block protect 0 */
75 #define SR_BP1 8 /* Block protect 1 */
76 #define SR_BP2 0x10 /* Block protect 2 */
77 #define SR_SRWD 0x80 /* SR write protect */
79 /* Define max times to check status register before we give up. */
80 #define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */
81 #define MAX_CMD_SIZE 6
83 #define JEDEC_MFR(_jedec_id) ((_jedec_id) >> 16)
85 /****************************************************************************/
88 struct spi_device *spi;
100 static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd)
102 return container_of(mtd, struct m25p, mtd);
105 /****************************************************************************/
108 * Internal helper functions
112 * Read the status register, returning its value in the location
113 * Return the status register value.
114 * Returns negative if error occurred.
116 static int read_sr(struct m25p *flash)
119 u8 code = OPCODE_RDSR;
122 retval = spi_write_then_read(flash->spi, &code, 1, &val, 1);
125 dev_err(&flash->spi->dev, "error %d reading SR\n",
134 * Write status register 1 byte
135 * Returns negative if error occurred.
137 static int write_sr(struct m25p *flash, u8 val)
139 flash->command[0] = OPCODE_WRSR;
140 flash->command[1] = val;
142 return spi_write(flash->spi, flash->command, 2);
146 * Set write enable latch with Write Enable command.
147 * Returns negative if error occurred.
149 static inline int write_enable(struct m25p *flash)
151 u8 code = OPCODE_WREN;
153 return spi_write_then_read(flash->spi, &code, 1, NULL, 0);
157 * Send write disble instruction to the chip.
159 static inline int write_disable(struct m25p *flash)
161 u8 code = OPCODE_WRDI;
163 return spi_write_then_read(flash->spi, &code, 1, NULL, 0);
167 * Enable/disable 4-byte addressing mode.
169 static inline int set_4byte(struct m25p *flash, u32 jedec_id, int enable)
172 bool need_wren = false;
174 switch (JEDEC_MFR(jedec_id)) {
175 case CFI_MFR_ST: /* Micron, actually */
176 /* Some Micron need WREN command; all will accept it */
178 case CFI_MFR_MACRONIX:
179 case 0xEF /* winbond */:
183 flash->command[0] = enable ? OPCODE_EN4B : OPCODE_EX4B;
184 status = spi_write(flash->spi, flash->command, 1);
187 write_disable(flash);
192 flash->command[0] = OPCODE_BRWR;
193 flash->command[1] = enable << 7;
194 return spi_write(flash->spi, flash->command, 2);
199 * Service routine to read status register until ready, or timeout occurs.
200 * Returns non-zero if error.
202 static int wait_till_ready(struct m25p *flash)
204 unsigned long deadline;
207 deadline = jiffies + MAX_READY_WAIT_JIFFIES;
210 if ((sr = read_sr(flash)) < 0)
212 else if (!(sr & SR_WIP))
217 } while (!time_after_eq(jiffies, deadline));
223 * Erase the whole flash memory
225 * Returns 0 if successful, non-zero otherwise.
227 static int erase_chip(struct m25p *flash)
229 pr_debug("%s: %s %lldKiB\n", dev_name(&flash->spi->dev), __func__,
230 (long long)(flash->mtd.size >> 10));
232 /* Wait until finished previous write command. */
233 if (wait_till_ready(flash))
236 /* Send write enable, then erase commands. */
239 /* Set up command buffer. */
240 flash->command[0] = OPCODE_CHIP_ERASE;
242 spi_write(flash->spi, flash->command, 1);
247 static void m25p_addr2cmd(struct m25p *flash, unsigned int addr, u8 *cmd)
249 /* opcode is in cmd[0] */
250 cmd[1] = addr >> (flash->addr_width * 8 - 8);
251 cmd[2] = addr >> (flash->addr_width * 8 - 16);
252 cmd[3] = addr >> (flash->addr_width * 8 - 24);
253 cmd[4] = addr >> (flash->addr_width * 8 - 32);
256 static int m25p_cmdsz(struct m25p *flash)
258 return 1 + flash->addr_width;
262 * Erase one sector of flash memory at offset ``offset'' which is any
263 * address within the sector which should be erased.
265 * Returns 0 if successful, non-zero otherwise.
267 static int erase_sector(struct m25p *flash, u32 offset)
269 pr_debug("%s: %s %dKiB at 0x%08x\n", dev_name(&flash->spi->dev),
270 __func__, flash->mtd.erasesize / 1024, offset);
272 /* Wait until finished previous write command. */
273 if (wait_till_ready(flash))
276 /* Send write enable, then erase commands. */
279 /* Set up command buffer. */
280 flash->command[0] = flash->erase_opcode;
281 m25p_addr2cmd(flash, offset, flash->command);
283 spi_write(flash->spi, flash->command, m25p_cmdsz(flash));
288 /****************************************************************************/
295 * Erase an address range on the flash chip. The address range may extend
296 * one or more erase sectors. Return an error is there is a problem erasing.
298 static int m25p80_erase(struct mtd_info *mtd, struct erase_info *instr)
300 struct m25p *flash = mtd_to_m25p(mtd);
304 pr_debug("%s: %s at 0x%llx, len %lld\n", dev_name(&flash->spi->dev),
305 __func__, (long long)instr->addr,
306 (long long)instr->len);
308 div_u64_rem(instr->len, mtd->erasesize, &rem);
315 mutex_lock(&flash->lock);
317 /* whole-chip erase? */
318 if (len == flash->mtd.size) {
319 if (erase_chip(flash)) {
320 instr->state = MTD_ERASE_FAILED;
321 mutex_unlock(&flash->lock);
325 /* REVISIT in some cases we could speed up erasing large regions
326 * by using OPCODE_SE instead of OPCODE_BE_4K. We may have set up
327 * to use "small sector erase", but that's not always optimal.
330 /* "sector"-at-a-time erase */
333 if (erase_sector(flash, addr)) {
334 instr->state = MTD_ERASE_FAILED;
335 mutex_unlock(&flash->lock);
339 addr += mtd->erasesize;
340 len -= mtd->erasesize;
344 mutex_unlock(&flash->lock);
346 instr->state = MTD_ERASE_DONE;
347 mtd_erase_callback(instr);
353 * Read an address range from the flash chip. The address range
354 * may be any size provided it is within the physical boundaries.
356 static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
357 size_t *retlen, u_char *buf)
359 struct m25p *flash = mtd_to_m25p(mtd);
360 struct spi_transfer t[2];
361 struct spi_message m;
364 pr_debug("%s: %s from 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
365 __func__, (u32)from, len);
367 spi_message_init(&m);
368 memset(t, 0, (sizeof t));
370 t[0].tx_buf = flash->command;
371 t[0].len = m25p_cmdsz(flash) + (flash->fast_read ? 1 : 0);
372 spi_message_add_tail(&t[0], &m);
376 spi_message_add_tail(&t[1], &m);
378 mutex_lock(&flash->lock);
380 /* Wait till previous write/erase is done. */
381 if (wait_till_ready(flash)) {
382 /* REVISIT status return?? */
383 mutex_unlock(&flash->lock);
387 /* Set up the write data buffer. */
388 opcode = flash->read_opcode;
389 flash->command[0] = opcode;
390 m25p_addr2cmd(flash, from, flash->command);
392 spi_sync(flash->spi, &m);
394 *retlen = m.actual_length - m25p_cmdsz(flash) -
395 (flash->fast_read ? 1 : 0);
397 mutex_unlock(&flash->lock);
403 * Write an address range to the flash chip. Data must be written in
404 * FLASH_PAGESIZE chunks. The address range may be any size provided
405 * it is within the physical boundaries.
407 static int m25p80_write(struct mtd_info *mtd, loff_t to, size_t len,
408 size_t *retlen, const u_char *buf)
410 struct m25p *flash = mtd_to_m25p(mtd);
411 u32 page_offset, page_size;
412 struct spi_transfer t[2];
413 struct spi_message m;
415 pr_debug("%s: %s to 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
416 __func__, (u32)to, len);
418 spi_message_init(&m);
419 memset(t, 0, (sizeof t));
421 t[0].tx_buf = flash->command;
422 t[0].len = m25p_cmdsz(flash);
423 spi_message_add_tail(&t[0], &m);
426 spi_message_add_tail(&t[1], &m);
428 mutex_lock(&flash->lock);
430 /* Wait until finished previous write command. */
431 if (wait_till_ready(flash)) {
432 mutex_unlock(&flash->lock);
438 /* Set up the opcode in the write buffer. */
439 flash->command[0] = flash->program_opcode;
440 m25p_addr2cmd(flash, to, flash->command);
442 page_offset = to & (flash->page_size - 1);
444 /* do all the bytes fit onto one page? */
445 if (page_offset + len <= flash->page_size) {
448 spi_sync(flash->spi, &m);
450 *retlen = m.actual_length - m25p_cmdsz(flash);
454 /* the size of data remaining on the first page */
455 page_size = flash->page_size - page_offset;
457 t[1].len = page_size;
458 spi_sync(flash->spi, &m);
460 *retlen = m.actual_length - m25p_cmdsz(flash);
462 /* write everything in flash->page_size chunks */
463 for (i = page_size; i < len; i += page_size) {
465 if (page_size > flash->page_size)
466 page_size = flash->page_size;
468 /* write the next page to flash */
469 m25p_addr2cmd(flash, to + i, flash->command);
471 t[1].tx_buf = buf + i;
472 t[1].len = page_size;
474 wait_till_ready(flash);
478 spi_sync(flash->spi, &m);
480 *retlen += m.actual_length - m25p_cmdsz(flash);
484 mutex_unlock(&flash->lock);
489 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
490 size_t *retlen, const u_char *buf)
492 struct m25p *flash = mtd_to_m25p(mtd);
493 struct spi_transfer t[2];
494 struct spi_message m;
498 pr_debug("%s: %s to 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
499 __func__, (u32)to, len);
501 spi_message_init(&m);
502 memset(t, 0, (sizeof t));
504 t[0].tx_buf = flash->command;
505 t[0].len = m25p_cmdsz(flash);
506 spi_message_add_tail(&t[0], &m);
509 spi_message_add_tail(&t[1], &m);
511 mutex_lock(&flash->lock);
513 /* Wait until finished previous write command. */
514 ret = wait_till_ready(flash);
521 /* Start write from odd address. */
523 flash->command[0] = OPCODE_BP;
524 m25p_addr2cmd(flash, to, flash->command);
526 /* write one byte. */
528 spi_sync(flash->spi, &m);
529 ret = wait_till_ready(flash);
532 *retlen += m.actual_length - m25p_cmdsz(flash);
536 flash->command[0] = OPCODE_AAI_WP;
537 m25p_addr2cmd(flash, to, flash->command);
539 /* Write out most of the data here. */
540 cmd_sz = m25p_cmdsz(flash);
541 for (; actual < len - 1; actual += 2) {
543 /* write two bytes. */
545 t[1].tx_buf = buf + actual;
547 spi_sync(flash->spi, &m);
548 ret = wait_till_ready(flash);
551 *retlen += m.actual_length - cmd_sz;
555 write_disable(flash);
556 ret = wait_till_ready(flash);
560 /* Write out trailing byte if it exists. */
563 flash->command[0] = OPCODE_BP;
564 m25p_addr2cmd(flash, to, flash->command);
565 t[0].len = m25p_cmdsz(flash);
567 t[1].tx_buf = buf + actual;
569 spi_sync(flash->spi, &m);
570 ret = wait_till_ready(flash);
573 *retlen += m.actual_length - m25p_cmdsz(flash);
574 write_disable(flash);
578 mutex_unlock(&flash->lock);
582 static int m25p80_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
584 struct m25p *flash = mtd_to_m25p(mtd);
585 uint32_t offset = ofs;
586 uint8_t status_old, status_new;
589 mutex_lock(&flash->lock);
590 /* Wait until finished previous command */
591 if (wait_till_ready(flash)) {
596 status_old = read_sr(flash);
598 if (offset < flash->mtd.size-(flash->mtd.size/2))
599 status_new = status_old | SR_BP2 | SR_BP1 | SR_BP0;
600 else if (offset < flash->mtd.size-(flash->mtd.size/4))
601 status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
602 else if (offset < flash->mtd.size-(flash->mtd.size/8))
603 status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
604 else if (offset < flash->mtd.size-(flash->mtd.size/16))
605 status_new = (status_old & ~(SR_BP0|SR_BP1)) | SR_BP2;
606 else if (offset < flash->mtd.size-(flash->mtd.size/32))
607 status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
608 else if (offset < flash->mtd.size-(flash->mtd.size/64))
609 status_new = (status_old & ~(SR_BP2|SR_BP0)) | SR_BP1;
611 status_new = (status_old & ~(SR_BP2|SR_BP1)) | SR_BP0;
613 /* Only modify protection if it will not unlock other areas */
614 if ((status_new&(SR_BP2|SR_BP1|SR_BP0)) >
615 (status_old&(SR_BP2|SR_BP1|SR_BP0))) {
617 if (write_sr(flash, status_new) < 0) {
623 err: mutex_unlock(&flash->lock);
627 static int m25p80_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
629 struct m25p *flash = mtd_to_m25p(mtd);
630 uint32_t offset = ofs;
631 uint8_t status_old, status_new;
634 mutex_lock(&flash->lock);
635 /* Wait until finished previous command */
636 if (wait_till_ready(flash)) {
641 status_old = read_sr(flash);
643 if (offset+len > flash->mtd.size-(flash->mtd.size/64))
644 status_new = status_old & ~(SR_BP2|SR_BP1|SR_BP0);
645 else if (offset+len > flash->mtd.size-(flash->mtd.size/32))
646 status_new = (status_old & ~(SR_BP2|SR_BP1)) | SR_BP0;
647 else if (offset+len > flash->mtd.size-(flash->mtd.size/16))
648 status_new = (status_old & ~(SR_BP2|SR_BP0)) | SR_BP1;
649 else if (offset+len > flash->mtd.size-(flash->mtd.size/8))
650 status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
651 else if (offset+len > flash->mtd.size-(flash->mtd.size/4))
652 status_new = (status_old & ~(SR_BP0|SR_BP1)) | SR_BP2;
653 else if (offset+len > flash->mtd.size-(flash->mtd.size/2))
654 status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
656 status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
658 /* Only modify protection if it will not lock other areas */
659 if ((status_new&(SR_BP2|SR_BP1|SR_BP0)) <
660 (status_old&(SR_BP2|SR_BP1|SR_BP0))) {
662 if (write_sr(flash, status_new) < 0) {
668 err: mutex_unlock(&flash->lock);
672 /****************************************************************************/
675 * SPI device driver setup and teardown
679 /* JEDEC id zero means "no ID" (most older chips); otherwise it has
680 * a high byte of zero plus three data bytes: the manufacturer id,
681 * then a two byte device id.
686 /* The size listed here is what works with OPCODE_SE, which isn't
687 * necessarily called a "sector" by the vendor.
689 unsigned sector_size;
696 #define SECT_4K 0x01 /* OPCODE_BE_4K works uniformly */
697 #define M25P_NO_ERASE 0x02 /* No erase command needed */
698 #define SST_WRITE 0x04 /* use SST byte programming */
699 #define M25P_NO_FR 0x08 /* Can't do fastread */
700 #define SECT_4K_PMC 0x10 /* OPCODE_BE_4K_PMC works uniformly */
703 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
704 ((kernel_ulong_t)&(struct flash_info) { \
705 .jedec_id = (_jedec_id), \
706 .ext_id = (_ext_id), \
707 .sector_size = (_sector_size), \
708 .n_sectors = (_n_sectors), \
713 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \
714 ((kernel_ulong_t)&(struct flash_info) { \
715 .sector_size = (_sector_size), \
716 .n_sectors = (_n_sectors), \
717 .page_size = (_page_size), \
718 .addr_width = (_addr_width), \
722 /* NOTE: double check command sets and memory organization when you add
723 * more flash chips. This current list focusses on newer chips, which
724 * have been converging on command sets which including JEDEC ID.
726 static const struct spi_device_id m25p_ids[] = {
727 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
728 { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
729 { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
731 { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
732 { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
733 { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
735 { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
736 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
737 { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
738 { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
740 { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
743 { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
744 { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
745 { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
746 { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
747 { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
748 { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
751 { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K) },
754 { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, M25P_NO_ERASE | M25P_NO_FR) },
755 { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, M25P_NO_ERASE | M25P_NO_FR) },
758 { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, SECT_4K) },
759 { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K) },
761 /* Intel/Numonyx -- xxxs33b */
762 { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
763 { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
764 { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
767 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
768 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
769 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
770 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
771 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) },
772 { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
773 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) },
774 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
775 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
776 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
777 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
778 { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, 0) },
781 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, 0) },
782 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, 0) },
783 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, 0) },
784 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K) },
785 { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K) },
788 { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
789 { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
790 { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) },
792 /* Spansion -- single (large) sector size only, at least
793 * for the chips listed here (without boot sectors).
795 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, 0) },
796 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, 0) },
797 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
798 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, 0) },
799 { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, 0) },
800 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
801 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
802 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
803 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) },
804 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 0) },
805 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
806 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
807 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
808 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
809 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
810 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) },
811 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
813 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
814 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
815 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
816 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
817 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
818 { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
819 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
820 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
821 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
822 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
824 /* ST Microelectronics -- newer production may have feature updates */
825 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
826 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
827 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
828 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
829 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
830 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
831 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
832 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
833 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
834 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, 0) },
836 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
837 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
838 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
839 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
840 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
841 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
842 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
843 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
844 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
846 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
847 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
848 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
850 { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) },
851 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
852 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
854 { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) },
855 { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) },
856 { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) },
857 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
859 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
860 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
861 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
862 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
863 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
864 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
865 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
866 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
867 { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K) },
868 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
869 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
870 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
871 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
872 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
873 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
874 { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) },
876 /* Catalyst / On Semiconductor -- non-JEDEC */
877 { "cat25c11", CAT25_INFO( 16, 8, 16, 1, M25P_NO_ERASE | M25P_NO_FR) },
878 { "cat25c03", CAT25_INFO( 32, 8, 16, 2, M25P_NO_ERASE | M25P_NO_FR) },
879 { "cat25c09", CAT25_INFO( 128, 8, 32, 2, M25P_NO_ERASE | M25P_NO_FR) },
880 { "cat25c17", CAT25_INFO( 256, 8, 32, 2, M25P_NO_ERASE | M25P_NO_FR) },
881 { "cat25128", CAT25_INFO(2048, 8, 64, 2, M25P_NO_ERASE | M25P_NO_FR) },
884 MODULE_DEVICE_TABLE(spi, m25p_ids);
886 static const struct spi_device_id *jedec_probe(struct spi_device *spi)
889 u8 code = OPCODE_RDID;
893 struct flash_info *info;
895 /* JEDEC also defines an optional "extended device information"
896 * string for after vendor-specific data, after the three bytes
897 * we use here. Supporting some chips might require using it.
899 tmp = spi_write_then_read(spi, &code, 1, id, 5);
901 pr_debug("%s: error %d reading JEDEC ID\n",
902 dev_name(&spi->dev), tmp);
911 ext_jedec = id[3] << 8 | id[4];
913 for (tmp = 0; tmp < ARRAY_SIZE(m25p_ids) - 1; tmp++) {
914 info = (void *)m25p_ids[tmp].driver_data;
915 if (info->jedec_id == jedec) {
916 if (info->ext_id != 0 && info->ext_id != ext_jedec)
918 return &m25p_ids[tmp];
921 dev_err(&spi->dev, "unrecognized JEDEC id %06x\n", jedec);
922 return ERR_PTR(-ENODEV);
927 * board specific setup should have ensured the SPI clock used here
928 * matches what the READ command supports, at least until this driver
929 * understands FAST_READ (for clocks over 25 MHz).
931 static int m25p_probe(struct spi_device *spi)
933 const struct spi_device_id *id = spi_get_device_id(spi);
934 struct flash_platform_data *data;
936 struct flash_info *info;
938 struct mtd_part_parser_data ppdata;
939 struct device_node *np = spi->dev.of_node;
941 /* Platform data helps sort out which chip type we have, as
942 * well as how this board partitions it. If we don't have
943 * a chip ID, try the JEDEC id commands; they'll work for most
944 * newer chips, even if we don't recognize the particular chip.
946 data = dev_get_platdata(&spi->dev);
947 if (data && data->type) {
948 const struct spi_device_id *plat_id;
950 for (i = 0; i < ARRAY_SIZE(m25p_ids) - 1; i++) {
951 plat_id = &m25p_ids[i];
952 if (strcmp(data->type, plat_id->name))
957 if (i < ARRAY_SIZE(m25p_ids) - 1)
960 dev_warn(&spi->dev, "unrecognized id %s\n", data->type);
963 info = (void *)id->driver_data;
965 if (info->jedec_id) {
966 const struct spi_device_id *jid;
968 jid = jedec_probe(spi);
971 } else if (jid != id) {
973 * JEDEC knows better, so overwrite platform ID. We
974 * can't trust partitions any longer, but we'll let
975 * mtd apply them anyway, since some partitions may be
976 * marked read-only, and we don't want to lose that
977 * information, even if it's not 100% accurate.
979 dev_warn(&spi->dev, "found %s, expected %s\n",
980 jid->name, id->name);
982 info = (void *)jid->driver_data;
986 flash = devm_kzalloc(&spi->dev, sizeof(*flash), GFP_KERNEL);
990 flash->command = devm_kzalloc(&spi->dev, MAX_CMD_SIZE, GFP_KERNEL);
995 mutex_init(&flash->lock);
996 spi_set_drvdata(spi, flash);
999 * Atmel, SST and Intel/Numonyx serial flash tend to power
1000 * up with the software protection bits set
1003 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ATMEL ||
1004 JEDEC_MFR(info->jedec_id) == CFI_MFR_INTEL ||
1005 JEDEC_MFR(info->jedec_id) == CFI_MFR_SST) {
1006 write_enable(flash);
1010 if (data && data->name)
1011 flash->mtd.name = data->name;
1013 flash->mtd.name = dev_name(&spi->dev);
1015 flash->mtd.type = MTD_NORFLASH;
1016 flash->mtd.writesize = 1;
1017 flash->mtd.flags = MTD_CAP_NORFLASH;
1018 flash->mtd.size = info->sector_size * info->n_sectors;
1019 flash->mtd._erase = m25p80_erase;
1020 flash->mtd._read = m25p80_read;
1022 /* flash protection support for STmicro chips */
1023 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ST) {
1024 flash->mtd._lock = m25p80_lock;
1025 flash->mtd._unlock = m25p80_unlock;
1028 /* sst flash chips use AAI word program */
1029 if (info->flags & SST_WRITE)
1030 flash->mtd._write = sst_write;
1032 flash->mtd._write = m25p80_write;
1034 /* prefer "small sector" erase if possible */
1035 if (info->flags & SECT_4K) {
1036 flash->erase_opcode = OPCODE_BE_4K;
1037 flash->mtd.erasesize = 4096;
1038 } else if (info->flags & SECT_4K_PMC) {
1039 flash->erase_opcode = OPCODE_BE_4K_PMC;
1040 flash->mtd.erasesize = 4096;
1042 flash->erase_opcode = OPCODE_SE;
1043 flash->mtd.erasesize = info->sector_size;
1046 if (info->flags & M25P_NO_ERASE)
1047 flash->mtd.flags |= MTD_NO_ERASE;
1049 ppdata.of_node = spi->dev.of_node;
1050 flash->mtd.dev.parent = &spi->dev;
1051 flash->page_size = info->page_size;
1052 flash->mtd.writebufsize = flash->page_size;
1055 /* If we were instantiated by DT, use it */
1056 flash->fast_read = of_property_read_bool(np, "m25p,fast-read");
1058 /* If we weren't instantiated by DT, default to fast-read */
1059 flash->fast_read = true;
1061 /* Some devices cannot do fast-read, no matter what DT tells us */
1062 if (info->flags & M25P_NO_FR)
1063 flash->fast_read = false;
1065 /* Default commands */
1066 if (flash->fast_read)
1067 flash->read_opcode = OPCODE_FAST_READ;
1069 flash->read_opcode = OPCODE_NORM_READ;
1071 flash->program_opcode = OPCODE_PP;
1073 if (info->addr_width)
1074 flash->addr_width = info->addr_width;
1075 else if (flash->mtd.size > 0x1000000) {
1076 /* enable 4-byte addressing if the device exceeds 16MiB */
1077 flash->addr_width = 4;
1078 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_AMD) {
1079 /* Dedicated 4-byte command set */
1080 flash->read_opcode = flash->fast_read ?
1081 OPCODE_FAST_READ_4B :
1082 OPCODE_NORM_READ_4B;
1083 flash->program_opcode = OPCODE_PP_4B;
1084 /* No small sector erase for 4-byte command set */
1085 flash->erase_opcode = OPCODE_SE_4B;
1086 flash->mtd.erasesize = info->sector_size;
1088 set_4byte(flash, info->jedec_id, 1);
1090 flash->addr_width = 3;
1093 dev_info(&spi->dev, "%s (%lld Kbytes)\n", id->name,
1094 (long long)flash->mtd.size >> 10);
1096 pr_debug("mtd .name = %s, .size = 0x%llx (%lldMiB) "
1097 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
1099 (long long)flash->mtd.size, (long long)(flash->mtd.size >> 20),
1100 flash->mtd.erasesize, flash->mtd.erasesize / 1024,
1101 flash->mtd.numeraseregions);
1103 if (flash->mtd.numeraseregions)
1104 for (i = 0; i < flash->mtd.numeraseregions; i++)
1105 pr_debug("mtd.eraseregions[%d] = { .offset = 0x%llx, "
1106 ".erasesize = 0x%.8x (%uKiB), "
1107 ".numblocks = %d }\n",
1108 i, (long long)flash->mtd.eraseregions[i].offset,
1109 flash->mtd.eraseregions[i].erasesize,
1110 flash->mtd.eraseregions[i].erasesize / 1024,
1111 flash->mtd.eraseregions[i].numblocks);
1114 /* partitions should match sector boundaries; and it may be good to
1115 * use readonly partitions for writeprotected sectors (BP2..BP0).
1117 return mtd_device_parse_register(&flash->mtd, NULL, &ppdata,
1118 data ? data->parts : NULL,
1119 data ? data->nr_parts : 0);
1123 static int m25p_remove(struct spi_device *spi)
1125 struct m25p *flash = spi_get_drvdata(spi);
1127 /* Clean up MTD stuff. */
1128 return mtd_device_unregister(&flash->mtd);
1132 static struct spi_driver m25p80_driver = {
1135 .owner = THIS_MODULE,
1137 .id_table = m25p_ids,
1138 .probe = m25p_probe,
1139 .remove = m25p_remove,
1141 /* REVISIT: many of these chips have deep power-down modes, which
1142 * should clearly be entered on suspend() to minimize power use.
1143 * And also when they're otherwise idle...
1147 module_spi_driver(m25p80_driver);
1149 MODULE_LICENSE("GPL");
1150 MODULE_AUTHOR("Mike Lavender");
1151 MODULE_DESCRIPTION("MTD SPI driver for ST M25Pxx flash chips");