drivers/mmc/zynq_sdhci.c

   1 /*
   2  * (C) Copyright 2013 - 2015 Xilinx, Inc.
   3  *
   4  * Xilinx Zynq SD Host Controller Interface
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <clk.h>
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <fdtdec.h>
  13 #include <libfdt.h>
  14 #include <malloc.h>
  15 #include <sdhci.h>
  16
  17 #ifndef CONFIG_ZYNQ_SDHCI_MIN_FREQ
  18 # define CONFIG_ZYNQ_SDHCI_MIN_FREQ     0
  19 #endif
  20
  21 struct arasan_sdhci_plat {
  22         struct mmc_config cfg;
  23         struct mmc mmc;
  24 };
  25
  26 static int arasan_sdhci_probe(struct udevice *dev)
  27 {
  28         struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
  29         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  30         struct sdhci_host *host = dev_get_priv(dev);
  31         struct clk clk;
  32         unsigned long clock;
  33         int ret;
  34
  35         ret = clk_get_by_index(dev, 0, &clk);
  36         if (ret < 0) {
  37                 dev_err(dev, "failed to get clock\n");
  38                 return ret;
  39         }
  40
  41         clock = clk_get_rate(&clk);
  42         if (IS_ERR_VALUE(clock)) {
  43                 dev_err(dev, "failed to get rate\n");
  44                 return clock;
  45         }
  46         debug("%s: CLK %ld\n", __func__, clock);
  47
  48         ret = clk_enable(&clk);
  49         if (ret && ret != -ENOSYS) {
  50                 dev_err(dev, "failed to enable clock\n");
  51                 return ret;
  52         }
  53
  54         host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
  55                        SDHCI_QUIRK_BROKEN_R1B;
  56
  57 #ifdef CONFIG_ZYNQ_HISPD_BROKEN
  58         host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
  59 #endif
  60
  61         host->max_clk = clock;
  62
  63         ret = sdhci_setup_cfg(&plat->cfg, host, CONFIG_ZYNQ_SDHCI_MAX_FREQ,
  64                               CONFIG_ZYNQ_SDHCI_MIN_FREQ);
  65         host->mmc = &plat->mmc;
  66         if (ret)
  67                 return ret;
  68         host->mmc->priv = host;
  69         host->mmc->dev = dev;
  70         upriv->mmc = host->mmc;
  71
  72         return sdhci_probe(dev);
  73 }
  74
  75 static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
  76 {
  77         struct sdhci_host *host = dev_get_priv(dev);
  78
  79         host->name = dev->name;
  80         host->ioaddr = (void *)dev_get_addr(dev);
  81
  82         return 0;
  83 }
  84
  85 static int arasan_sdhci_bind(struct udevice *dev)
  86 {
  87         struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
  88
  89         return sdhci_bind(dev, &plat->mmc, &plat->cfg);
  90 }
  91
  92 static const struct udevice_id arasan_sdhci_ids[] = {
  93         { .compatible = "arasan,sdhci-8.9a" },
  94         { }
  95 };
  96
  97 U_BOOT_DRIVER(arasan_sdhci_drv) = {
  98         .name           = "arasan_sdhci",
  99         .id             = UCLASS_MMC,
 100         .of_match       = arasan_sdhci_ids,
 101         .ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
 102         .ops            = &sdhci_ops,
 103         .bind           = arasan_sdhci_bind,
 104         .probe          = arasan_sdhci_probe,
 105         .priv_auto_alloc_size = sizeof(struct sdhci_host),
 106         .platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat),
 107 };