1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2013 - 2015 Xilinx, Inc.
5 * Xilinx Zynq SD Host Controller Interface
12 #include "mmc_private.h"
13 #include <linux/libfdt.h>
16 #include <zynqmp_tap_delay.h>
18 DECLARE_GLOBAL_DATA_PTR;
20 struct arasan_sdhci_plat {
21 struct mmc_config cfg;
26 struct arasan_sdhci_priv {
27 struct sdhci_host *host;
33 #if defined(CONFIG_ARCH_ZYNQMP)
34 #define MMC_HS200_BUS_SPEED 5
36 static const u8 mode2timing[] = {
37 [MMC_LEGACY] = UHS_SDR12_BUS_SPEED,
38 [SD_LEGACY] = UHS_SDR12_BUS_SPEED,
39 [MMC_HS] = HIGH_SPEED_BUS_SPEED,
40 [SD_HS] = HIGH_SPEED_BUS_SPEED,
41 [MMC_HS_52] = HIGH_SPEED_BUS_SPEED,
42 [MMC_DDR_52] = HIGH_SPEED_BUS_SPEED,
43 [UHS_SDR12] = UHS_SDR12_BUS_SPEED,
44 [UHS_SDR25] = UHS_SDR25_BUS_SPEED,
45 [UHS_SDR50] = UHS_SDR50_BUS_SPEED,
46 [UHS_DDR50] = UHS_DDR50_BUS_SPEED,
47 [UHS_SDR104] = UHS_SDR104_BUS_SPEED,
48 [MMC_HS_200] = MMC_HS200_BUS_SPEED,
51 #define SDHCI_HOST_CTRL2 0x3E
52 #define SDHCI_CTRL2_MODE_MASK 0x7
53 #define SDHCI_18V_SIGNAL 0x8
54 #define SDHCI_CTRL_EXEC_TUNING 0x0040
55 #define SDHCI_CTRL_TUNED_CLK 0x80
56 #define SDHCI_TUNING_LOOP_COUNT 40
58 static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 deviceid)
61 unsigned long timeout;
63 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
64 clk &= ~(SDHCI_CLOCK_CARD_EN);
65 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
68 zynqmp_dll_reset(deviceid);
72 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
73 & SDHCI_CLOCK_INT_STABLE)) {
75 dev_err(mmc_dev(host->mmc),
76 ": Internal clock never stabilised.\n");
83 clk |= SDHCI_CLOCK_CARD_EN;
84 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
87 static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
92 struct sdhci_host *host;
93 struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
94 char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
97 debug("%s\n", __func__);
100 deviceid = priv->deviceid;
102 ctrl = sdhci_readw(host, SDHCI_HOST_CTRL2);
103 ctrl |= SDHCI_CTRL_EXEC_TUNING;
104 sdhci_writew(host, ctrl, SDHCI_HOST_CTRL2);
108 arasan_zynqmp_dll_reset(host, deviceid);
110 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
111 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
115 cmd.resp_type = MMC_RSP_R1;
120 data.flags = MMC_DATA_READ;
122 if (tuning_loop_counter-- == 0)
125 if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200 &&
127 data.blocksize = 128;
129 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
132 sdhci_writew(host, data.blocks, SDHCI_BLOCK_COUNT);
133 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
135 mmc_send_cmd(mmc, &cmd, NULL);
136 ctrl = sdhci_readw(host, SDHCI_HOST_CTRL2);
138 if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
141 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
143 if (tuning_loop_counter < 0) {
144 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
145 sdhci_writel(host, ctrl, SDHCI_HOST_CTRL2);
148 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
149 printf("%s:Tuning failed\n", __func__);
154 arasan_zynqmp_dll_reset(host, deviceid);
156 /* Enable only interrupts served by the SD controller */
157 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
159 /* Mask all sdhci interrupt sources */
160 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
165 static void arasan_sdhci_set_tapdelay(struct sdhci_host *host)
167 struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
168 struct mmc *mmc = (struct mmc *)host->mmc;
171 uhsmode = mode2timing[mmc->selected_mode];
173 if (uhsmode >= UHS_SDR25_BUS_SPEED)
174 arasan_zynqmp_set_tapdelay(priv->deviceid, uhsmode,
178 static void arasan_sdhci_set_control_reg(struct sdhci_host *host)
180 struct mmc *mmc = (struct mmc *)host->mmc;
186 if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
187 reg = sdhci_readw(host, SDHCI_HOST_CTRL2);
188 reg |= SDHCI_18V_SIGNAL;
189 sdhci_writew(host, reg, SDHCI_HOST_CTRL2);
192 if (mmc->selected_mode > SD_HS &&
193 mmc->selected_mode <= UHS_DDR50) {
194 reg = sdhci_readw(host, SDHCI_HOST_CTRL2);
195 reg &= ~SDHCI_CTRL2_MODE_MASK;
196 switch (mmc->selected_mode) {
198 reg |= UHS_SDR12_BUS_SPEED;
201 reg |= UHS_SDR25_BUS_SPEED;
204 reg |= UHS_SDR50_BUS_SPEED;
207 reg |= UHS_SDR104_BUS_SPEED;
210 reg |= UHS_DDR50_BUS_SPEED;
215 sdhci_writew(host, reg, SDHCI_HOST_CTRL2);
220 #if defined(CONFIG_DM_MMC) && defined(CONFIG_ARCH_ZYNQMP)
221 const struct sdhci_ops arasan_ops = {
222 .platform_execute_tuning = &arasan_sdhci_execute_tuning,
223 .set_delay = &arasan_sdhci_set_tapdelay,
224 .set_control_reg = &arasan_sdhci_set_control_reg,
228 static int arasan_sdhci_probe(struct udevice *dev)
230 struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
231 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
232 struct arasan_sdhci_priv *priv = dev_get_priv(dev);
233 struct sdhci_host *host;
240 ret = clk_get_by_index(dev, 0, &clk);
242 dev_err(dev, "failed to get clock\n");
246 clock = clk_get_rate(&clk);
247 if (IS_ERR_VALUE(clock)) {
248 dev_err(dev, "failed to get rate\n");
252 debug("%s: CLK %ld\n", __func__, clock);
254 ret = clk_enable(&clk);
255 if (ret && ret != -ENOSYS) {
256 dev_err(dev, "failed to enable clock\n");
260 host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
261 SDHCI_QUIRK_BROKEN_R1B;
263 #ifdef CONFIG_ZYNQ_HISPD_BROKEN
264 host->quirks |= SDHCI_QUIRK_BROKEN_HISPD_MODE;
268 host->quirks |= SDHCI_QUIRK_NO_1_8_V;
270 host->max_clk = clock;
272 ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max,
273 CONFIG_ZYNQ_SDHCI_MIN_FREQ);
274 host->mmc = &plat->mmc;
277 host->mmc->priv = host;
278 host->mmc->dev = dev;
279 upriv->mmc = host->mmc;
281 return sdhci_probe(dev);
284 static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
286 struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
287 struct arasan_sdhci_priv *priv = dev_get_priv(dev);
289 priv->host = calloc(1, sizeof(struct sdhci_host));
293 priv->host->name = dev->name;
295 #if defined(CONFIG_DM_MMC) && defined(CONFIG_ARCH_ZYNQMP)
296 priv->host->ops = &arasan_ops;
299 priv->host->ioaddr = (void *)dev_read_addr(dev);
300 if (IS_ERR(priv->host->ioaddr))
301 return PTR_ERR(priv->host->ioaddr);
303 priv->deviceid = dev_read_u32_default(dev, "xlnx,device_id", -1);
304 priv->bank = dev_read_u32_default(dev, "xlnx,mio_bank", -1);
305 priv->no_1p8 = dev_read_bool(dev, "no-1-8-v");
307 plat->f_max = dev_read_u32_default(dev, "max-frequency",
308 CONFIG_ZYNQ_SDHCI_MAX_FREQ);
312 static int arasan_sdhci_bind(struct udevice *dev)
314 struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
316 return sdhci_bind(dev, &plat->mmc, &plat->cfg);
319 static const struct udevice_id arasan_sdhci_ids[] = {
320 { .compatible = "arasan,sdhci-8.9a" },
324 U_BOOT_DRIVER(arasan_sdhci_drv) = {
325 .name = "arasan_sdhci",
327 .of_match = arasan_sdhci_ids,
328 .ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
330 .bind = arasan_sdhci_bind,
331 .probe = arasan_sdhci_probe,
332 .priv_auto_alloc_size = sizeof(struct arasan_sdhci_priv),
333 .platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat),