1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2013 - 2015 Xilinx, Inc.
5 * Xilinx Zynq SD Host Controller Interface
12 #include <linux/delay.h>
13 #include "mmc_private.h"
15 #include <dm/device_compat.h>
16 #include <linux/err.h>
17 #include <linux/libfdt.h>
18 #include <asm/cache.h>
21 #include <zynqmp_firmware.h>
23 #define SDHCI_ARASAN_ITAPDLY_REGISTER 0xF0F8
24 #define SDHCI_ARASAN_ITAPDLY_SEL_MASK GENMASK(7, 0)
25 #define SDHCI_ARASAN_OTAPDLY_REGISTER 0xF0FC
26 #define SDHCI_ARASAN_OTAPDLY_SEL_MASK GENMASK(5, 0)
27 #define SDHCI_ITAPDLY_CHGWIN BIT(9)
28 #define SDHCI_ITAPDLY_ENABLE BIT(8)
29 #define SDHCI_OTAPDLY_ENABLE BIT(6)
31 #define SDHCI_TUNING_LOOP_COUNT 40
34 #define SD_DLL_CTRL 0xFF180358
35 #define SD_ITAP_DLY 0xFF180314
36 #define SD_OTAP_DLY 0xFF180318
37 #define SD0_DLL_RST BIT(2)
38 #define SD1_DLL_RST BIT(18)
39 #define SD0_ITAPCHGWIN BIT(9)
40 #define SD1_ITAPCHGWIN BIT(25)
41 #define SD0_ITAPDLYENA BIT(8)
42 #define SD1_ITAPDLYENA BIT(24)
43 #define SD0_ITAPDLYSEL_MASK GENMASK(7, 0)
44 #define SD1_ITAPDLYSEL_MASK GENMASK(23, 16)
45 #define SD0_OTAPDLYSEL_MASK GENMASK(5, 0)
46 #define SD1_OTAPDLYSEL_MASK GENMASK(21, 16)
48 struct arasan_sdhci_clk_data {
49 int clk_phase_in[MMC_TIMING_MMC_HS400 + 1];
50 int clk_phase_out[MMC_TIMING_MMC_HS400 + 1];
53 struct arasan_sdhci_plat {
54 struct mmc_config cfg;
58 struct arasan_sdhci_priv {
59 struct sdhci_host *host;
60 struct arasan_sdhci_clk_data clk_data;
66 /* For Versal platforms zynqmp_mmio_write() won't be available */
67 __weak int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value)
72 #if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL)
73 /* Default settings for ZynqMP Clock Phases */
74 static const u32 zynqmp_iclk_phases[] = {0, 63, 63, 0, 63, 0,
76 static const u32 zynqmp_oclk_phases[] = {0, 72, 60, 0, 60, 72,
79 /* Default settings for Versal Clock Phases */
80 static const u32 versal_iclk_phases[] = {0, 132, 132, 0, 132,
82 static const u32 versal_oclk_phases[] = {0, 60, 48, 0, 48, 72,
85 static const u8 mode2timing[] = {
86 [MMC_LEGACY] = MMC_TIMING_LEGACY,
87 [MMC_HS] = MMC_TIMING_MMC_HS,
88 [SD_HS] = MMC_TIMING_SD_HS,
89 [MMC_HS_52] = MMC_TIMING_UHS_SDR50,
90 [MMC_DDR_52] = MMC_TIMING_UHS_DDR50,
91 [UHS_SDR12] = MMC_TIMING_UHS_SDR12,
92 [UHS_SDR25] = MMC_TIMING_UHS_SDR25,
93 [UHS_SDR50] = MMC_TIMING_UHS_SDR50,
94 [UHS_DDR50] = MMC_TIMING_UHS_DDR50,
95 [UHS_SDR104] = MMC_TIMING_UHS_SDR104,
96 [MMC_HS_200] = MMC_TIMING_MMC_HS200,
99 static inline int arasan_zynqmp_set_in_tapdelay(u8 node_id, u32 itap_delay)
103 if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
104 if (node_id == NODE_SD_0) {
105 ret = zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN,
110 ret = zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA,
115 ret = zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK,
120 ret = zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN, 0);
124 ret = zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN,
129 ret = zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA,
134 ret = zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
139 ret = zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN, 0);
143 return xilinx_pm_request(PM_IOCTL, (u32)node_id,
144 IOCTL_SET_SD_TAPDELAY,
145 PM_TAPDELAY_INPUT, itap_delay, NULL);
151 static inline int arasan_zynqmp_set_out_tapdelay(u8 node_id, u32 otap_delay)
153 if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
154 if (node_id == NODE_SD_0)
155 return zynqmp_mmio_write(SD_OTAP_DLY,
159 return zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
162 return xilinx_pm_request(PM_IOCTL, (u32)node_id,
163 IOCTL_SET_SD_TAPDELAY,
164 PM_TAPDELAY_OUTPUT, otap_delay, NULL);
168 static inline int zynqmp_dll_reset(u8 node_id, u32 type)
170 if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
171 if (node_id == NODE_SD_0)
172 return zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST,
173 type == PM_DLL_RESET_ASSERT ?
176 return zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST,
177 type == PM_DLL_RESET_ASSERT ?
180 return xilinx_pm_request(PM_IOCTL, (u32)node_id,
181 IOCTL_SD_DLL_RESET, type, 0, NULL);
185 static int arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 node_id)
187 struct mmc *mmc = (struct mmc *)host->mmc;
188 struct udevice *dev = mmc->dev;
189 unsigned long timeout;
193 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
194 clk &= ~(SDHCI_CLOCK_CARD_EN);
195 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
197 /* Issue DLL Reset */
198 ret = zynqmp_dll_reset(node_id, PM_DLL_RESET_ASSERT);
200 dev_err(dev, "dll_reset assert failed with err: %d\n", ret);
204 /* Allow atleast 1ms delay for proper DLL reset */
206 ret = zynqmp_dll_reset(node_id, PM_DLL_RESET_RELEASE);
208 dev_err(dev, "dll_reset release failed with err: %d\n", ret);
214 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
215 & SDHCI_CLOCK_INT_STABLE)) {
217 dev_err(dev, ": Internal clock never stabilised.\n");
224 clk |= SDHCI_CLOCK_CARD_EN;
225 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
230 static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
233 struct mmc_data data;
235 struct sdhci_host *host;
236 struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
237 char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
238 u8 node_id = priv->deviceid ? NODE_SD_1 : NODE_SD_0;
240 debug("%s\n", __func__);
244 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
245 ctrl |= SDHCI_CTRL_EXEC_TUNING;
246 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
250 arasan_zynqmp_dll_reset(host, node_id);
252 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
253 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
257 cmd.resp_type = MMC_RSP_R1;
262 data.flags = MMC_DATA_READ;
264 if (tuning_loop_counter-- == 0)
267 if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200 &&
269 data.blocksize = 128;
271 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
274 sdhci_writew(host, data.blocks, SDHCI_BLOCK_COUNT);
275 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
277 mmc_send_cmd(mmc, &cmd, NULL);
278 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
280 if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
283 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
285 if (tuning_loop_counter < 0) {
286 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
287 sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL2);
290 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
291 printf("%s:Tuning failed\n", __func__);
296 arasan_zynqmp_dll_reset(host, node_id);
298 /* Enable only interrupts served by the SD controller */
299 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
301 /* Mask all sdhci interrupt sources */
302 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
308 * sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
310 * @host: Pointer to the sdhci_host structure.
311 * @degrees: The clock phase shift between 0 - 359.
314 * Set the SD Output Clock Tap Delays for Output path
316 static int sdhci_zynqmp_sdcardclk_set_phase(struct sdhci_host *host,
319 struct mmc *mmc = (struct mmc *)host->mmc;
320 struct udevice *dev = mmc->dev;
321 struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
322 u8 node_id = priv->deviceid ? NODE_SD_1 : NODE_SD_0;
323 u8 tap_delay, tap_max = 0;
324 int timing = mode2timing[mmc->selected_mode];
328 * This is applicable for SDHCI_SPEC_300 and above
329 * ZynqMP does not set phase for <=25MHz clock.
330 * If degrees is zero, no need to do anything.
332 if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
336 case MMC_TIMING_MMC_HS:
337 case MMC_TIMING_SD_HS:
338 case MMC_TIMING_UHS_SDR25:
339 case MMC_TIMING_UHS_DDR50:
340 case MMC_TIMING_MMC_DDR52:
341 /* For 50MHz clock, 30 Taps are available */
344 case MMC_TIMING_UHS_SDR50:
345 /* For 100MHz clock, 15 Taps are available */
348 case MMC_TIMING_UHS_SDR104:
349 case MMC_TIMING_MMC_HS200:
350 /* For 200MHz clock, 8 Taps are available */
356 tap_delay = (degrees * tap_max) / 360;
358 /* Limit output tap_delay value to 6 bits */
359 tap_delay &= SDHCI_ARASAN_OTAPDLY_SEL_MASK;
361 /* Set the Clock Phase */
362 ret = arasan_zynqmp_set_out_tapdelay(node_id, tap_delay);
364 dev_err(dev, "Error setting output Tap Delay\n");
368 /* Release DLL Reset */
369 ret = zynqmp_dll_reset(node_id, PM_DLL_RESET_RELEASE);
371 dev_err(dev, "dll_reset release failed with err: %d\n", ret);
379 * sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays
381 * @host: Pointer to the sdhci_host structure.
382 * @degrees: The clock phase shift between 0 - 359.
385 * Set the SD Input Clock Tap Delays for Input path
387 static int sdhci_zynqmp_sampleclk_set_phase(struct sdhci_host *host,
390 struct mmc *mmc = (struct mmc *)host->mmc;
391 struct udevice *dev = mmc->dev;
392 struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
393 u8 node_id = priv->deviceid ? NODE_SD_1 : NODE_SD_0;
394 u8 tap_delay, tap_max = 0;
395 int timing = mode2timing[mmc->selected_mode];
399 * This is applicable for SDHCI_SPEC_300 and above
400 * ZynqMP does not set phase for <=25MHz clock.
401 * If degrees is zero, no need to do anything.
403 if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
406 /* Assert DLL Reset */
407 ret = zynqmp_dll_reset(node_id, PM_DLL_RESET_ASSERT);
409 dev_err(dev, "dll_reset assert failed with err: %d\n", ret);
414 case MMC_TIMING_MMC_HS:
415 case MMC_TIMING_SD_HS:
416 case MMC_TIMING_UHS_SDR25:
417 case MMC_TIMING_UHS_DDR50:
418 case MMC_TIMING_MMC_DDR52:
419 /* For 50MHz clock, 120 Taps are available */
422 case MMC_TIMING_UHS_SDR50:
423 /* For 100MHz clock, 60 Taps are available */
426 case MMC_TIMING_UHS_SDR104:
427 case MMC_TIMING_MMC_HS200:
428 /* For 200MHz clock, 30 Taps are available */
434 tap_delay = (degrees * tap_max) / 360;
436 /* Limit input tap_delay value to 8 bits */
437 tap_delay &= SDHCI_ARASAN_ITAPDLY_SEL_MASK;
439 ret = arasan_zynqmp_set_in_tapdelay(node_id, tap_delay);
441 dev_err(dev, "Error setting Input Tap Delay\n");
449 * sdhci_versal_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
451 * @host: Pointer to the sdhci_host structure.
452 * @degrees: The clock phase shift between 0 - 359.
455 * Set the SD Output Clock Tap Delays for Output path
457 static int sdhci_versal_sdcardclk_set_phase(struct sdhci_host *host,
460 struct mmc *mmc = (struct mmc *)host->mmc;
461 u8 tap_delay, tap_max = 0;
462 int timing = mode2timing[mmc->selected_mode];
466 * This is applicable for SDHCI_SPEC_300 and above
467 * Versal does not set phase for <=25MHz clock.
468 * If degrees is zero, no need to do anything.
470 if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
474 case MMC_TIMING_MMC_HS:
475 case MMC_TIMING_SD_HS:
476 case MMC_TIMING_UHS_SDR25:
477 case MMC_TIMING_UHS_DDR50:
478 case MMC_TIMING_MMC_DDR52:
479 /* For 50MHz clock, 30 Taps are available */
482 case MMC_TIMING_UHS_SDR50:
483 /* For 100MHz clock, 15 Taps are available */
486 case MMC_TIMING_UHS_SDR104:
487 case MMC_TIMING_MMC_HS200:
488 /* For 200MHz clock, 8 Taps are available */
494 tap_delay = (degrees * tap_max) / 360;
496 /* Limit output tap_delay value to 6 bits */
497 tap_delay &= SDHCI_ARASAN_OTAPDLY_SEL_MASK;
499 /* Set the Clock Phase */
500 regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER);
501 regval |= SDHCI_OTAPDLY_ENABLE;
502 sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
503 regval &= ~SDHCI_ARASAN_OTAPDLY_SEL_MASK;
505 sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
511 * sdhci_versal_sampleclk_set_phase - Set the SD Input Clock Tap Delays
513 * @host: Pointer to the sdhci_host structure.
514 * @degrees: The clock phase shift between 0 - 359.
517 * Set the SD Input Clock Tap Delays for Input path
519 static int sdhci_versal_sampleclk_set_phase(struct sdhci_host *host,
522 struct mmc *mmc = (struct mmc *)host->mmc;
523 u8 tap_delay, tap_max = 0;
524 int timing = mode2timing[mmc->selected_mode];
528 * This is applicable for SDHCI_SPEC_300 and above
529 * Versal does not set phase for <=25MHz clock.
530 * If degrees is zero, no need to do anything.
532 if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
536 case MMC_TIMING_MMC_HS:
537 case MMC_TIMING_SD_HS:
538 case MMC_TIMING_UHS_SDR25:
539 case MMC_TIMING_UHS_DDR50:
540 case MMC_TIMING_MMC_DDR52:
541 /* For 50MHz clock, 120 Taps are available */
544 case MMC_TIMING_UHS_SDR50:
545 /* For 100MHz clock, 60 Taps are available */
548 case MMC_TIMING_UHS_SDR104:
549 case MMC_TIMING_MMC_HS200:
550 /* For 200MHz clock, 30 Taps are available */
556 tap_delay = (degrees * tap_max) / 360;
558 /* Limit input tap_delay value to 8 bits */
559 tap_delay &= SDHCI_ARASAN_ITAPDLY_SEL_MASK;
561 /* Set the Clock Phase */
562 regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER);
563 regval |= SDHCI_ITAPDLY_CHGWIN;
564 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
565 regval |= SDHCI_ITAPDLY_ENABLE;
566 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
567 regval &= ~SDHCI_ARASAN_ITAPDLY_SEL_MASK;
569 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
570 regval &= ~SDHCI_ITAPDLY_CHGWIN;
571 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
576 static int arasan_sdhci_set_tapdelay(struct sdhci_host *host)
578 struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
579 struct arasan_sdhci_clk_data *clk_data = &priv->clk_data;
580 struct mmc *mmc = (struct mmc *)host->mmc;
581 struct udevice *dev = mmc->dev;
582 u8 timing = mode2timing[mmc->selected_mode];
583 u32 iclk_phase = clk_data->clk_phase_in[timing];
584 u32 oclk_phase = clk_data->clk_phase_out[timing];
587 dev_dbg(dev, "%s, host:%s, mode:%d\n", __func__, host->name, timing);
589 if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) &&
590 device_is_compatible(dev, "xlnx,zynqmp-8.9a")) {
591 ret = sdhci_zynqmp_sampleclk_set_phase(host, iclk_phase);
595 ret = sdhci_zynqmp_sdcardclk_set_phase(host, oclk_phase);
598 } else if (IS_ENABLED(CONFIG_ARCH_VERSAL) &&
599 device_is_compatible(dev, "xlnx,versal-8.9a")) {
600 ret = sdhci_versal_sampleclk_set_phase(host, iclk_phase);
604 ret = sdhci_versal_sdcardclk_set_phase(host, oclk_phase);
612 static void arasan_dt_read_clk_phase(struct udevice *dev, unsigned char timing,
615 struct arasan_sdhci_priv *priv = dev_get_priv(dev);
616 struct arasan_sdhci_clk_data *clk_data = &priv->clk_data;
617 u32 clk_phase[2] = {0};
620 * Read Tap Delay values from DT, if the DT does not contain the
621 * Tap Values then use the pre-defined values
623 if (dev_read_u32_array(dev, prop, &clk_phase[0], 2)) {
624 dev_dbg(dev, "Using predefined clock phase for %s = %d %d\n",
625 prop, clk_data->clk_phase_in[timing],
626 clk_data->clk_phase_out[timing]);
630 /* The values read are Input and Output Clock Delays in order */
631 clk_data->clk_phase_in[timing] = clk_phase[0];
632 clk_data->clk_phase_out[timing] = clk_phase[1];
636 * arasan_dt_parse_clk_phases - Read Tap Delay values from DT
638 * @dev: Pointer to our struct udevice.
640 * Called at initialization to parse the values of Tap Delays.
642 static void arasan_dt_parse_clk_phases(struct udevice *dev)
644 struct arasan_sdhci_priv *priv = dev_get_priv(dev);
645 struct arasan_sdhci_clk_data *clk_data = &priv->clk_data;
648 if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) &&
649 device_is_compatible(dev, "xlnx,zynqmp-8.9a")) {
650 for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
651 clk_data->clk_phase_in[i] = zynqmp_iclk_phases[i];
652 clk_data->clk_phase_out[i] = zynqmp_oclk_phases[i];
655 if (priv->bank == MMC_BANK2) {
656 clk_data->clk_phase_out[MMC_TIMING_UHS_SDR104] = 90;
657 clk_data->clk_phase_out[MMC_TIMING_MMC_HS200] = 90;
661 if (IS_ENABLED(CONFIG_ARCH_VERSAL) &&
662 device_is_compatible(dev, "xlnx,versal-8.9a")) {
663 for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
664 clk_data->clk_phase_in[i] = versal_iclk_phases[i];
665 clk_data->clk_phase_out[i] = versal_oclk_phases[i];
669 arasan_dt_read_clk_phase(dev, MMC_TIMING_LEGACY,
671 arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_HS,
673 arasan_dt_read_clk_phase(dev, MMC_TIMING_SD_HS,
675 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR12,
676 "clk-phase-uhs-sdr12");
677 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR25,
678 "clk-phase-uhs-sdr25");
679 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR50,
680 "clk-phase-uhs-sdr50");
681 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR104,
682 "clk-phase-uhs-sdr104");
683 arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_DDR50,
684 "clk-phase-uhs-ddr50");
685 arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_DDR52,
686 "clk-phase-mmc-ddr52");
687 arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_HS200,
688 "clk-phase-mmc-hs200");
689 arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_HS400,
690 "clk-phase-mmc-hs400");
693 static void arasan_sdhci_set_control_reg(struct sdhci_host *host)
695 struct mmc *mmc = (struct mmc *)host->mmc;
701 if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
702 reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
703 reg |= SDHCI_CTRL_VDD_180;
704 sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
707 if (mmc->selected_mode > SD_HS &&
708 mmc->selected_mode <= MMC_HS_200)
709 sdhci_set_uhs_timing(host);
712 static const struct sdhci_ops arasan_ops = {
713 .platform_execute_tuning = &arasan_sdhci_execute_tuning,
714 .set_delay = &arasan_sdhci_set_tapdelay,
715 .set_control_reg = &arasan_sdhci_set_control_reg,
719 static int arasan_sdhci_probe(struct udevice *dev)
721 struct arasan_sdhci_plat *plat = dev_get_plat(dev);
722 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
723 struct arasan_sdhci_priv *priv = dev_get_priv(dev);
724 struct sdhci_host *host;
731 ret = clk_get_by_index(dev, 0, &clk);
733 dev_err(dev, "failed to get clock\n");
737 clock = clk_get_rate(&clk);
738 if (IS_ERR_VALUE(clock)) {
739 dev_err(dev, "failed to get rate\n");
743 debug("%s: CLK %ld\n", __func__, clock);
745 ret = clk_enable(&clk);
747 dev_err(dev, "failed to enable clock\n");
751 host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
752 SDHCI_QUIRK_BROKEN_R1B;
754 #ifdef CONFIG_ZYNQ_HISPD_BROKEN
755 host->quirks |= SDHCI_QUIRK_BROKEN_HISPD_MODE;
759 host->quirks |= SDHCI_QUIRK_NO_1_8_V;
761 plat->cfg.f_max = CONFIG_ZYNQ_SDHCI_MAX_FREQ;
763 ret = mmc_of_parse(dev, &plat->cfg);
767 host->max_clk = clock;
769 host->mmc = &plat->mmc;
770 host->mmc->dev = dev;
771 host->mmc->priv = host;
773 ret = sdhci_setup_cfg(&plat->cfg, host, plat->cfg.f_max,
774 CONFIG_ZYNQ_SDHCI_MIN_FREQ);
777 upriv->mmc = host->mmc;
780 * WORKAROUND: Versal platforms have an issue with card detect state.
781 * Due to this, host controller is switching off voltage to sd card
782 * causing sd card timeout error. Workaround this by adding a wait for
783 * 1000msec till the card detect state gets stable.
785 if (IS_ENABLED(CONFIG_ARCH_VERSAL)) {
788 while (((sdhci_readl(host, SDHCI_PRESENT_STATE) &
789 SDHCI_CARD_STATE_STABLE) == 0) && timeout--) {
793 dev_err(dev, "Sdhci card detect state not stable\n");
798 return sdhci_probe(dev);
801 static int arasan_sdhci_of_to_plat(struct udevice *dev)
803 struct arasan_sdhci_priv *priv = dev_get_priv(dev);
805 priv->host = calloc(1, sizeof(struct sdhci_host));
809 priv->host->name = dev->name;
811 #if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL)
812 priv->host->ops = &arasan_ops;
813 arasan_dt_parse_clk_phases(dev);
816 priv->host->ioaddr = (void *)dev_read_addr(dev);
817 if (IS_ERR(priv->host->ioaddr))
818 return PTR_ERR(priv->host->ioaddr);
820 priv->deviceid = dev_read_u32_default(dev, "xlnx,device_id", -1);
821 priv->bank = dev_read_u32_default(dev, "xlnx,mio-bank", 0);
822 priv->no_1p8 = dev_read_bool(dev, "no-1-8-v");
827 static int arasan_sdhci_bind(struct udevice *dev)
829 struct arasan_sdhci_plat *plat = dev_get_plat(dev);
831 return sdhci_bind(dev, &plat->mmc, &plat->cfg);
834 static const struct udevice_id arasan_sdhci_ids[] = {
835 { .compatible = "arasan,sdhci-8.9a" },
839 U_BOOT_DRIVER(arasan_sdhci_drv) = {
840 .name = "arasan_sdhci",
842 .of_match = arasan_sdhci_ids,
843 .of_to_plat = arasan_sdhci_of_to_plat,
845 .bind = arasan_sdhci_bind,
846 .probe = arasan_sdhci_probe,
847 .priv_auto = sizeof(struct arasan_sdhci_priv),
848 .plat_auto = sizeof(struct arasan_sdhci_plat),