mmc: zynq: Fix tuning_loop_counter type in arasan_sdhci_execute_tuning()
[platform/kernel/u-boot.git] / drivers / mmc / zynq_sdhci.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2013 - 2015 Xilinx, Inc.
4  *
5  * Xilinx Zynq SD Host Controller Interface
6  */
7
8 #include <clk.h>
9 #include <common.h>
10 #include <dm.h>
11 #include <fdtdec.h>
12 #include "mmc_private.h"
13 #include <linux/libfdt.h>
14 #include <malloc.h>
15 #include <sdhci.h>
16 #include <zynqmp_tap_delay.h>
17
18 DECLARE_GLOBAL_DATA_PTR;
19
20 struct arasan_sdhci_plat {
21         struct mmc_config cfg;
22         struct mmc mmc;
23         unsigned int f_max;
24 };
25
26 struct arasan_sdhci_priv {
27         struct sdhci_host *host;
28         u8 deviceid;
29         u8 bank;
30         u8 no_1p8;
31         bool pwrseq;
32 };
33
34 #if defined(CONFIG_ARCH_ZYNQMP)
35 #define MMC_HS200_BUS_SPEED     5
36
37 static const u8 mode2timing[] = {
38         [MMC_LEGACY] = UHS_SDR12_BUS_SPEED,
39         [SD_LEGACY] = UHS_SDR12_BUS_SPEED,
40         [MMC_HS] = HIGH_SPEED_BUS_SPEED,
41         [SD_HS] = HIGH_SPEED_BUS_SPEED,
42         [MMC_HS_52] = HIGH_SPEED_BUS_SPEED,
43         [MMC_DDR_52] = HIGH_SPEED_BUS_SPEED,
44         [UHS_SDR12] = UHS_SDR12_BUS_SPEED,
45         [UHS_SDR25] = UHS_SDR25_BUS_SPEED,
46         [UHS_SDR50] = UHS_SDR50_BUS_SPEED,
47         [UHS_DDR50] = UHS_DDR50_BUS_SPEED,
48         [UHS_SDR104] = UHS_SDR104_BUS_SPEED,
49         [MMC_HS_200] = MMC_HS200_BUS_SPEED,
50 };
51
52 #define SDHCI_HOST_CTRL2        0x3E
53 #define SDHCI_CTRL2_MODE_MASK   0x7
54 #define SDHCI_18V_SIGNAL        0x8
55 #define SDHCI_CTRL_EXEC_TUNING  0x0040
56 #define SDHCI_CTRL_TUNED_CLK    0x80
57 #define SDHCI_TUNING_LOOP_COUNT 40
58
59 static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 deviceid)
60 {
61         u16 clk;
62         unsigned long timeout;
63
64         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
65         clk &= ~(SDHCI_CLOCK_CARD_EN);
66         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
67
68         /* Issue DLL Reset */
69         zynqmp_dll_reset(deviceid);
70
71         /* Wait max 20 ms */
72         timeout = 100;
73         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
74                                 & SDHCI_CLOCK_INT_STABLE)) {
75                 if (timeout == 0) {
76                         dev_err(mmc_dev(host->mmc),
77                                 ": Internal clock never stabilised.\n");
78                         return;
79                 }
80                 timeout--;
81                 udelay(1000);
82         }
83
84         clk |= SDHCI_CLOCK_CARD_EN;
85         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
86 }
87
88 static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
89 {
90         struct mmc_cmd cmd;
91         struct mmc_data data;
92         u32 ctrl;
93         struct sdhci_host *host;
94         struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
95         char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
96         u8 deviceid;
97
98         debug("%s\n", __func__);
99
100         host = priv->host;
101         deviceid = priv->deviceid;
102
103         ctrl = sdhci_readw(host, SDHCI_HOST_CTRL2);
104         ctrl |= SDHCI_CTRL_EXEC_TUNING;
105         sdhci_writew(host, ctrl, SDHCI_HOST_CTRL2);
106
107         mdelay(1);
108
109         arasan_zynqmp_dll_reset(host, deviceid);
110
111         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
112         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
113
114         do {
115                 cmd.cmdidx = opcode;
116                 cmd.resp_type = MMC_RSP_R1;
117                 cmd.cmdarg = 0;
118
119                 data.blocksize = 64;
120                 data.blocks = 1;
121                 data.flags = MMC_DATA_READ;
122
123                 if (tuning_loop_counter-- == 0)
124                         break;
125
126                 if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200 &&
127                     mmc->bus_width == 8)
128                         data.blocksize = 128;
129
130                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
131                                                     data.blocksize),
132                              SDHCI_BLOCK_SIZE);
133                 sdhci_writew(host, data.blocks, SDHCI_BLOCK_COUNT);
134                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
135
136                 mmc_send_cmd(mmc, &cmd, NULL);
137                 ctrl = sdhci_readw(host, SDHCI_HOST_CTRL2);
138
139                 if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
140                         udelay(1);
141
142         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
143
144         if (tuning_loop_counter < 0) {
145                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
146                 sdhci_writel(host, ctrl, SDHCI_HOST_CTRL2);
147         }
148
149         if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
150                 printf("%s:Tuning failed\n", __func__);
151                 return -1;
152         }
153
154         udelay(1);
155         arasan_zynqmp_dll_reset(host, deviceid);
156
157         /* Enable only interrupts served by the SD controller */
158         sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
159                      SDHCI_INT_ENABLE);
160         /* Mask all sdhci interrupt sources */
161         sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
162
163         return 0;
164 }
165
166 static void arasan_sdhci_set_tapdelay(struct sdhci_host *host)
167 {
168         struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
169         struct mmc *mmc = (struct mmc *)host->mmc;
170         u8 uhsmode;
171
172         uhsmode = mode2timing[mmc->selected_mode];
173
174         if (uhsmode >= UHS_SDR25_BUS_SPEED)
175                 arasan_zynqmp_set_tapdelay(priv->deviceid, uhsmode,
176                                            priv->bank);
177 }
178
179 static void arasan_sdhci_set_control_reg(struct sdhci_host *host)
180 {
181         struct mmc *mmc = (struct mmc *)host->mmc;
182         u32 reg;
183
184         if (!IS_SD(mmc))
185                 return;
186
187         if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
188                 reg = sdhci_readw(host, SDHCI_HOST_CTRL2);
189                 reg |= SDHCI_18V_SIGNAL;
190                 sdhci_writew(host, reg, SDHCI_HOST_CTRL2);
191         }
192
193         if (mmc->selected_mode > SD_HS &&
194             mmc->selected_mode <= UHS_DDR50) {
195                 reg = sdhci_readw(host, SDHCI_HOST_CTRL2);
196                 reg &= ~SDHCI_CTRL2_MODE_MASK;
197                 switch (mmc->selected_mode) {
198                 case UHS_SDR12:
199                         reg |= UHS_SDR12_BUS_SPEED;
200                         break;
201                 case UHS_SDR25:
202                         reg |= UHS_SDR25_BUS_SPEED;
203                         break;
204                 case UHS_SDR50:
205                         reg |= UHS_SDR50_BUS_SPEED;
206                         break;
207                 case UHS_SDR104:
208                         reg |= UHS_SDR104_BUS_SPEED;
209                         break;
210                 case UHS_DDR50:
211                         reg |= UHS_DDR50_BUS_SPEED;
212                         break;
213                 default:
214                         break;
215                 }
216                 sdhci_writew(host, reg, SDHCI_HOST_CTRL2);
217         }
218 }
219 #endif
220
221 #if defined(CONFIG_DM_MMC) && defined(CONFIG_ARCH_ZYNQMP)
222 const struct sdhci_ops arasan_ops = {
223         .platform_execute_tuning        = &arasan_sdhci_execute_tuning,
224         .set_delay = &arasan_sdhci_set_tapdelay,
225         .set_control_reg = &arasan_sdhci_set_control_reg,
226 };
227 #endif
228
229 static int arasan_sdhci_probe(struct udevice *dev)
230 {
231         struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
232         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
233         struct arasan_sdhci_priv *priv = dev_get_priv(dev);
234         struct sdhci_host *host;
235         struct clk clk;
236         unsigned long clock;
237         int ret;
238
239         host = priv->host;
240
241         ret = clk_get_by_index(dev, 0, &clk);
242         if (ret < 0) {
243                 dev_err(dev, "failed to get clock\n");
244                 return ret;
245         }
246
247         clock = clk_get_rate(&clk);
248         if (IS_ERR_VALUE(clock)) {
249                 dev_err(dev, "failed to get rate\n");
250                 return clock;
251         }
252
253         debug("%s: CLK %ld\n", __func__, clock);
254
255         ret = clk_enable(&clk);
256         if (ret && ret != -ENOSYS) {
257                 dev_err(dev, "failed to enable clock\n");
258                 return ret;
259         }
260
261         host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
262                        SDHCI_QUIRK_BROKEN_R1B;
263
264 #ifdef CONFIG_ZYNQ_HISPD_BROKEN
265         host->quirks |= SDHCI_QUIRK_BROKEN_HISPD_MODE;
266 #endif
267
268         if (priv->no_1p8)
269                 host->quirks |= SDHCI_QUIRK_NO_1_8_V;
270
271         host->max_clk = clock;
272
273         ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max,
274                               CONFIG_ZYNQ_SDHCI_MIN_FREQ);
275         host->mmc = &plat->mmc;
276         if (ret)
277                 return ret;
278         host->mmc->priv = host;
279         host->mmc->dev = dev;
280         upriv->mmc = host->mmc;
281
282         return sdhci_probe(dev);
283 }
284
285 static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
286 {
287         struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
288         struct arasan_sdhci_priv *priv = dev_get_priv(dev);
289
290         priv->host = calloc(1, sizeof(struct sdhci_host));
291         if (!priv->host)
292                 return -1;
293
294         priv->host->name = dev->name;
295
296 #if defined(CONFIG_DM_MMC) && defined(CONFIG_ARCH_ZYNQMP)
297         priv->host->ops = &arasan_ops;
298 #endif
299
300         priv->host->ioaddr = (void *)dev_read_addr(dev);
301         if (IS_ERR(priv->host->ioaddr))
302                 return PTR_ERR(priv->host->ioaddr);
303
304         priv->deviceid = dev_read_u32_default(dev, "xlnx,device_id", -1);
305         priv->bank = dev_read_u32_default(dev, "xlnx,mio_bank", -1);
306         priv->no_1p8 = dev_read_bool(dev, "no-1-8-v");
307
308         plat->f_max = dev_read_u32_default(dev, "max-frequency",
309                                            CONFIG_ZYNQ_SDHCI_MAX_FREQ);
310         return 0;
311 }
312
313 static int arasan_sdhci_bind(struct udevice *dev)
314 {
315         struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
316
317         return sdhci_bind(dev, &plat->mmc, &plat->cfg);
318 }
319
320 static const struct udevice_id arasan_sdhci_ids[] = {
321         { .compatible = "arasan,sdhci-8.9a" },
322         { }
323 };
324
325 U_BOOT_DRIVER(arasan_sdhci_drv) = {
326         .name           = "arasan_sdhci",
327         .id             = UCLASS_MMC,
328         .of_match       = arasan_sdhci_ids,
329         .ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
330         .ops            = &sdhci_ops,
331         .bind           = arasan_sdhci_bind,
332         .probe          = arasan_sdhci_probe,
333         .priv_auto_alloc_size = sizeof(struct arasan_sdhci_priv),
334         .platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat),
335 };