drivers/mmc/zynq_sdhci.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2013 - 2015 Xilinx, Inc.
   4  *
   5  * Xilinx Zynq SD Host Controller Interface
   6  */
   7
   8 #include <clk.h>
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <fdtdec.h>
  12 #include "mmc_private.h"
  13 #include <dm/device_compat.h>
  14 #include <linux/err.h>
  15 #include <linux/libfdt.h>
  16 #include <malloc.h>
  17 #include <sdhci.h>
  18 #include <zynqmp_tap_delay.h>
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 struct arasan_sdhci_plat {
  23         struct mmc_config cfg;
  24         struct mmc mmc;
  25         unsigned int f_max;
  26 };
  27
  28 struct arasan_sdhci_priv {
  29         struct sdhci_host *host;
  30         u8 deviceid;
  31         u8 bank;
  32         u8 no_1p8;
  33 };
  34
  35 #if defined(CONFIG_ARCH_ZYNQMP)
  36 #define MMC_HS200_BUS_SPEED     5
  37
  38 static const u8 mode2timing[] = {
  39         [MMC_LEGACY] = UHS_SDR12_BUS_SPEED,
  40         [SD_LEGACY] = UHS_SDR12_BUS_SPEED,
  41         [MMC_HS] = HIGH_SPEED_BUS_SPEED,
  42         [SD_HS] = HIGH_SPEED_BUS_SPEED,
  43         [MMC_HS_52] = HIGH_SPEED_BUS_SPEED,
  44         [MMC_DDR_52] = HIGH_SPEED_BUS_SPEED,
  45         [UHS_SDR12] = UHS_SDR12_BUS_SPEED,
  46         [UHS_SDR25] = UHS_SDR25_BUS_SPEED,
  47         [UHS_SDR50] = UHS_SDR50_BUS_SPEED,
  48         [UHS_DDR50] = UHS_DDR50_BUS_SPEED,
  49         [UHS_SDR104] = UHS_SDR104_BUS_SPEED,
  50         [MMC_HS_200] = MMC_HS200_BUS_SPEED,
  51 };
  52
  53 #define SDHCI_TUNING_LOOP_COUNT 40
  54
  55 static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 deviceid)
  56 {
  57         u16 clk;
  58         unsigned long timeout;
  59
  60         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
  61         clk &= ~(SDHCI_CLOCK_CARD_EN);
  62         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  63
  64         /* Issue DLL Reset */
  65         zynqmp_dll_reset(deviceid);
  66
  67         /* Wait max 20 ms */
  68         timeout = 100;
  69         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
  70                                 & SDHCI_CLOCK_INT_STABLE)) {
  71                 if (timeout == 0) {
  72                         dev_err(mmc_dev(host->mmc),
  73                                 ": Internal clock never stabilised.\n");
  74                         return;
  75                 }
  76                 timeout--;
  77                 udelay(1000);
  78         }
  79
  80         clk |= SDHCI_CLOCK_CARD_EN;
  81         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  82 }
  83
  84 static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
  85 {
  86         struct mmc_cmd cmd;
  87         struct mmc_data data;
  88         u32 ctrl;
  89         struct sdhci_host *host;
  90         struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
  91         char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
  92         u8 deviceid;
  93
  94         debug("%s\n", __func__);
  95
  96         host = priv->host;
  97         deviceid = priv->deviceid;
  98
  99         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 100         ctrl |= SDHCI_CTRL_EXEC_TUNING;
 101         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
 102
 103         mdelay(1);
 104
 105         arasan_zynqmp_dll_reset(host, deviceid);
 106
 107         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
 108         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
 109
 110         do {
 111                 cmd.cmdidx = opcode;
 112                 cmd.resp_type = MMC_RSP_R1;
 113                 cmd.cmdarg = 0;
 114
 115                 data.blocksize = 64;
 116                 data.blocks = 1;
 117                 data.flags = MMC_DATA_READ;
 118
 119                 if (tuning_loop_counter-- == 0)
 120                         break;
 121
 122                 if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200 &&
 123                     mmc->bus_width == 8)
 124                         data.blocksize = 128;
 125
 126                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 127                                                     data.blocksize),
 128                              SDHCI_BLOCK_SIZE);
 129                 sdhci_writew(host, data.blocks, SDHCI_BLOCK_COUNT);
 130                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
 131
 132                 mmc_send_cmd(mmc, &cmd, NULL);
 133                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 134
 135                 if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
 136                         udelay(1);
 137
 138         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
 139
 140         if (tuning_loop_counter < 0) {
 141                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
 142                 sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL2);
 143         }
 144
 145         if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
 146                 printf("%s:Tuning failed\n", __func__);
 147                 return -1;
 148         }
 149
 150         udelay(1);
 151         arasan_zynqmp_dll_reset(host, deviceid);
 152
 153         /* Enable only interrupts served by the SD controller */
 154         sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
 155                      SDHCI_INT_ENABLE);
 156         /* Mask all sdhci interrupt sources */
 157         sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
 158
 159         return 0;
 160 }
 161
 162 static void arasan_sdhci_set_tapdelay(struct sdhci_host *host)
 163 {
 164         struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
 165         struct mmc *mmc = (struct mmc *)host->mmc;
 166         u8 uhsmode;
 167
 168         uhsmode = mode2timing[mmc->selected_mode];
 169
 170         if (uhsmode >= UHS_SDR25_BUS_SPEED)
 171                 arasan_zynqmp_set_tapdelay(priv->deviceid, uhsmode,
 172                                            priv->bank);
 173 }
 174
 175 static void arasan_sdhci_set_control_reg(struct sdhci_host *host)
 176 {
 177         struct mmc *mmc = (struct mmc *)host->mmc;
 178         u32 reg;
 179
 180         if (!IS_SD(mmc))
 181                 return;
 182
 183         if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
 184                 reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 185                 reg |= SDHCI_CTRL_VDD_180;
 186                 sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
 187         }
 188
 189         if (mmc->selected_mode > SD_HS &&
 190             mmc->selected_mode <= UHS_DDR50)
 191                 sdhci_set_uhs_timing(host);
 192 }
 193 #endif
 194
 195 #if defined(CONFIG_ARCH_ZYNQMP)
 196 const struct sdhci_ops arasan_ops = {
 197         .platform_execute_tuning        = &arasan_sdhci_execute_tuning,
 198         .set_delay = &arasan_sdhci_set_tapdelay,
 199         .set_control_reg = &arasan_sdhci_set_control_reg,
 200 };
 201 #endif
 202
 203 static int arasan_sdhci_probe(struct udevice *dev)
 204 {
 205         struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
 206         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 207         struct arasan_sdhci_priv *priv = dev_get_priv(dev);
 208         struct sdhci_host *host;
 209         struct clk clk;
 210         unsigned long clock;
 211         int ret;
 212
 213         host = priv->host;
 214
 215         ret = clk_get_by_index(dev, 0, &clk);
 216         if (ret < 0) {
 217                 dev_err(dev, "failed to get clock\n");
 218                 return ret;
 219         }
 220
 221         clock = clk_get_rate(&clk);
 222         if (IS_ERR_VALUE(clock)) {
 223                 dev_err(dev, "failed to get rate\n");
 224                 return clock;
 225         }
 226
 227         debug("%s: CLK %ld\n", __func__, clock);
 228
 229         ret = clk_enable(&clk);
 230         if (ret && ret != -ENOSYS) {
 231                 dev_err(dev, "failed to enable clock\n");
 232                 return ret;
 233         }
 234
 235         host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
 236                        SDHCI_QUIRK_BROKEN_R1B;
 237
 238 #ifdef CONFIG_ZYNQ_HISPD_BROKEN
 239         host->quirks |= SDHCI_QUIRK_BROKEN_HISPD_MODE;
 240 #endif
 241
 242         if (priv->no_1p8)
 243                 host->quirks |= SDHCI_QUIRK_NO_1_8_V;
 244
 245         host->max_clk = clock;
 246
 247         host->mmc = &plat->mmc;
 248         host->mmc->dev = dev;
 249         host->mmc->priv = host;
 250
 251         ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max,
 252                               CONFIG_ZYNQ_SDHCI_MIN_FREQ);
 253         if (ret)
 254                 return ret;
 255         upriv->mmc = host->mmc;
 256
 257         return sdhci_probe(dev);
 258 }
 259
 260 static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
 261 {
 262         struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
 263         struct arasan_sdhci_priv *priv = dev_get_priv(dev);
 264
 265         priv->host = calloc(1, sizeof(struct sdhci_host));
 266         if (!priv->host)
 267                 return -1;
 268
 269         priv->host->name = dev->name;
 270
 271 #if defined(CONFIG_ARCH_ZYNQMP)
 272         priv->host->ops = &arasan_ops;
 273 #endif
 274
 275         priv->host->ioaddr = (void *)dev_read_addr(dev);
 276         if (IS_ERR(priv->host->ioaddr))
 277                 return PTR_ERR(priv->host->ioaddr);
 278
 279         priv->deviceid = dev_read_u32_default(dev, "xlnx,device_id", -1);
 280         priv->bank = dev_read_u32_default(dev, "xlnx,mio_bank", -1);
 281         priv->no_1p8 = dev_read_bool(dev, "no-1-8-v");
 282
 283         plat->f_max = dev_read_u32_default(dev, "max-frequency",
 284                                            CONFIG_ZYNQ_SDHCI_MAX_FREQ);
 285         return 0;
 286 }
 287
 288 static int arasan_sdhci_bind(struct udevice *dev)
 289 {
 290         struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
 291
 292         return sdhci_bind(dev, &plat->mmc, &plat->cfg);
 293 }
 294
 295 static const struct udevice_id arasan_sdhci_ids[] = {
 296         { .compatible = "arasan,sdhci-8.9a" },
 297         { }
 298 };
 299
 300 U_BOOT_DRIVER(arasan_sdhci_drv) = {
 301         .name           = "arasan_sdhci",
 302         .id             = UCLASS_MMC,
 303         .of_match       = arasan_sdhci_ids,
 304         .ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
 305         .ops            = &sdhci_ops,
 306         .bind           = arasan_sdhci_bind,
 307         .probe          = arasan_sdhci_probe,
 308         .priv_auto_alloc_size = sizeof(struct arasan_sdhci_priv),
 309         .platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat),
 310 };