drivers/mmc/zynq_sdhci.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2013 - 2015 Xilinx, Inc.
   4  *
   5  * Xilinx Zynq SD Host Controller Interface
   6  */
   7
   8 #include <clk.h>
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <fdtdec.h>
  12 #include "mmc_private.h"
  13 #include <linux/libfdt.h>
  14 #include <malloc.h>
  15 #include <sdhci.h>
  16 #include <zynqmp_tap_delay.h>
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 struct arasan_sdhci_plat {
  21         struct mmc_config cfg;
  22         struct mmc mmc;
  23         unsigned int f_max;
  24 };
  25
  26 struct arasan_sdhci_priv {
  27         struct sdhci_host *host;
  28         u8 deviceid;
  29         u8 bank;
  30         u8 no_1p8;
  31 };
  32
  33 #if defined(CONFIG_ARCH_ZYNQMP)
  34 #define MMC_HS200_BUS_SPEED     5
  35
  36 static const u8 mode2timing[] = {
  37         [MMC_LEGACY] = UHS_SDR12_BUS_SPEED,
  38         [SD_LEGACY] = UHS_SDR12_BUS_SPEED,
  39         [MMC_HS] = HIGH_SPEED_BUS_SPEED,
  40         [SD_HS] = HIGH_SPEED_BUS_SPEED,
  41         [MMC_HS_52] = HIGH_SPEED_BUS_SPEED,
  42         [MMC_DDR_52] = HIGH_SPEED_BUS_SPEED,
  43         [UHS_SDR12] = UHS_SDR12_BUS_SPEED,
  44         [UHS_SDR25] = UHS_SDR25_BUS_SPEED,
  45         [UHS_SDR50] = UHS_SDR50_BUS_SPEED,
  46         [UHS_DDR50] = UHS_DDR50_BUS_SPEED,
  47         [UHS_SDR104] = UHS_SDR104_BUS_SPEED,
  48         [MMC_HS_200] = MMC_HS200_BUS_SPEED,
  49 };
  50
  51 #define SDHCI_TUNING_LOOP_COUNT 40
  52
  53 static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 deviceid)
  54 {
  55         u16 clk;
  56         unsigned long timeout;
  57
  58         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
  59         clk &= ~(SDHCI_CLOCK_CARD_EN);
  60         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  61
  62         /* Issue DLL Reset */
  63         zynqmp_dll_reset(deviceid);
  64
  65         /* Wait max 20 ms */
  66         timeout = 100;
  67         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
  68                                 & SDHCI_CLOCK_INT_STABLE)) {
  69                 if (timeout == 0) {
  70                         dev_err(mmc_dev(host->mmc),
  71                                 ": Internal clock never stabilised.\n");
  72                         return;
  73                 }
  74                 timeout--;
  75                 udelay(1000);
  76         }
  77
  78         clk |= SDHCI_CLOCK_CARD_EN;
  79         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  80 }
  81
  82 static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
  83 {
  84         struct mmc_cmd cmd;
  85         struct mmc_data data;
  86         u32 ctrl;
  87         struct sdhci_host *host;
  88         struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
  89         char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
  90         u8 deviceid;
  91
  92         debug("%s\n", __func__);
  93
  94         host = priv->host;
  95         deviceid = priv->deviceid;
  96
  97         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  98         ctrl |= SDHCI_CTRL_EXEC_TUNING;
  99         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
 100
 101         mdelay(1);
 102
 103         arasan_zynqmp_dll_reset(host, deviceid);
 104
 105         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
 106         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
 107
 108         do {
 109                 cmd.cmdidx = opcode;
 110                 cmd.resp_type = MMC_RSP_R1;
 111                 cmd.cmdarg = 0;
 112
 113                 data.blocksize = 64;
 114                 data.blocks = 1;
 115                 data.flags = MMC_DATA_READ;
 116
 117                 if (tuning_loop_counter-- == 0)
 118                         break;
 119
 120                 if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200 &&
 121                     mmc->bus_width == 8)
 122                         data.blocksize = 128;
 123
 124                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 125                                                     data.blocksize),
 126                              SDHCI_BLOCK_SIZE);
 127                 sdhci_writew(host, data.blocks, SDHCI_BLOCK_COUNT);
 128                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
 129
 130                 mmc_send_cmd(mmc, &cmd, NULL);
 131                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 132
 133                 if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
 134                         udelay(1);
 135
 136         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
 137
 138         if (tuning_loop_counter < 0) {
 139                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
 140                 sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL2);
 141         }
 142
 143         if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
 144                 printf("%s:Tuning failed\n", __func__);
 145                 return -1;
 146         }
 147
 148         udelay(1);
 149         arasan_zynqmp_dll_reset(host, deviceid);
 150
 151         /* Enable only interrupts served by the SD controller */
 152         sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
 153                      SDHCI_INT_ENABLE);
 154         /* Mask all sdhci interrupt sources */
 155         sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
 156
 157         return 0;
 158 }
 159
 160 static void arasan_sdhci_set_tapdelay(struct sdhci_host *host)
 161 {
 162         struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
 163         struct mmc *mmc = (struct mmc *)host->mmc;
 164         u8 uhsmode;
 165
 166         uhsmode = mode2timing[mmc->selected_mode];
 167
 168         if (uhsmode >= UHS_SDR25_BUS_SPEED)
 169                 arasan_zynqmp_set_tapdelay(priv->deviceid, uhsmode,
 170                                            priv->bank);
 171 }
 172
 173 static void arasan_sdhci_set_control_reg(struct sdhci_host *host)
 174 {
 175         struct mmc *mmc = (struct mmc *)host->mmc;
 176         u32 reg;
 177
 178         if (!IS_SD(mmc))
 179                 return;
 180
 181         if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
 182                 reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 183                 reg |= SDHCI_CTRL_VDD_180;
 184                 sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
 185         }
 186
 187         if (mmc->selected_mode > SD_HS &&
 188             mmc->selected_mode <= UHS_DDR50)
 189                 sdhci_set_uhs_timing(host);
 190 }
 191 #endif
 192
 193 #if defined(CONFIG_DM_MMC) && defined(CONFIG_ARCH_ZYNQMP)
 194 const struct sdhci_ops arasan_ops = {
 195         .platform_execute_tuning        = &arasan_sdhci_execute_tuning,
 196         .set_delay = &arasan_sdhci_set_tapdelay,
 197         .set_control_reg = &arasan_sdhci_set_control_reg,
 198 };
 199 #endif
 200
 201 static int arasan_sdhci_probe(struct udevice *dev)
 202 {
 203         struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
 204         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 205         struct arasan_sdhci_priv *priv = dev_get_priv(dev);
 206         struct sdhci_host *host;
 207         struct clk clk;
 208         unsigned long clock;
 209         int ret;
 210
 211         host = priv->host;
 212
 213         ret = clk_get_by_index(dev, 0, &clk);
 214         if (ret < 0) {
 215                 dev_err(dev, "failed to get clock\n");
 216                 return ret;
 217         }
 218
 219         clock = clk_get_rate(&clk);
 220         if (IS_ERR_VALUE(clock)) {
 221                 dev_err(dev, "failed to get rate\n");
 222                 return clock;
 223         }
 224
 225         debug("%s: CLK %ld\n", __func__, clock);
 226
 227         ret = clk_enable(&clk);
 228         if (ret && ret != -ENOSYS) {
 229                 dev_err(dev, "failed to enable clock\n");
 230                 return ret;
 231         }
 232
 233         host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
 234                        SDHCI_QUIRK_BROKEN_R1B;
 235
 236 #ifdef CONFIG_ZYNQ_HISPD_BROKEN
 237         host->quirks |= SDHCI_QUIRK_BROKEN_HISPD_MODE;
 238 #endif
 239
 240         if (priv->no_1p8)
 241                 host->quirks |= SDHCI_QUIRK_NO_1_8_V;
 242
 243         host->max_clk = clock;
 244
 245         host->mmc = &plat->mmc;
 246         host->mmc->dev = dev;
 247         host->mmc->priv = host;
 248
 249         ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max,
 250                               CONFIG_ZYNQ_SDHCI_MIN_FREQ);
 251         if (ret)
 252                 return ret;
 253         upriv->mmc = host->mmc;
 254
 255         return sdhci_probe(dev);
 256 }
 257
 258 static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
 259 {
 260         struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
 261         struct arasan_sdhci_priv *priv = dev_get_priv(dev);
 262
 263         priv->host = calloc(1, sizeof(struct sdhci_host));
 264         if (!priv->host)
 265                 return -1;
 266
 267         priv->host->name = dev->name;
 268
 269 #if defined(CONFIG_DM_MMC) && defined(CONFIG_ARCH_ZYNQMP)
 270         priv->host->ops = &arasan_ops;
 271 #endif
 272
 273         priv->host->ioaddr = (void *)dev_read_addr(dev);
 274         if (IS_ERR(priv->host->ioaddr))
 275                 return PTR_ERR(priv->host->ioaddr);
 276
 277         priv->deviceid = dev_read_u32_default(dev, "xlnx,device_id", -1);
 278         priv->bank = dev_read_u32_default(dev, "xlnx,mio_bank", -1);
 279         priv->no_1p8 = dev_read_bool(dev, "no-1-8-v");
 280
 281         plat->f_max = dev_read_u32_default(dev, "max-frequency",
 282                                            CONFIG_ZYNQ_SDHCI_MAX_FREQ);
 283         return 0;
 284 }
 285
 286 static int arasan_sdhci_bind(struct udevice *dev)
 287 {
 288         struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
 289
 290         return sdhci_bind(dev, &plat->mmc, &plat->cfg);
 291 }
 292
 293 static const struct udevice_id arasan_sdhci_ids[] = {
 294         { .compatible = "arasan,sdhci-8.9a" },
 295         { }
 296 };
 297
 298 U_BOOT_DRIVER(arasan_sdhci_drv) = {
 299         .name           = "arasan_sdhci",
 300         .id             = UCLASS_MMC,
 301         .of_match       = arasan_sdhci_ids,
 302         .ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
 303         .ops            = &sdhci_ops,
 304         .bind           = arasan_sdhci_bind,
 305         .probe          = arasan_sdhci_probe,
 306         .priv_auto_alloc_size = sizeof(struct arasan_sdhci_priv),
 307         .platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat),
 308 };