drivers/mmc/zynq_sdhci.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2013 - 2015 Xilinx, Inc.
   4  *
   5  * Xilinx Zynq SD Host Controller Interface
   6  */
   7
   8 #include <clk.h>
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <fdtdec.h>
  12 #include <linux/delay.h>
  13 #include "mmc_private.h"
  14 #include <log.h>
  15 #include <reset.h>
  16 #include <dm/device_compat.h>
  17 #include <linux/err.h>
  18 #include <linux/libfdt.h>
  19 #include <asm/types.h>
  20 #include <linux/math64.h>
  21 #include <asm/cache.h>
  22 #include <malloc.h>
  23 #include <sdhci.h>
  24 #include <zynqmp_firmware.h>
  25
  26 #define SDHCI_ARASAN_ITAPDLY_REGISTER   0xF0F8
  27 #define SDHCI_ARASAN_ITAPDLY_SEL_MASK   GENMASK(7, 0)
  28 #define SDHCI_ARASAN_OTAPDLY_REGISTER   0xF0FC
  29 #define SDHCI_ARASAN_OTAPDLY_SEL_MASK   GENMASK(5, 0)
  30 #define SDHCI_ITAPDLY_CHGWIN            BIT(9)
  31 #define SDHCI_ITAPDLY_ENABLE            BIT(8)
  32 #define SDHCI_OTAPDLY_ENABLE            BIT(6)
  33
  34 #define SDHCI_TUNING_LOOP_COUNT         40
  35 #define MMC_BANK2                       0x2
  36
  37 #define SD_DLL_CTRL                     0xFF180358
  38 #define SD_ITAP_DLY                     0xFF180314
  39 #define SD_OTAP_DLY                     0xFF180318
  40 #define SD0_DLL_RST                     BIT(2)
  41 #define SD1_DLL_RST                     BIT(18)
  42 #define SD0_ITAPCHGWIN                  BIT(9)
  43 #define SD1_ITAPCHGWIN                  BIT(25)
  44 #define SD0_ITAPDLYENA                  BIT(8)
  45 #define SD1_ITAPDLYENA                  BIT(24)
  46 #define SD0_ITAPDLYSEL_MASK             GENMASK(7, 0)
  47 #define SD1_ITAPDLYSEL_MASK             GENMASK(23, 16)
  48 #define SD0_OTAPDLYSEL_MASK             GENMASK(5, 0)
  49 #define SD1_OTAPDLYSEL_MASK             GENMASK(21, 16)
  50
  51 struct arasan_sdhci_clk_data {
  52         int clk_phase_in[MMC_TIMING_MMC_HS400 + 1];
  53         int clk_phase_out[MMC_TIMING_MMC_HS400 + 1];
  54 };
  55
  56 struct arasan_sdhci_plat {
  57         struct mmc_config cfg;
  58         struct mmc mmc;
  59 };
  60
  61 struct arasan_sdhci_priv {
  62         struct sdhci_host *host;
  63         struct arasan_sdhci_clk_data clk_data;
  64         u8 deviceid;
  65         u8 bank;
  66         u8 no_1p8;
  67         struct reset_ctl_bulk resets;
  68 };
  69
  70 /* For Versal platforms zynqmp_mmio_write() won't be available */
  71 __weak int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value)
  72 {
  73         return 0;
  74 }
  75
  76 __weak int xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
  77                              u32 arg3, u32 *ret_payload)
  78 {
  79         return 0;
  80 }
  81
  82 #if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL)
  83 /* Default settings for ZynqMP Clock Phases */
  84 static const u32 zynqmp_iclk_phases[] = {0, 63, 63, 0, 63,  0,
  85                                          0, 183, 54,  0, 0};
  86 static const u32 zynqmp_oclk_phases[] = {0, 72, 60, 0, 60, 72,
  87                                          135, 48, 72, 135, 0};
  88
  89 /* Default settings for Versal Clock Phases */
  90 static const u32 versal_iclk_phases[] = {0, 132, 132, 0, 132,
  91                                          0, 0, 162, 90, 0, 0};
  92 static const u32 versal_oclk_phases[] = {0,  60, 48, 0, 48, 72,
  93                                          90, 36, 60, 90, 0};
  94
  95 static const u8 mode2timing[] = {
  96         [MMC_LEGACY] = MMC_TIMING_LEGACY,
  97         [MMC_HS] = MMC_TIMING_MMC_HS,
  98         [SD_HS] = MMC_TIMING_SD_HS,
  99         [MMC_HS_52] = MMC_TIMING_UHS_SDR50,
 100         [MMC_DDR_52] = MMC_TIMING_UHS_DDR50,
 101         [UHS_SDR12] = MMC_TIMING_UHS_SDR12,
 102         [UHS_SDR25] = MMC_TIMING_UHS_SDR25,
 103         [UHS_SDR50] = MMC_TIMING_UHS_SDR50,
 104         [UHS_DDR50] = MMC_TIMING_UHS_DDR50,
 105         [UHS_SDR104] = MMC_TIMING_UHS_SDR104,
 106         [MMC_HS_200] = MMC_TIMING_MMC_HS200,
 107 };
 108
 109 static inline int arasan_zynqmp_set_in_tapdelay(u8 node_id, u32 itap_delay)
 110 {
 111         int ret;
 112
 113         if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
 114                 if (node_id == NODE_SD_0) {
 115                         ret = zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN,
 116                                                 SD0_ITAPCHGWIN);
 117                         if (ret)
 118                                 return ret;
 119
 120                         ret = zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA,
 121                                                 SD0_ITAPDLYENA);
 122                         if (ret)
 123                                 return ret;
 124
 125                         ret = zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK,
 126                                                 itap_delay);
 127                         if (ret)
 128                                 return ret;
 129
 130                         ret = zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN, 0);
 131                         if (ret)
 132                                 return ret;
 133                 }
 134                 ret = zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN,
 135                                         SD1_ITAPCHGWIN);
 136                 if (ret)
 137                         return ret;
 138
 139                 ret = zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA,
 140                                         SD1_ITAPDLYENA);
 141                 if (ret)
 142                         return ret;
 143
 144                 ret = zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
 145                                         (itap_delay << 16));
 146                 if (ret)
 147                         return ret;
 148
 149                 ret = zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN, 0);
 150                 if (ret)
 151                         return ret;
 152         } else {
 153                 return xilinx_pm_request(PM_IOCTL, (u32)node_id,
 154                                          IOCTL_SET_SD_TAPDELAY,
 155                                          PM_TAPDELAY_INPUT, itap_delay, NULL);
 156         }
 157
 158         return 0;
 159 }
 160
 161 static inline int arasan_zynqmp_set_out_tapdelay(u8 node_id, u32 otap_delay)
 162 {
 163         if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
 164                 if (node_id == NODE_SD_0)
 165                         return zynqmp_mmio_write(SD_OTAP_DLY,
 166                                                  SD0_OTAPDLYSEL_MASK,
 167                                                  otap_delay);
 168
 169                 return zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
 170                                          (otap_delay << 16));
 171         } else {
 172                 return xilinx_pm_request(PM_IOCTL, (u32)node_id,
 173                                          IOCTL_SET_SD_TAPDELAY,
 174                                          PM_TAPDELAY_OUTPUT, otap_delay, NULL);
 175         }
 176 }
 177
 178 static inline int zynqmp_dll_reset(u8 node_id, u32 type)
 179 {
 180         if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
 181                 if (node_id == NODE_SD_0)
 182                         return zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST,
 183                                                  type == PM_DLL_RESET_ASSERT ?
 184                                                  SD0_DLL_RST : 0);
 185
 186                 return zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST,
 187                                          type == PM_DLL_RESET_ASSERT ?
 188                                          SD1_DLL_RST : 0);
 189         } else {
 190                 return xilinx_pm_request(PM_IOCTL, (u32)node_id,
 191                                          IOCTL_SD_DLL_RESET, type, 0, NULL);
 192         }
 193 }
 194
 195 static int arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 node_id)
 196 {
 197         struct mmc *mmc = (struct mmc *)host->mmc;
 198         struct udevice *dev = mmc->dev;
 199         unsigned long timeout;
 200         int ret;
 201         u16 clk;
 202
 203         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
 204         clk &= ~(SDHCI_CLOCK_CARD_EN);
 205         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 206
 207         /* Issue DLL Reset */
 208         ret = zynqmp_dll_reset(node_id, PM_DLL_RESET_ASSERT);
 209         if (ret) {
 210                 dev_err(dev, "dll_reset assert failed with err: %d\n", ret);
 211                 return ret;
 212         }
 213
 214         /* Allow atleast 1ms delay for proper DLL reset */
 215         mdelay(1);
 216         ret = zynqmp_dll_reset(node_id, PM_DLL_RESET_RELEASE);
 217         if (ret) {
 218                 dev_err(dev, "dll_reset release failed with err: %d\n", ret);
 219                 return ret;
 220         }
 221
 222         /* Wait max 20 ms */
 223         timeout = 100;
 224         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
 225                                 & SDHCI_CLOCK_INT_STABLE)) {
 226                 if (timeout == 0) {
 227                         dev_err(dev, ": Internal clock never stabilised.\n");
 228                         return -EBUSY;
 229                 }
 230                 timeout--;
 231                 udelay(1000);
 232         }
 233
 234         clk |= SDHCI_CLOCK_CARD_EN;
 235         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 236
 237         return 0;
 238 }
 239
 240 static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
 241 {
 242         struct mmc_cmd cmd;
 243         struct mmc_data data;
 244         u32 ctrl;
 245         struct sdhci_host *host;
 246         struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
 247         char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
 248         u8 node_id = priv->deviceid ? NODE_SD_1 : NODE_SD_0;
 249
 250         dev_dbg(mmc->dev, "%s\n", __func__);
 251
 252         host = priv->host;
 253
 254         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 255         ctrl |= SDHCI_CTRL_EXEC_TUNING;
 256         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
 257
 258         mdelay(1);
 259
 260         arasan_zynqmp_dll_reset(host, node_id);
 261
 262         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
 263         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
 264
 265         do {
 266                 cmd.cmdidx = opcode;
 267                 cmd.resp_type = MMC_RSP_R1;
 268                 cmd.cmdarg = 0;
 269
 270                 data.blocksize = 64;
 271                 data.blocks = 1;
 272                 data.flags = MMC_DATA_READ;
 273
 274                 if (tuning_loop_counter-- == 0)
 275                         break;
 276
 277                 if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200 &&
 278                     mmc->bus_width == 8)
 279                         data.blocksize = 128;
 280
 281                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 282                                                     data.blocksize),
 283                              SDHCI_BLOCK_SIZE);
 284                 sdhci_writew(host, data.blocks, SDHCI_BLOCK_COUNT);
 285                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
 286
 287                 mmc_send_cmd(mmc, &cmd, NULL);
 288                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 289
 290                 if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
 291                         udelay(1);
 292
 293         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
 294
 295         if (tuning_loop_counter < 0) {
 296                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
 297                 sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL2);
 298         }
 299
 300         if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
 301                 printf("%s:Tuning failed\n", __func__);
 302                 return -1;
 303         }
 304
 305         udelay(1);
 306         arasan_zynqmp_dll_reset(host, node_id);
 307
 308         /* Enable only interrupts served by the SD controller */
 309         sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
 310                      SDHCI_INT_ENABLE);
 311         /* Mask all sdhci interrupt sources */
 312         sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
 313
 314         return 0;
 315 }
 316
 317 /**
 318  * sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
 319  *
 320  * @host:               Pointer to the sdhci_host structure.
 321  * @degrees:            The clock phase shift between 0 - 359.
 322  * Return: 0
 323  *
 324  * Set the SD Output Clock Tap Delays for Output path
 325  */
 326 static int sdhci_zynqmp_sdcardclk_set_phase(struct sdhci_host *host,
 327                                             int degrees)
 328 {
 329         struct mmc *mmc = (struct mmc *)host->mmc;
 330         struct udevice *dev = mmc->dev;
 331         struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
 332         u8 node_id = priv->deviceid ? NODE_SD_1 : NODE_SD_0;
 333         u8 tap_delay, tap_max = 0;
 334         int timing = mode2timing[mmc->selected_mode];
 335         int ret;
 336
 337         /*
 338          * This is applicable for SDHCI_SPEC_300 and above
 339          * ZynqMP does not set phase for <=25MHz clock.
 340          * If degrees is zero, no need to do anything.
 341          */
 342         if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
 343                 return 0;
 344
 345         switch (timing) {
 346         case MMC_TIMING_MMC_HS:
 347         case MMC_TIMING_SD_HS:
 348         case MMC_TIMING_UHS_SDR25:
 349         case MMC_TIMING_UHS_DDR50:
 350         case MMC_TIMING_MMC_DDR52:
 351                 /* For 50MHz clock, 30 Taps are available */
 352                 tap_max = 30;
 353                 break;
 354         case MMC_TIMING_UHS_SDR50:
 355                 /* For 100MHz clock, 15 Taps are available */
 356                 tap_max = 15;
 357                 break;
 358         case MMC_TIMING_UHS_SDR104:
 359         case MMC_TIMING_MMC_HS200:
 360                 /* For 200MHz clock, 8 Taps are available */
 361                 tap_max = 8;
 362         default:
 363                 break;
 364         }
 365
 366         tap_delay = (degrees * tap_max) / 360;
 367
 368         /* Limit output tap_delay value to 6 bits */
 369         tap_delay &= SDHCI_ARASAN_OTAPDLY_SEL_MASK;
 370
 371         /* Set the Clock Phase */
 372         ret = arasan_zynqmp_set_out_tapdelay(node_id, tap_delay);
 373         if (ret) {
 374                 dev_err(dev, "Error setting output Tap Delay\n");
 375                 return ret;
 376         }
 377
 378         /* Release DLL Reset */
 379         ret = zynqmp_dll_reset(node_id, PM_DLL_RESET_RELEASE);
 380         if (ret) {
 381                 dev_err(dev, "dll_reset release failed with err: %d\n", ret);
 382                 return ret;
 383         }
 384
 385         return 0;
 386 }
 387
 388 /**
 389  * sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays
 390  *
 391  * @host:               Pointer to the sdhci_host structure.
 392  * @degrees:            The clock phase shift between 0 - 359.
 393  * Return: 0
 394  *
 395  * Set the SD Input Clock Tap Delays for Input path
 396  */
 397 static int sdhci_zynqmp_sampleclk_set_phase(struct sdhci_host *host,
 398                                             int degrees)
 399 {
 400         struct mmc *mmc = (struct mmc *)host->mmc;
 401         struct udevice *dev = mmc->dev;
 402         struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
 403         u8 node_id = priv->deviceid ? NODE_SD_1 : NODE_SD_0;
 404         u8 tap_delay, tap_max = 0;
 405         int timing = mode2timing[mmc->selected_mode];
 406         int ret;
 407
 408         /*
 409          * This is applicable for SDHCI_SPEC_300 and above
 410          * ZynqMP does not set phase for <=25MHz clock.
 411          * If degrees is zero, no need to do anything.
 412          */
 413         if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
 414                 return 0;
 415
 416         /* Assert DLL Reset */
 417         ret = zynqmp_dll_reset(node_id, PM_DLL_RESET_ASSERT);
 418         if (ret) {
 419                 dev_err(dev, "dll_reset assert failed with err: %d\n", ret);
 420                 return ret;
 421         }
 422
 423         switch (timing) {
 424         case MMC_TIMING_MMC_HS:
 425         case MMC_TIMING_SD_HS:
 426         case MMC_TIMING_UHS_SDR25:
 427         case MMC_TIMING_UHS_DDR50:
 428         case MMC_TIMING_MMC_DDR52:
 429                 /* For 50MHz clock, 120 Taps are available */
 430                 tap_max = 120;
 431                 break;
 432         case MMC_TIMING_UHS_SDR50:
 433                 /* For 100MHz clock, 60 Taps are available */
 434                 tap_max = 60;
 435                 break;
 436         case MMC_TIMING_UHS_SDR104:
 437         case MMC_TIMING_MMC_HS200:
 438                 /* For 200MHz clock, 30 Taps are available */
 439                 tap_max = 30;
 440         default:
 441                 break;
 442         }
 443
 444         tap_delay = (degrees * tap_max) / 360;
 445
 446         /* Limit input tap_delay value to 8 bits */
 447         tap_delay &= SDHCI_ARASAN_ITAPDLY_SEL_MASK;
 448
 449         ret = arasan_zynqmp_set_in_tapdelay(node_id, tap_delay);
 450         if (ret) {
 451                 dev_err(dev, "Error setting Input Tap Delay\n");
 452                 return ret;
 453         }
 454
 455         return 0;
 456 }
 457
 458 /**
 459  * sdhci_versal_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
 460  *
 461  * @host:               Pointer to the sdhci_host structure.
 462  * @degrees:            The clock phase shift between 0 - 359.
 463  * Return: 0
 464  *
 465  * Set the SD Output Clock Tap Delays for Output path
 466  */
 467 static int sdhci_versal_sdcardclk_set_phase(struct sdhci_host *host,
 468                                             int degrees)
 469 {
 470         struct mmc *mmc = (struct mmc *)host->mmc;
 471         u8 tap_delay, tap_max = 0;
 472         int timing = mode2timing[mmc->selected_mode];
 473         u32 regval;
 474
 475         /*
 476          * This is applicable for SDHCI_SPEC_300 and above
 477          * Versal does not set phase for <=25MHz clock.
 478          * If degrees is zero, no need to do anything.
 479          */
 480         if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
 481                 return 0;
 482
 483         switch (timing) {
 484         case MMC_TIMING_MMC_HS:
 485         case MMC_TIMING_SD_HS:
 486         case MMC_TIMING_UHS_SDR25:
 487         case MMC_TIMING_UHS_DDR50:
 488         case MMC_TIMING_MMC_DDR52:
 489                 /* For 50MHz clock, 30 Taps are available */
 490                 tap_max = 30;
 491                 break;
 492         case MMC_TIMING_UHS_SDR50:
 493                 /* For 100MHz clock, 15 Taps are available */
 494                 tap_max = 15;
 495                 break;
 496         case MMC_TIMING_UHS_SDR104:
 497         case MMC_TIMING_MMC_HS200:
 498                 /* For 200MHz clock, 8 Taps are available */
 499                 tap_max = 8;
 500         default:
 501                 break;
 502         }
 503
 504         tap_delay = (degrees * tap_max) / 360;
 505
 506         /* Limit output tap_delay value to 6 bits */
 507         tap_delay &= SDHCI_ARASAN_OTAPDLY_SEL_MASK;
 508
 509         /* Set the Clock Phase */
 510         regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER);
 511         regval |= SDHCI_OTAPDLY_ENABLE;
 512         sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
 513         regval &= ~SDHCI_ARASAN_OTAPDLY_SEL_MASK;
 514         regval |= tap_delay;
 515         sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
 516
 517         return 0;
 518 }
 519
 520 /**
 521  * sdhci_versal_sampleclk_set_phase - Set the SD Input Clock Tap Delays
 522  *
 523  * @host:               Pointer to the sdhci_host structure.
 524  * @degrees:            The clock phase shift between 0 - 359.
 525  * Return: 0
 526  *
 527  * Set the SD Input Clock Tap Delays for Input path
 528  */
 529 static int sdhci_versal_sampleclk_set_phase(struct sdhci_host *host,
 530                                             int degrees)
 531 {
 532         struct mmc *mmc = (struct mmc *)host->mmc;
 533         u8 tap_delay, tap_max = 0;
 534         int timing = mode2timing[mmc->selected_mode];
 535         u32 regval;
 536
 537         /*
 538          * This is applicable for SDHCI_SPEC_300 and above
 539          * Versal does not set phase for <=25MHz clock.
 540          * If degrees is zero, no need to do anything.
 541          */
 542         if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
 543                 return 0;
 544
 545         switch (timing) {
 546         case MMC_TIMING_MMC_HS:
 547         case MMC_TIMING_SD_HS:
 548         case MMC_TIMING_UHS_SDR25:
 549         case MMC_TIMING_UHS_DDR50:
 550         case MMC_TIMING_MMC_DDR52:
 551                 /* For 50MHz clock, 120 Taps are available */
 552                 tap_max = 120;
 553                 break;
 554         case MMC_TIMING_UHS_SDR50:
 555                 /* For 100MHz clock, 60 Taps are available */
 556                 tap_max = 60;
 557                 break;
 558         case MMC_TIMING_UHS_SDR104:
 559         case MMC_TIMING_MMC_HS200:
 560                 /* For 200MHz clock, 30 Taps are available */
 561                 tap_max = 30;
 562         default:
 563                 break;
 564         }
 565
 566         tap_delay = (degrees * tap_max) / 360;
 567
 568         /* Limit input tap_delay value to 8 bits */
 569         tap_delay &= SDHCI_ARASAN_ITAPDLY_SEL_MASK;
 570
 571         /* Set the Clock Phase */
 572         regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER);
 573         regval |= SDHCI_ITAPDLY_CHGWIN;
 574         sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
 575         regval |= SDHCI_ITAPDLY_ENABLE;
 576         sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
 577         regval &= ~SDHCI_ARASAN_ITAPDLY_SEL_MASK;
 578         regval |= tap_delay;
 579         sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
 580         regval &= ~SDHCI_ITAPDLY_CHGWIN;
 581         sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
 582
 583         return 0;
 584 }
 585
 586 static int arasan_sdhci_set_tapdelay(struct sdhci_host *host)
 587 {
 588         struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
 589         struct arasan_sdhci_clk_data *clk_data = &priv->clk_data;
 590         struct mmc *mmc = (struct mmc *)host->mmc;
 591         struct udevice *dev = mmc->dev;
 592         u8 timing = mode2timing[mmc->selected_mode];
 593         u32 iclk_phase = clk_data->clk_phase_in[timing];
 594         u32 oclk_phase = clk_data->clk_phase_out[timing];
 595         int ret;
 596
 597         dev_dbg(dev, "%s, host:%s, mode:%d\n", __func__, host->name, timing);
 598
 599         if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) &&
 600             device_is_compatible(dev, "xlnx,zynqmp-8.9a")) {
 601                 ret = sdhci_zynqmp_sampleclk_set_phase(host, iclk_phase);
 602                 if (ret)
 603                         return ret;
 604
 605                 ret = sdhci_zynqmp_sdcardclk_set_phase(host, oclk_phase);
 606                 if (ret)
 607                         return ret;
 608         } else if (IS_ENABLED(CONFIG_ARCH_VERSAL) &&
 609                    device_is_compatible(dev, "xlnx,versal-8.9a")) {
 610                 ret = sdhci_versal_sampleclk_set_phase(host, iclk_phase);
 611                 if (ret)
 612                         return ret;
 613
 614                 ret = sdhci_versal_sdcardclk_set_phase(host, oclk_phase);
 615                 if (ret)
 616                         return ret;
 617         }
 618
 619         return 0;
 620 }
 621
 622 static void arasan_dt_read_clk_phase(struct udevice *dev, unsigned char timing,
 623                                      const char *prop)
 624 {
 625         struct arasan_sdhci_priv *priv = dev_get_priv(dev);
 626         struct arasan_sdhci_clk_data *clk_data = &priv->clk_data;
 627         u32 clk_phase[2] = {0};
 628
 629         /*
 630          * Read Tap Delay values from DT, if the DT does not contain the
 631          * Tap Values then use the pre-defined values
 632          */
 633         if (dev_read_u32_array(dev, prop, &clk_phase[0], 2)) {
 634                 dev_dbg(dev, "Using predefined clock phase for %s = %d %d\n",
 635                         prop, clk_data->clk_phase_in[timing],
 636                         clk_data->clk_phase_out[timing]);
 637                 return;
 638         }
 639
 640         /* The values read are Input and Output Clock Delays in order */
 641         clk_data->clk_phase_in[timing] = clk_phase[0];
 642         clk_data->clk_phase_out[timing] = clk_phase[1];
 643 }
 644
 645 /**
 646  * arasan_dt_parse_clk_phases - Read Tap Delay values from DT
 647  *
 648  * @dev:                Pointer to our struct udevice.
 649  *
 650  * Called at initialization to parse the values of Tap Delays.
 651  */
 652 static void arasan_dt_parse_clk_phases(struct udevice *dev)
 653 {
 654         struct arasan_sdhci_priv *priv = dev_get_priv(dev);
 655         struct arasan_sdhci_clk_data *clk_data = &priv->clk_data;
 656         int i;
 657
 658         if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) &&
 659             device_is_compatible(dev, "xlnx,zynqmp-8.9a")) {
 660                 for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
 661                         clk_data->clk_phase_in[i] = zynqmp_iclk_phases[i];
 662                         clk_data->clk_phase_out[i] = zynqmp_oclk_phases[i];
 663                 }
 664
 665                 if (priv->bank == MMC_BANK2) {
 666                         clk_data->clk_phase_out[MMC_TIMING_UHS_SDR104] = 90;
 667                         clk_data->clk_phase_out[MMC_TIMING_MMC_HS200] = 90;
 668                 }
 669         }
 670
 671         if (IS_ENABLED(CONFIG_ARCH_VERSAL) &&
 672             device_is_compatible(dev, "xlnx,versal-8.9a")) {
 673                 for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
 674                         clk_data->clk_phase_in[i] = versal_iclk_phases[i];
 675                         clk_data->clk_phase_out[i] = versal_oclk_phases[i];
 676                 }
 677         }
 678
 679         arasan_dt_read_clk_phase(dev, MMC_TIMING_LEGACY,
 680                                  "clk-phase-legacy");
 681         arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_HS,
 682                                  "clk-phase-mmc-hs");
 683         arasan_dt_read_clk_phase(dev, MMC_TIMING_SD_HS,
 684                                  "clk-phase-sd-hs");
 685         arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR12,
 686                                  "clk-phase-uhs-sdr12");
 687         arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR25,
 688                                  "clk-phase-uhs-sdr25");
 689         arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR50,
 690                                  "clk-phase-uhs-sdr50");
 691         arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR104,
 692                                  "clk-phase-uhs-sdr104");
 693         arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_DDR50,
 694                                  "clk-phase-uhs-ddr50");
 695         arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_DDR52,
 696                                  "clk-phase-mmc-ddr52");
 697         arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_HS200,
 698                                  "clk-phase-mmc-hs200");
 699         arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_HS400,
 700                                  "clk-phase-mmc-hs400");
 701 }
 702
 703 static const struct sdhci_ops arasan_ops = {
 704         .platform_execute_tuning        = &arasan_sdhci_execute_tuning,
 705         .set_delay = &arasan_sdhci_set_tapdelay,
 706         .set_control_reg = &sdhci_set_control_reg,
 707 };
 708 #endif
 709
 710 #if defined(CONFIG_ARCH_ZYNQMP)
 711 static int sdhci_zynqmp_set_dynamic_config(struct arasan_sdhci_priv *priv,
 712                                            struct udevice *dev)
 713 {
 714         int ret;
 715         u32 node_id = priv->deviceid ? NODE_SD_1 : NODE_SD_0;
 716         struct clk clk;
 717         unsigned long clock, mhz;
 718
 719         ret = xilinx_pm_request(PM_REQUEST_NODE, node_id, ZYNQMP_PM_CAPABILITY_ACCESS,
 720                                 ZYNQMP_PM_MAX_QOS, ZYNQMP_PM_REQUEST_ACK_NO, NULL);
 721         if (ret) {
 722                 dev_err(dev, "Request node failed for %d\n", node_id);
 723                 return ret;
 724         }
 725
 726         ret = reset_get_bulk(dev, &priv->resets);
 727         if (ret == -ENOTSUPP || ret == -ENOENT) {
 728                 dev_err(dev, "Reset not found\n");
 729                 return 0;
 730         } else if (ret) {
 731                 dev_err(dev, "Reset failed\n");
 732                 return ret;
 733         }
 734
 735         ret = reset_assert_bulk(&priv->resets);
 736         if (ret) {
 737                 dev_err(dev, "Reset assert failed\n");
 738                 return ret;
 739         }
 740
 741         ret = zynqmp_pm_set_sd_config(node_id, SD_CONFIG_FIXED, 0);
 742         if (ret) {
 743                 dev_err(dev, "SD_CONFIG_FIXED failed\n");
 744                 return ret;
 745         }
 746
 747         ret = zynqmp_pm_set_sd_config(node_id, SD_CONFIG_EMMC_SEL,
 748                                       dev_read_bool(dev, "non-removable"));
 749         if (ret) {
 750                 dev_err(dev, "SD_CONFIG_EMMC_SEL failed\n");
 751                 return ret;
 752         }
 753
 754         ret = clk_get_by_index(dev, 0, &clk);
 755         if (ret < 0) {
 756                 dev_err(dev, "failed to get clock\n");
 757                 return ret;
 758         }
 759
 760         clock = clk_get_rate(&clk);
 761         if (IS_ERR_VALUE(clock)) {
 762                 dev_err(dev, "failed to get rate\n");
 763                 return clock;
 764         }
 765
 766         mhz = DIV64_U64_ROUND_UP(clock, 1000000);
 767
 768         ret = zynqmp_pm_set_sd_config(node_id, SD_CONFIG_BASECLK, mhz);
 769         if (ret) {
 770                 dev_err(dev, "SD_CONFIG_BASECLK failed\n");
 771                 return ret;
 772         }
 773
 774         ret = zynqmp_pm_set_sd_config(node_id, SD_CONFIG_8BIT,
 775                                       (dev_read_u32_default(dev, "bus-width", 1) == 8));
 776         if (ret) {
 777                 dev_err(dev, "SD_CONFIG_8BIT failed\n");
 778                 return ret;
 779         }
 780
 781         ret = reset_deassert_bulk(&priv->resets);
 782         if (ret) {
 783                 dev_err(dev, "Reset release failed\n");
 784                 return ret;
 785         }
 786
 787         return 0;
 788 }
 789 #endif
 790
 791 static int arasan_sdhci_probe(struct udevice *dev)
 792 {
 793         struct arasan_sdhci_plat *plat = dev_get_plat(dev);
 794         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 795         struct arasan_sdhci_priv *priv = dev_get_priv(dev);
 796         struct sdhci_host *host;
 797         struct clk clk;
 798         unsigned long clock;
 799         int ret;
 800
 801         host = priv->host;
 802
 803 #if defined(CONFIG_ARCH_ZYNQMP)
 804         if (device_is_compatible(dev, "xlnx,zynqmp-8.9a")) {
 805                 ret = zynqmp_pm_is_function_supported(PM_IOCTL,
 806                                                       IOCTL_SET_SD_CONFIG);
 807                 if (!ret) {
 808                         ret = sdhci_zynqmp_set_dynamic_config(priv, dev);
 809                         if (ret)
 810                                 return ret;
 811                 }
 812         }
 813 #endif
 814
 815         ret = clk_get_by_index(dev, 0, &clk);
 816         if (ret < 0) {
 817                 dev_err(dev, "failed to get clock\n");
 818                 return ret;
 819         }
 820
 821         clock = clk_get_rate(&clk);
 822         if (IS_ERR_VALUE(clock)) {
 823                 dev_err(dev, "failed to get rate\n");
 824                 return clock;
 825         }
 826
 827         dev_dbg(dev, "%s: CLK %ld\n", __func__, clock);
 828
 829         ret = clk_enable(&clk);
 830         if (ret) {
 831                 dev_err(dev, "failed to enable clock\n");
 832                 return ret;
 833         }
 834
 835         host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
 836                        SDHCI_QUIRK_BROKEN_R1B;
 837
 838 #ifdef CONFIG_ZYNQ_HISPD_BROKEN
 839         host->quirks |= SDHCI_QUIRK_BROKEN_HISPD_MODE;
 840 #endif
 841
 842         if (priv->no_1p8)
 843                 host->quirks |= SDHCI_QUIRK_NO_1_8_V;
 844
 845         plat->cfg.f_max = CONFIG_ZYNQ_SDHCI_MAX_FREQ;
 846
 847         ret = mmc_of_parse(dev, &plat->cfg);
 848         if (ret)
 849                 return ret;
 850
 851         host->max_clk = clock;
 852
 853         host->mmc = &plat->mmc;
 854         host->mmc->dev = dev;
 855         host->mmc->priv = host;
 856
 857         ret = sdhci_setup_cfg(&plat->cfg, host, plat->cfg.f_max,
 858                               CONFIG_ZYNQ_SDHCI_MIN_FREQ);
 859         if (ret)
 860                 return ret;
 861         upriv->mmc = host->mmc;
 862
 863         /*
 864          * WORKAROUND: Versal platforms have an issue with card detect state.
 865          * Due to this, host controller is switching off voltage to sd card
 866          * causing sd card timeout error. Workaround this by adding a wait for
 867          * 1000msec till the card detect state gets stable.
 868          */
 869         if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) || IS_ENABLED(CONFIG_ARCH_VERSAL)) {
 870                 u32 timeout = 1000000;
 871
 872                 while (((sdhci_readl(host, SDHCI_PRESENT_STATE) &
 873                          SDHCI_CARD_STATE_STABLE) == 0) && timeout) {
 874                         udelay(1);
 875                         timeout--;
 876                 }
 877                 if (!timeout) {
 878                         dev_err(dev, "Sdhci card detect state not stable\n");
 879                         return -ETIMEDOUT;
 880                 }
 881         }
 882
 883         return sdhci_probe(dev);
 884 }
 885
 886 static int arasan_sdhci_of_to_plat(struct udevice *dev)
 887 {
 888         struct arasan_sdhci_priv *priv = dev_get_priv(dev);
 889
 890         priv->host = calloc(1, sizeof(struct sdhci_host));
 891         if (!priv->host)
 892                 return -1;
 893
 894         priv->host->name = dev->name;
 895
 896 #if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL)
 897         priv->host->ops = &arasan_ops;
 898         arasan_dt_parse_clk_phases(dev);
 899 #endif
 900
 901         priv->host->ioaddr = (void *)dev_read_addr(dev);
 902         if (IS_ERR(priv->host->ioaddr))
 903                 return PTR_ERR(priv->host->ioaddr);
 904
 905         priv->deviceid = dev_read_u32_default(dev, "xlnx,device_id", -1);
 906         priv->bank = dev_read_u32_default(dev, "xlnx,mio-bank", 0);
 907         priv->no_1p8 = dev_read_bool(dev, "no-1-8-v");
 908
 909         return 0;
 910 }
 911
 912 static int arasan_sdhci_bind(struct udevice *dev)
 913 {
 914         struct arasan_sdhci_plat *plat = dev_get_plat(dev);
 915
 916         return sdhci_bind(dev, &plat->mmc, &plat->cfg);
 917 }
 918
 919 static const struct udevice_id arasan_sdhci_ids[] = {
 920         { .compatible = "arasan,sdhci-8.9a" },
 921         { }
 922 };
 923
 924 U_BOOT_DRIVER(arasan_sdhci_drv) = {
 925         .name           = "arasan_sdhci",
 926         .id             = UCLASS_MMC,
 927         .of_match       = arasan_sdhci_ids,
 928         .of_to_plat = arasan_sdhci_of_to_plat,
 929         .ops            = &sdhci_ops,
 930         .bind           = arasan_sdhci_bind,
 931         .probe          = arasan_sdhci_probe,
 932         .priv_auto      = sizeof(struct arasan_sdhci_priv),
 933         .plat_auto      = sizeof(struct arasan_sdhci_plat),
 934 };