drivers/mmc/zynq_sdhci.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2013 - 2022, Xilinx, Inc.
   4  * (C) Copyright 2022, Advanced Micro Devices, Inc.
   5  *
   6  * Xilinx Zynq SD Host Controller Interface
   7  */
   8
   9 #include <clk.h>
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <fdtdec.h>
  13 #include <linux/delay.h>
  14 #include "mmc_private.h"
  15 #include <log.h>
  16 #include <reset.h>
  17 #include <asm/arch/sys_proto.h>
  18 #include <dm/device_compat.h>
  19 #include <linux/err.h>
  20 #include <linux/libfdt.h>
  21 #include <linux/iopoll.h>
  22 #include <asm/types.h>
  23 #include <linux/math64.h>
  24 #include <asm/cache.h>
  25 #include <malloc.h>
  26 #include <sdhci.h>
  27 #include <zynqmp_firmware.h>
  28
  29 #define SDHCI_ARASAN_ITAPDLY_REGISTER   0xF0F8
  30 #define SDHCI_ARASAN_ITAPDLY_SEL_MASK   GENMASK(7, 0)
  31 #define SDHCI_ARASAN_OTAPDLY_REGISTER   0xF0FC
  32 #define SDHCI_ARASAN_OTAPDLY_SEL_MASK   GENMASK(5, 0)
  33 #define SDHCI_ITAPDLY_CHGWIN            BIT(9)
  34 #define SDHCI_ITAPDLY_ENABLE            BIT(8)
  35 #define SDHCI_OTAPDLY_ENABLE            BIT(6)
  36
  37 #define SDHCI_TUNING_LOOP_COUNT         40
  38 #define MMC_BANK2                       0x2
  39
  40 #define SD_DLL_CTRL                     0xFF180358
  41 #define SD_ITAP_DLY                     0xFF180314
  42 #define SD_OTAP_DLY                     0xFF180318
  43 #define SD0_DLL_RST                     BIT(2)
  44 #define SD1_DLL_RST                     BIT(18)
  45 #define SD0_ITAPCHGWIN                  BIT(9)
  46 #define SD1_ITAPCHGWIN                  BIT(25)
  47 #define SD0_ITAPDLYENA                  BIT(8)
  48 #define SD1_ITAPDLYENA                  BIT(24)
  49 #define SD0_ITAPDLYSEL_MASK             GENMASK(7, 0)
  50 #define SD1_ITAPDLYSEL_MASK             GENMASK(23, 16)
  51 #define SD0_OTAPDLYSEL_MASK             GENMASK(5, 0)
  52 #define SD1_OTAPDLYSEL_MASK             GENMASK(21, 16)
  53
  54 #define MIN_PHY_CLK_HZ                  50000000
  55
  56 #define PHY_CTRL_REG1                   0x270
  57 #define PHY_CTRL_ITAPDLY_ENA_MASK       BIT(0)
  58 #define PHY_CTRL_ITAPDLY_SEL_MASK       GENMASK(5, 1)
  59 #define PHY_CTRL_ITAPDLY_SEL_SHIFT      1
  60 #define PHY_CTRL_ITAP_CHG_WIN_MASK      BIT(6)
  61 #define PHY_CTRL_OTAPDLY_ENA_MASK       BIT(8)
  62 #define PHY_CTRL_OTAPDLY_SEL_MASK       GENMASK(15, 12)
  63 #define PHY_CTRL_OTAPDLY_SEL_SHIFT      12
  64 #define PHY_CTRL_STRB_SEL_MASK          GENMASK(23, 16)
  65 #define PHY_CTRL_STRB_SEL_SHIFT         16
  66 #define PHY_CTRL_TEST_CTRL_MASK         GENMASK(31, 24)
  67
  68 #define PHY_CTRL_REG2                   0x274
  69 #define PHY_CTRL_EN_DLL_MASK            BIT(0)
  70 #define PHY_CTRL_DLL_RDY_MASK           BIT(1)
  71 #define PHY_CTRL_FREQ_SEL_MASK          GENMASK(6, 4)
  72 #define PHY_CTRL_FREQ_SEL_SHIFT         4
  73 #define PHY_CTRL_SEL_DLY_TX_MASK        BIT(16)
  74 #define PHY_CTRL_SEL_DLY_RX_MASK        BIT(17)
  75 #define FREQSEL_200M_170M               0x0
  76 #define FREQSEL_170M_140M               0x1
  77 #define FREQSEL_140M_110M               0x2
  78 #define FREQSEL_110M_80M                0x3
  79 #define FREQSEL_80M_50M                 0x4
  80 #define FREQSEL_275M_250M               0x5
  81 #define FREQSEL_250M_225M               0x6
  82 #define FREQSEL_225M_200M               0x7
  83 #define PHY_DLL_TIMEOUT_MS              100
  84
  85 #define VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLY_CHAIN      39
  86 #define VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLL            146
  87 #define VERSAL_NET_PHY_CTRL_STRB90_STRB180_VAL          0X77
  88
  89 struct arasan_sdhci_clk_data {
  90         int clk_phase_in[MMC_TIMING_MMC_HS400 + 1];
  91         int clk_phase_out[MMC_TIMING_MMC_HS400 + 1];
  92 };
  93
  94 struct arasan_sdhci_plat {
  95         struct mmc_config cfg;
  96         struct mmc mmc;
  97 };
  98
  99 struct arasan_sdhci_priv {
 100         struct sdhci_host *host;
 101         struct arasan_sdhci_clk_data clk_data;
 102         u32 node_id;
 103         u8 bank;
 104         u8 no_1p8;
 105         bool internal_phy_reg;
 106         struct reset_ctl_bulk resets;
 107 };
 108
 109 /* For Versal platforms zynqmp_mmio_write() won't be available */
 110 __weak int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value)
 111 {
 112         return 0;
 113 }
 114
 115 __weak int xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
 116                              u32 arg3, u32 *ret_payload)
 117 {
 118         return 0;
 119 }
 120
 121 __weak int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id)
 122 {
 123         return 1;
 124 }
 125
 126 #if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL) || defined(CONFIG_ARCH_VERSAL_NET)
 127 /* Default settings for ZynqMP Clock Phases */
 128 static const u32 zynqmp_iclk_phases[] = {0, 63, 63, 0, 63,  0,
 129                                          0, 183, 54,  0, 0};
 130 static const u32 zynqmp_oclk_phases[] = {0, 72, 60, 0, 60, 72,
 131                                          135, 48, 72, 135, 0};
 132
 133 /* Default settings for Versal Clock Phases */
 134 static const u32 versal_iclk_phases[] = {0, 132, 132, 0, 132,
 135                                          0, 0, 162, 90, 0, 0};
 136 static const u32 versal_oclk_phases[] = {0,  60, 48, 0, 48, 72,
 137                                          90, 36, 60, 90, 0};
 138
 139 /* Default settings for versal-net eMMC Clock Phases */
 140 static const u32 versal_net_emmc_iclk_phases[] = {0, 0, 0, 0, 0, 0, 0, 0, 39,
 141                                                   0, 0};
 142 static const u32 versal_net_emmc_oclk_phases[] = {0, 113, 0, 0, 0, 0, 0, 0,
 143                                                   113, 79, 45};
 144
 145 static const u8 mode2timing[] = {
 146         [MMC_LEGACY] = MMC_TIMING_LEGACY,
 147         [MMC_HS] = MMC_TIMING_MMC_HS,
 148         [SD_HS] = MMC_TIMING_SD_HS,
 149         [MMC_HS_52] = MMC_TIMING_MMC_HS,
 150         [MMC_DDR_52] = MMC_TIMING_MMC_DDR52,
 151         [UHS_SDR12] = MMC_TIMING_UHS_SDR12,
 152         [UHS_SDR25] = MMC_TIMING_UHS_SDR25,
 153         [UHS_SDR50] = MMC_TIMING_UHS_SDR50,
 154         [UHS_DDR50] = MMC_TIMING_UHS_DDR50,
 155         [UHS_SDR104] = MMC_TIMING_UHS_SDR104,
 156         [MMC_HS_200] = MMC_TIMING_MMC_HS200,
 157         [MMC_HS_400] = MMC_TIMING_MMC_HS400,
 158 };
 159
 160 #if defined(CONFIG_ARCH_VERSAL_NET)
 161 /**
 162  * arasan_phy_set_delaychain - Set eMMC delay chain based Input/Output clock
 163  *
 164  * @host:       Pointer to the sdhci_host structure
 165  * @enable:     Enable or disable Delay chain based Tx and Rx clock
 166  * Return:      None
 167  *
 168  * Enable or disable eMMC delay chain based Input and Output clock in
 169  * PHY_CTRL_REG2
 170  */
 171 static void arasan_phy_set_delaychain(struct sdhci_host *host, bool enable)
 172 {
 173         u32 reg;
 174
 175         reg = sdhci_readw(host, PHY_CTRL_REG2);
 176         if (enable)
 177                 reg |= PHY_CTRL_SEL_DLY_TX_MASK | PHY_CTRL_SEL_DLY_RX_MASK;
 178         else
 179                 reg &= ~(PHY_CTRL_SEL_DLY_TX_MASK | PHY_CTRL_SEL_DLY_RX_MASK);
 180
 181         sdhci_writew(host, reg, PHY_CTRL_REG2);
 182 }
 183
 184 /**
 185  * arasan_phy_set_dll - Set eMMC DLL clock
 186  *
 187  * @host:       Pointer to the sdhci_host structure
 188  * @enable:     Enable or disable DLL clock
 189  * Return:      0 if success or timeout error
 190  *
 191  * Enable or disable eMMC DLL clock in PHY_CTRL_REG2. When DLL enable is
 192  * set, wait till DLL is locked
 193  */
 194 static int arasan_phy_set_dll(struct sdhci_host *host, bool enable)
 195 {
 196         u32 reg;
 197
 198         reg = sdhci_readw(host, PHY_CTRL_REG2);
 199         if (enable)
 200                 reg |= PHY_CTRL_EN_DLL_MASK;
 201         else
 202                 reg &= ~PHY_CTRL_EN_DLL_MASK;
 203
 204         sdhci_writew(host, reg, PHY_CTRL_REG2);
 205
 206         /* If DLL is disabled return success */
 207         if (!enable)
 208                 return 0;
 209
 210         /* If DLL is enabled wait till DLL loop is locked, which is
 211          * indicated by dll_rdy bit(bit1) in PHY_CTRL_REG2
 212          */
 213         return readl_relaxed_poll_timeout(host->ioaddr + PHY_CTRL_REG2, reg,
 214                                           (reg & PHY_CTRL_DLL_RDY_MASK),
 215                                           1000 * PHY_DLL_TIMEOUT_MS);
 216 }
 217
 218 /**
 219  * arasan_phy_dll_set_freq - Select frequency range of DLL for eMMC
 220  *
 221  * @host:       Pointer to the sdhci_host structure
 222  * @clock:      clock value
 223  * Return:      None
 224  *
 225  * Set frequency range bits based on the selected clock for eMMC
 226  */
 227 static void arasan_phy_dll_set_freq(struct sdhci_host *host, int clock)
 228 {
 229         u32 reg, freq_sel, freq;
 230
 231         freq = DIV_ROUND_CLOSEST(clock, 1000000);
 232         if (freq <= 200 && freq > 170)
 233                 freq_sel = FREQSEL_200M_170M;
 234         else if (freq <= 170 && freq > 140)
 235                 freq_sel = FREQSEL_170M_140M;
 236         else if (freq <= 140 && freq > 110)
 237                 freq_sel = FREQSEL_140M_110M;
 238         else if (freq <= 110 && freq > 80)
 239                 freq_sel = FREQSEL_110M_80M;
 240         else
 241                 freq_sel = FREQSEL_80M_50M;
 242
 243         reg = sdhci_readw(host, PHY_CTRL_REG2);
 244         reg &= ~PHY_CTRL_FREQ_SEL_MASK;
 245         reg |= (freq_sel << PHY_CTRL_FREQ_SEL_SHIFT);
 246         sdhci_writew(host, reg, PHY_CTRL_REG2);
 247 }
 248
 249 static int arasan_sdhci_config_dll(struct sdhci_host *host, unsigned int clock, bool enable)
 250 {
 251         struct mmc *mmc = (struct mmc *)host->mmc;
 252         struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
 253
 254         if (enable) {
 255                 if (priv->internal_phy_reg && clock >= MIN_PHY_CLK_HZ && enable)
 256                         arasan_phy_set_dll(host, 1);
 257                 return 0;
 258         }
 259
 260         if (priv->internal_phy_reg && clock >= MIN_PHY_CLK_HZ) {
 261                 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 262                 arasan_phy_set_dll(host, 0);
 263                 arasan_phy_set_delaychain(host, 0);
 264                 arasan_phy_dll_set_freq(host, clock);
 265                 return 0;
 266         }
 267
 268         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 269         arasan_phy_set_delaychain(host, 1);
 270
 271         return 0;
 272 }
 273 #endif
 274
 275 static inline int arasan_zynqmp_set_in_tapdelay(u32 node_id, u32 itap_delay)
 276 {
 277         int ret;
 278
 279         if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
 280                 if (node_id == NODE_SD_0) {
 281                         ret = zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN,
 282                                                 SD0_ITAPCHGWIN);
 283                         if (ret)
 284                                 return ret;
 285
 286                         ret = zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA,
 287                                                 SD0_ITAPDLYENA);
 288                         if (ret)
 289                                 return ret;
 290
 291                         ret = zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK,
 292                                                 itap_delay);
 293                         if (ret)
 294                                 return ret;
 295
 296                         ret = zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN, 0);
 297                         if (ret)
 298                                 return ret;
 299                 }
 300                 ret = zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN,
 301                                         SD1_ITAPCHGWIN);
 302                 if (ret)
 303                         return ret;
 304
 305                 ret = zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA,
 306                                         SD1_ITAPDLYENA);
 307                 if (ret)
 308                         return ret;
 309
 310                 ret = zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
 311                                         (itap_delay << 16));
 312                 if (ret)
 313                         return ret;
 314
 315                 ret = zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN, 0);
 316                 if (ret)
 317                         return ret;
 318         } else {
 319                 return xilinx_pm_request(PM_IOCTL, node_id,
 320                                          IOCTL_SET_SD_TAPDELAY,
 321                                          PM_TAPDELAY_INPUT, itap_delay, NULL);
 322         }
 323
 324         return 0;
 325 }
 326
 327 static inline int arasan_zynqmp_set_out_tapdelay(u32 node_id, u32 otap_delay)
 328 {
 329         if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
 330                 if (node_id == NODE_SD_0)
 331                         return zynqmp_mmio_write(SD_OTAP_DLY,
 332                                                  SD0_OTAPDLYSEL_MASK,
 333                                                  otap_delay);
 334
 335                 return zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
 336                                          (otap_delay << 16));
 337         } else {
 338                 return xilinx_pm_request(PM_IOCTL, node_id,
 339                                          IOCTL_SET_SD_TAPDELAY,
 340                                          PM_TAPDELAY_OUTPUT, otap_delay, NULL);
 341         }
 342 }
 343
 344 static inline int zynqmp_dll_reset(u32 node_id, u32 type)
 345 {
 346         if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
 347                 if (node_id == NODE_SD_0)
 348                         return zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST,
 349                                                  type == PM_DLL_RESET_ASSERT ?
 350                                                  SD0_DLL_RST : 0);
 351
 352                 return zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST,
 353                                          type == PM_DLL_RESET_ASSERT ?
 354                                          SD1_DLL_RST : 0);
 355         } else {
 356                 return xilinx_pm_request(PM_IOCTL, node_id,
 357                                          IOCTL_SD_DLL_RESET, type, 0, NULL);
 358         }
 359 }
 360
 361 static int arasan_zynqmp_dll_reset(struct sdhci_host *host, u32 node_id)
 362 {
 363         struct mmc *mmc = (struct mmc *)host->mmc;
 364         struct udevice *dev = mmc->dev;
 365         unsigned long timeout;
 366         int ret;
 367         u16 clk;
 368
 369         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
 370         clk &= ~(SDHCI_CLOCK_CARD_EN);
 371         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 372
 373         /* Issue DLL Reset */
 374         ret = zynqmp_dll_reset(node_id, PM_DLL_RESET_ASSERT);
 375         if (ret) {
 376                 dev_err(dev, "dll_reset assert failed with err: %d\n", ret);
 377                 return ret;
 378         }
 379
 380         /* Allow atleast 1ms delay for proper DLL reset */
 381         mdelay(1);
 382         ret = zynqmp_dll_reset(node_id, PM_DLL_RESET_RELEASE);
 383         if (ret) {
 384                 dev_err(dev, "dll_reset release failed with err: %d\n", ret);
 385                 return ret;
 386         }
 387
 388         /* Wait max 20 ms */
 389         timeout = 100;
 390         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
 391                                 & SDHCI_CLOCK_INT_STABLE)) {
 392                 if (timeout == 0) {
 393                         dev_err(dev, ": Internal clock never stabilised.\n");
 394                         return -EBUSY;
 395                 }
 396                 timeout--;
 397                 udelay(1000);
 398         }
 399
 400         clk |= SDHCI_CLOCK_CARD_EN;
 401         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 402
 403         return 0;
 404 }
 405
 406 static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
 407 {
 408         struct mmc_cmd cmd;
 409         struct mmc_data data;
 410         u32 ctrl;
 411         struct sdhci_host *host;
 412         struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
 413         int tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
 414
 415         dev_dbg(mmc->dev, "%s\n", __func__);
 416
 417         host = priv->host;
 418
 419         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 420         ctrl |= SDHCI_CTRL_EXEC_TUNING;
 421         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
 422
 423         mdelay(1);
 424
 425         arasan_zynqmp_dll_reset(host, priv->node_id);
 426
 427         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
 428         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
 429
 430         do {
 431                 cmd.cmdidx = opcode;
 432                 cmd.resp_type = MMC_RSP_R1;
 433                 cmd.cmdarg = 0;
 434
 435                 data.blocksize = 64;
 436                 data.blocks = 1;
 437                 data.flags = MMC_DATA_READ;
 438
 439                 if (tuning_loop_counter-- == 0)
 440                         break;
 441
 442                 if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200 &&
 443                     mmc->bus_width == 8)
 444                         data.blocksize = 128;
 445
 446                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 447                                                     data.blocksize),
 448                              SDHCI_BLOCK_SIZE);
 449                 sdhci_writew(host, data.blocks, SDHCI_BLOCK_COUNT);
 450                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
 451
 452                 mmc_send_cmd(mmc, &cmd, NULL);
 453                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 454
 455                 if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
 456                         udelay(1);
 457
 458         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
 459
 460         if (tuning_loop_counter < 0) {
 461                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
 462                 sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL2);
 463         }
 464
 465         if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
 466                 printf("%s:Tuning failed\n", __func__);
 467                 return -1;
 468         }
 469
 470         udelay(1);
 471         arasan_zynqmp_dll_reset(host, priv->node_id);
 472
 473         /* Enable only interrupts served by the SD controller */
 474         sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
 475                      SDHCI_INT_ENABLE);
 476         /* Mask all sdhci interrupt sources */
 477         sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
 478
 479         return 0;
 480 }
 481
 482 /**
 483  * sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
 484  *
 485  * @host:               Pointer to the sdhci_host structure.
 486  * @degrees:            The clock phase shift between 0 - 359.
 487  * Return: 0
 488  *
 489  * Set the SD Output Clock Tap Delays for Output path
 490  */
 491 static int sdhci_zynqmp_sdcardclk_set_phase(struct sdhci_host *host,
 492                                             int degrees)
 493 {
 494         struct mmc *mmc = (struct mmc *)host->mmc;
 495         struct udevice *dev = mmc->dev;
 496         struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
 497         u8 tap_delay, tap_max = 0;
 498         int timing = mode2timing[mmc->selected_mode];
 499         int ret;
 500
 501         /*
 502          * This is applicable for SDHCI_SPEC_300 and above
 503          * ZynqMP does not set phase for <=25MHz clock.
 504          * If degrees is zero, no need to do anything.
 505          */
 506         if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
 507                 return 0;
 508
 509         switch (timing) {
 510         case MMC_TIMING_MMC_HS:
 511         case MMC_TIMING_SD_HS:
 512         case MMC_TIMING_UHS_SDR25:
 513         case MMC_TIMING_UHS_DDR50:
 514         case MMC_TIMING_MMC_DDR52:
 515                 /* For 50MHz clock, 30 Taps are available */
 516                 tap_max = 30;
 517                 break;
 518         case MMC_TIMING_UHS_SDR50:
 519                 /* For 100MHz clock, 15 Taps are available */
 520                 tap_max = 15;
 521                 break;
 522         case MMC_TIMING_UHS_SDR104:
 523         case MMC_TIMING_MMC_HS200:
 524                 /* For 200MHz clock, 8 Taps are available */
 525                 tap_max = 8;
 526         default:
 527                 break;
 528         }
 529
 530         tap_delay = (degrees * tap_max) / 360;
 531
 532         /* Limit output tap_delay value to 6 bits */
 533         tap_delay &= SDHCI_ARASAN_OTAPDLY_SEL_MASK;
 534
 535         /* Set the Clock Phase */
 536         ret = arasan_zynqmp_set_out_tapdelay(priv->node_id, tap_delay);
 537         if (ret) {
 538                 dev_err(dev, "Error setting output Tap Delay\n");
 539                 return ret;
 540         }
 541
 542         /* Release DLL Reset */
 543         ret = zynqmp_dll_reset(priv->node_id, PM_DLL_RESET_RELEASE);
 544         if (ret) {
 545                 dev_err(dev, "dll_reset release failed with err: %d\n", ret);
 546                 return ret;
 547         }
 548
 549         return 0;
 550 }
 551
 552 /**
 553  * sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays
 554  *
 555  * @host:               Pointer to the sdhci_host structure.
 556  * @degrees:            The clock phase shift between 0 - 359.
 557  * Return: 0
 558  *
 559  * Set the SD Input Clock Tap Delays for Input path
 560  */
 561 static int sdhci_zynqmp_sampleclk_set_phase(struct sdhci_host *host,
 562                                             int degrees)
 563 {
 564         struct mmc *mmc = (struct mmc *)host->mmc;
 565         struct udevice *dev = mmc->dev;
 566         struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
 567         u8 tap_delay, tap_max = 0;
 568         int timing = mode2timing[mmc->selected_mode];
 569         int ret;
 570
 571         /*
 572          * This is applicable for SDHCI_SPEC_300 and above
 573          * ZynqMP does not set phase for <=25MHz clock.
 574          * If degrees is zero, no need to do anything.
 575          */
 576         if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
 577                 return 0;
 578
 579         /* Assert DLL Reset */
 580         ret = zynqmp_dll_reset(priv->node_id, PM_DLL_RESET_ASSERT);
 581         if (ret) {
 582                 dev_err(dev, "dll_reset assert failed with err: %d\n", ret);
 583                 return ret;
 584         }
 585
 586         switch (timing) {
 587         case MMC_TIMING_MMC_HS:
 588         case MMC_TIMING_SD_HS:
 589         case MMC_TIMING_UHS_SDR25:
 590         case MMC_TIMING_UHS_DDR50:
 591         case MMC_TIMING_MMC_DDR52:
 592                 /* For 50MHz clock, 120 Taps are available */
 593                 tap_max = 120;
 594                 break;
 595         case MMC_TIMING_UHS_SDR50:
 596                 /* For 100MHz clock, 60 Taps are available */
 597                 tap_max = 60;
 598                 break;
 599         case MMC_TIMING_UHS_SDR104:
 600         case MMC_TIMING_MMC_HS200:
 601                 /* For 200MHz clock, 30 Taps are available */
 602                 tap_max = 30;
 603         default:
 604                 break;
 605         }
 606
 607         tap_delay = (degrees * tap_max) / 360;
 608
 609         /* Limit input tap_delay value to 8 bits */
 610         tap_delay &= SDHCI_ARASAN_ITAPDLY_SEL_MASK;
 611
 612         ret = arasan_zynqmp_set_in_tapdelay(priv->node_id, tap_delay);
 613         if (ret) {
 614                 dev_err(dev, "Error setting Input Tap Delay\n");
 615                 return ret;
 616         }
 617
 618         return 0;
 619 }
 620
 621 /**
 622  * sdhci_versal_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
 623  *
 624  * @host:               Pointer to the sdhci_host structure.
 625  * @degrees:            The clock phase shift between 0 - 359.
 626  * Return: 0
 627  *
 628  * Set the SD Output Clock Tap Delays for Output path
 629  */
 630 static int sdhci_versal_sdcardclk_set_phase(struct sdhci_host *host,
 631                                             int degrees)
 632 {
 633         struct mmc *mmc = (struct mmc *)host->mmc;
 634         u8 tap_delay, tap_max = 0;
 635         int timing = mode2timing[mmc->selected_mode];
 636         u32 regval;
 637
 638         /*
 639          * This is applicable for SDHCI_SPEC_300 and above
 640          * Versal does not set phase for <=25MHz clock.
 641          * If degrees is zero, no need to do anything.
 642          */
 643         if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
 644                 return 0;
 645
 646         switch (timing) {
 647         case MMC_TIMING_MMC_HS:
 648         case MMC_TIMING_SD_HS:
 649         case MMC_TIMING_UHS_SDR25:
 650         case MMC_TIMING_UHS_DDR50:
 651         case MMC_TIMING_MMC_DDR52:
 652                 /* For 50MHz clock, 30 Taps are available */
 653                 tap_max = 30;
 654                 break;
 655         case MMC_TIMING_UHS_SDR50:
 656                 /* For 100MHz clock, 15 Taps are available */
 657                 tap_max = 15;
 658                 break;
 659         case MMC_TIMING_UHS_SDR104:
 660         case MMC_TIMING_MMC_HS200:
 661                 /* For 200MHz clock, 8 Taps are available */
 662                 tap_max = 8;
 663         default:
 664                 break;
 665         }
 666
 667         tap_delay = (degrees * tap_max) / 360;
 668
 669         /* Limit output tap_delay value to 6 bits */
 670         tap_delay &= SDHCI_ARASAN_OTAPDLY_SEL_MASK;
 671
 672         /* Set the Clock Phase */
 673         regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER);
 674         regval |= SDHCI_OTAPDLY_ENABLE;
 675         sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
 676         regval &= ~SDHCI_ARASAN_OTAPDLY_SEL_MASK;
 677         regval |= tap_delay;
 678         sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
 679
 680         return 0;
 681 }
 682
 683 /**
 684  * sdhci_versal_sampleclk_set_phase - Set the SD Input Clock Tap Delays
 685  *
 686  * @host:               Pointer to the sdhci_host structure.
 687  * @degrees:            The clock phase shift between 0 - 359.
 688  * Return: 0
 689  *
 690  * Set the SD Input Clock Tap Delays for Input path
 691  */
 692 static int sdhci_versal_sampleclk_set_phase(struct sdhci_host *host,
 693                                             int degrees)
 694 {
 695         struct mmc *mmc = (struct mmc *)host->mmc;
 696         u8 tap_delay, tap_max = 0;
 697         int timing = mode2timing[mmc->selected_mode];
 698         u32 regval;
 699
 700         /*
 701          * This is applicable for SDHCI_SPEC_300 and above
 702          * Versal does not set phase for <=25MHz clock.
 703          * If degrees is zero, no need to do anything.
 704          */
 705         if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
 706                 return 0;
 707
 708         switch (timing) {
 709         case MMC_TIMING_MMC_HS:
 710         case MMC_TIMING_SD_HS:
 711         case MMC_TIMING_UHS_SDR25:
 712         case MMC_TIMING_UHS_DDR50:
 713         case MMC_TIMING_MMC_DDR52:
 714                 /* For 50MHz clock, 120 Taps are available */
 715                 tap_max = 120;
 716                 break;
 717         case MMC_TIMING_UHS_SDR50:
 718                 /* For 100MHz clock, 60 Taps are available */
 719                 tap_max = 60;
 720                 break;
 721         case MMC_TIMING_UHS_SDR104:
 722         case MMC_TIMING_MMC_HS200:
 723                 /* For 200MHz clock, 30 Taps are available */
 724                 tap_max = 30;
 725         default:
 726                 break;
 727         }
 728
 729         tap_delay = (degrees * tap_max) / 360;
 730
 731         /* Limit input tap_delay value to 8 bits */
 732         tap_delay &= SDHCI_ARASAN_ITAPDLY_SEL_MASK;
 733
 734         /* Set the Clock Phase */
 735         regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER);
 736         regval |= SDHCI_ITAPDLY_CHGWIN;
 737         sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
 738         regval |= SDHCI_ITAPDLY_ENABLE;
 739         sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
 740         regval &= ~SDHCI_ARASAN_ITAPDLY_SEL_MASK;
 741         regval |= tap_delay;
 742         sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
 743         regval &= ~SDHCI_ITAPDLY_CHGWIN;
 744         sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
 745
 746         return 0;
 747 }
 748
 749 /**
 750  * sdhci_versal_net_emmc_sdcardclk_set_phase - Set eMMC Output Clock Tap Delays
 751  *
 752  * @host:               Pointer to the sdhci_host structure.
 753  * @degrees:            The clock phase shift between 0 - 359.
 754  * Return: 0
 755  *
 756  * Set eMMC Output Clock Tap Delays for Output path
 757  */
 758 static int sdhci_versal_net_emmc_sdcardclk_set_phase(struct sdhci_host *host, int degrees)
 759 {
 760         struct mmc *mmc = (struct mmc *)host->mmc;
 761         int timing = mode2timing[mmc->selected_mode];
 762         u8 tap_delay, tap_max = 0;
 763         u32 regval;
 764
 765         switch (timing) {
 766         case MMC_TIMING_MMC_HS:
 767         case MMC_TIMING_MMC_DDR52:
 768                 tap_max = 16;
 769                 break;
 770         case MMC_TIMING_MMC_HS200:
 771         case MMC_TIMING_MMC_HS400:
 772                  /* For 200MHz clock, 32 Taps are available */
 773                 tap_max = 32;
 774                 break;
 775         default:
 776                 break;
 777         }
 778
 779         tap_delay = (degrees * tap_max) / 360;
 780         /* Set the Clock Phase */
 781         if (tap_delay) {
 782                 regval = sdhci_readl(host, PHY_CTRL_REG1);
 783                 regval |= PHY_CTRL_OTAPDLY_ENA_MASK;
 784                 sdhci_writel(host, regval, PHY_CTRL_REG1);
 785                 regval &= ~PHY_CTRL_OTAPDLY_SEL_MASK;
 786                 regval |= tap_delay << PHY_CTRL_OTAPDLY_SEL_SHIFT;
 787                 sdhci_writel(host, regval, PHY_CTRL_REG1);
 788         }
 789
 790         return 0;
 791 }
 792
 793 /**
 794  * sdhci_versal_net_emmc_sampleclk_set_phase - Set eMMC Input Clock Tap Delays
 795  *
 796  * @host:               Pointer to the sdhci_host structure.
 797  * @degrees:            The clock phase shift between 0 - 359.
 798  * Return: 0
 799  *
 800  * Set eMMC Input Clock Tap Delays for Input path. If HS400 is selected,
 801  * set strobe90 and strobe180 in PHY_CTRL_REG1.
 802  */
 803 static int sdhci_versal_net_emmc_sampleclk_set_phase(struct sdhci_host *host, int degrees)
 804 {
 805         struct mmc *mmc = (struct mmc *)host->mmc;
 806         int timing = mode2timing[mmc->selected_mode];
 807         u8 tap_delay, tap_max = 0;
 808         u32 regval;
 809
 810         switch (timing) {
 811         case MMC_TIMING_MMC_HS:
 812         case MMC_TIMING_MMC_DDR52:
 813                 tap_max = 32;
 814                 break;
 815         case MMC_TIMING_MMC_HS400:
 816                 /* Strobe select tap point for strb90 and strb180 */
 817                 regval = sdhci_readl(host, PHY_CTRL_REG1);
 818                 regval &= ~PHY_CTRL_STRB_SEL_MASK;
 819                 regval |= VERSAL_NET_PHY_CTRL_STRB90_STRB180_VAL << PHY_CTRL_STRB_SEL_SHIFT;
 820                 sdhci_writel(host, regval, PHY_CTRL_REG1);
 821                 break;
 822         default:
 823                 break;
 824         }
 825
 826         tap_delay = (degrees * tap_max) / 360;
 827         /* Set the Clock Phase */
 828         if (tap_delay) {
 829                 regval = sdhci_readl(host, PHY_CTRL_REG1);
 830                 regval |= PHY_CTRL_ITAP_CHG_WIN_MASK;
 831                 sdhci_writel(host, regval, PHY_CTRL_REG1);
 832                 regval |= PHY_CTRL_ITAPDLY_ENA_MASK;
 833                 sdhci_writel(host, regval, PHY_CTRL_REG1);
 834                 regval &= ~PHY_CTRL_ITAPDLY_SEL_MASK;
 835                 regval |= tap_delay << PHY_CTRL_ITAPDLY_SEL_SHIFT;
 836                 sdhci_writel(host, regval, PHY_CTRL_REG1);
 837                 regval &= ~PHY_CTRL_ITAP_CHG_WIN_MASK;
 838                 sdhci_writel(host, regval, PHY_CTRL_REG1);
 839         }
 840
 841         return 0;
 842 }
 843
 844 static int arasan_sdhci_set_tapdelay(struct sdhci_host *host)
 845 {
 846         struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
 847         struct arasan_sdhci_clk_data *clk_data = &priv->clk_data;
 848         struct mmc *mmc = (struct mmc *)host->mmc;
 849         struct udevice *dev = mmc->dev;
 850         u8 timing = mode2timing[mmc->selected_mode];
 851         u32 iclk_phase = clk_data->clk_phase_in[timing];
 852         u32 oclk_phase = clk_data->clk_phase_out[timing];
 853         int ret;
 854
 855         dev_dbg(dev, "%s, host:%s, mode:%d\n", __func__, host->name, timing);
 856
 857         if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) &&
 858             device_is_compatible(dev, "xlnx,zynqmp-8.9a")) {
 859                 ret = sdhci_zynqmp_sampleclk_set_phase(host, iclk_phase);
 860                 if (ret)
 861                         return ret;
 862
 863                 ret = sdhci_zynqmp_sdcardclk_set_phase(host, oclk_phase);
 864                 if (ret)
 865                         return ret;
 866         } else if (IS_ENABLED(CONFIG_ARCH_VERSAL) &&
 867                    device_is_compatible(dev, "xlnx,versal-8.9a")) {
 868                 ret = sdhci_versal_sampleclk_set_phase(host, iclk_phase);
 869                 if (ret)
 870                         return ret;
 871
 872                 ret = sdhci_versal_sdcardclk_set_phase(host, oclk_phase);
 873                 if (ret)
 874                         return ret;
 875         } else if (IS_ENABLED(CONFIG_ARCH_VERSAL_NET) &&
 876                    device_is_compatible(dev, "xlnx,versal-net-5.1-emmc")) {
 877                 if (mmc->clock >= MIN_PHY_CLK_HZ)
 878                         if (iclk_phase == VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLY_CHAIN)
 879                                 iclk_phase = VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLL;
 880
 881                 ret = sdhci_versal_net_emmc_sampleclk_set_phase(host, iclk_phase);
 882                 if (ret)
 883                         return ret;
 884
 885                 ret = sdhci_versal_net_emmc_sdcardclk_set_phase(host, oclk_phase);
 886                 if (ret)
 887                         return ret;
 888         }
 889
 890         return 0;
 891 }
 892
 893 static void arasan_dt_read_clk_phase(struct udevice *dev, unsigned char timing,
 894                                      const char *prop)
 895 {
 896         struct arasan_sdhci_priv *priv = dev_get_priv(dev);
 897         struct arasan_sdhci_clk_data *clk_data = &priv->clk_data;
 898         u32 clk_phase[2] = {0};
 899
 900         /*
 901          * Read Tap Delay values from DT, if the DT does not contain the
 902          * Tap Values then use the pre-defined values
 903          */
 904         if (dev_read_u32_array(dev, prop, &clk_phase[0], 2)) {
 905                 dev_dbg(dev, "Using predefined clock phase for %s = %d %d\n",
 906                         prop, clk_data->clk_phase_in[timing],
 907                         clk_data->clk_phase_out[timing]);
 908                 return;
 909         }
 910
 911         /* The values read are Input and Output Clock Delays in order */
 912         clk_data->clk_phase_in[timing] = clk_phase[0];
 913         clk_data->clk_phase_out[timing] = clk_phase[1];
 914 }
 915
 916 /**
 917  * arasan_dt_parse_clk_phases - Read Tap Delay values from DT
 918  *
 919  * @dev:                Pointer to our struct udevice.
 920  *
 921  * Called at initialization to parse the values of Tap Delays.
 922  */
 923 static void arasan_dt_parse_clk_phases(struct udevice *dev)
 924 {
 925         struct arasan_sdhci_priv *priv = dev_get_priv(dev);
 926         struct arasan_sdhci_clk_data *clk_data = &priv->clk_data;
 927         int i;
 928
 929         if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) &&
 930             device_is_compatible(dev, "xlnx,zynqmp-8.9a")) {
 931                 for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
 932                         clk_data->clk_phase_in[i] = zynqmp_iclk_phases[i];
 933                         clk_data->clk_phase_out[i] = zynqmp_oclk_phases[i];
 934                 }
 935
 936                 if (priv->bank == MMC_BANK2) {
 937                         clk_data->clk_phase_out[MMC_TIMING_UHS_SDR104] = 90;
 938                         clk_data->clk_phase_out[MMC_TIMING_MMC_HS200] = 90;
 939                 }
 940         }
 941
 942         if (IS_ENABLED(CONFIG_ARCH_VERSAL) &&
 943             device_is_compatible(dev, "xlnx,versal-8.9a")) {
 944                 for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
 945                         clk_data->clk_phase_in[i] = versal_iclk_phases[i];
 946                         clk_data->clk_phase_out[i] = versal_oclk_phases[i];
 947                 }
 948         }
 949
 950         if (IS_ENABLED(CONFIG_ARCH_VERSAL_NET) &&
 951             device_is_compatible(dev, "xlnx,versal-net-5.1-emmc")) {
 952                 for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
 953                         clk_data->clk_phase_in[i] = versal_net_emmc_iclk_phases[i];
 954                         clk_data->clk_phase_out[i] = versal_net_emmc_oclk_phases[i];
 955                 }
 956         }
 957
 958         arasan_dt_read_clk_phase(dev, MMC_TIMING_LEGACY,
 959                                  "clk-phase-legacy");
 960         arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_HS,
 961                                  "clk-phase-mmc-hs");
 962         arasan_dt_read_clk_phase(dev, MMC_TIMING_SD_HS,
 963                                  "clk-phase-sd-hs");
 964         arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR12,
 965                                  "clk-phase-uhs-sdr12");
 966         arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR25,
 967                                  "clk-phase-uhs-sdr25");
 968         arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR50,
 969                                  "clk-phase-uhs-sdr50");
 970         arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR104,
 971                                  "clk-phase-uhs-sdr104");
 972         arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_DDR50,
 973                                  "clk-phase-uhs-ddr50");
 974         arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_DDR52,
 975                                  "clk-phase-mmc-ddr52");
 976         arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_HS200,
 977                                  "clk-phase-mmc-hs200");
 978         arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_HS400,
 979                                  "clk-phase-mmc-hs400");
 980 }
 981
 982 static const struct sdhci_ops arasan_ops = {
 983         .platform_execute_tuning        = &arasan_sdhci_execute_tuning,
 984         .set_delay = &arasan_sdhci_set_tapdelay,
 985         .set_control_reg = &sdhci_set_control_reg,
 986 #if defined(CONFIG_ARCH_VERSAL_NET)
 987         .config_dll = &arasan_sdhci_config_dll,
 988 #endif
 989 };
 990 #endif
 991
 992 #if defined(CONFIG_ARCH_ZYNQMP) && defined(CONFIG_ZYNQMP_FIRMWARE)
 993 static int sdhci_zynqmp_set_dynamic_config(struct arasan_sdhci_priv *priv,
 994                                            struct udevice *dev)
 995 {
 996         int ret;
 997         struct clk clk;
 998         unsigned long clock, mhz;
 999
1000         ret = xilinx_pm_request(PM_REQUEST_NODE, priv->node_id,
1001                                 ZYNQMP_PM_CAPABILITY_ACCESS, ZYNQMP_PM_MAX_QOS,
1002                                 ZYNQMP_PM_REQUEST_ACK_NO, NULL);
1003         if (ret) {
1004                 dev_err(dev, "Request node failed for %d\n", priv->node_id);
1005                 return ret;
1006         }
1007
1008         ret = reset_get_bulk(dev, &priv->resets);
1009         if (ret == -ENOTSUPP || ret == -ENOENT) {
1010                 dev_err(dev, "Reset not found\n");
1011                 return 0;
1012         } else if (ret) {
1013                 dev_err(dev, "Reset failed\n");
1014                 return ret;
1015         }
1016
1017         ret = reset_assert_bulk(&priv->resets);
1018         if (ret) {
1019                 dev_err(dev, "Reset assert failed\n");
1020                 return ret;
1021         }
1022
1023         ret = zynqmp_pm_set_sd_config(priv->node_id, SD_CONFIG_FIXED, 0);
1024         if (ret) {
1025                 dev_err(dev, "SD_CONFIG_FIXED failed\n");
1026                 return ret;
1027         }
1028
1029         ret = zynqmp_pm_set_sd_config(priv->node_id, SD_CONFIG_EMMC_SEL,
1030                                       dev_read_bool(dev, "non-removable"));
1031         if (ret) {
1032                 dev_err(dev, "SD_CONFIG_EMMC_SEL failed\n");
1033                 return ret;
1034         }
1035
1036         ret = clk_get_by_index(dev, 0, &clk);
1037         if (ret < 0) {
1038                 dev_err(dev, "failed to get clock\n");
1039                 return ret;
1040         }
1041
1042         clock = clk_get_rate(&clk);
1043         if (IS_ERR_VALUE(clock)) {
1044                 dev_err(dev, "failed to get rate\n");
1045                 return clock;
1046         }
1047
1048         mhz = DIV64_U64_ROUND_UP(clock, 1000000);
1049
1050         if (mhz > 100 && mhz <= 200)
1051                 mhz = 200;
1052         else if (mhz > 50 && mhz <= 100)
1053                 mhz = 100;
1054         else if (mhz > 25 && mhz <= 50)
1055                 mhz = 50;
1056         else
1057                 mhz = 25;
1058
1059         ret = zynqmp_pm_set_sd_config(priv->node_id, SD_CONFIG_BASECLK, mhz);
1060         if (ret) {
1061                 dev_err(dev, "SD_CONFIG_BASECLK failed\n");
1062                 return ret;
1063         }
1064
1065         ret = zynqmp_pm_set_sd_config(priv->node_id, SD_CONFIG_8BIT,
1066                                       (dev_read_u32_default(dev, "bus-width", 1) == 8));
1067         if (ret) {
1068                 dev_err(dev, "SD_CONFIG_8BIT failed\n");
1069                 return ret;
1070         }
1071
1072         ret = reset_deassert_bulk(&priv->resets);
1073         if (ret) {
1074                 dev_err(dev, "Reset release failed\n");
1075                 return ret;
1076         }
1077
1078         return 0;
1079 }
1080 #endif
1081
1082 static int arasan_sdhci_probe(struct udevice *dev)
1083 {
1084         struct arasan_sdhci_plat *plat = dev_get_plat(dev);
1085         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1086         struct arasan_sdhci_priv *priv = dev_get_priv(dev);
1087         struct sdhci_host *host;
1088         struct clk clk;
1089         unsigned long clock;
1090         int ret;
1091
1092         host = priv->host;
1093
1094 #if defined(CONFIG_ARCH_ZYNQMP) && defined(CONFIG_ZYNQMP_FIRMWARE)
1095         if (device_is_compatible(dev, "xlnx,zynqmp-8.9a")) {
1096                 ret = zynqmp_pm_is_function_supported(PM_IOCTL,
1097                                                       IOCTL_SET_SD_CONFIG);
1098                 if (!ret) {
1099                         ret = sdhci_zynqmp_set_dynamic_config(priv, dev);
1100                         if (ret)
1101                                 return ret;
1102                 }
1103         }
1104 #endif
1105         if (device_is_compatible(dev, "xlnx,versal-net-5.1-emmc"))
1106                 priv->internal_phy_reg = true;
1107
1108         ret = clk_get_by_index(dev, 0, &clk);
1109         if (ret < 0) {
1110                 dev_err(dev, "failed to get clock\n");
1111                 return ret;
1112         }
1113
1114         clock = clk_get_rate(&clk);
1115         if (IS_ERR_VALUE(clock)) {
1116                 dev_err(dev, "failed to get rate\n");
1117                 return clock;
1118         }
1119
1120         dev_dbg(dev, "%s: CLK %ld\n", __func__, clock);
1121
1122         ret = clk_enable(&clk);
1123         if (ret) {
1124                 dev_err(dev, "failed to enable clock\n");
1125                 return ret;
1126         }
1127
1128         host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
1129                        SDHCI_QUIRK_BROKEN_R1B;
1130
1131 #ifdef CONFIG_ZYNQ_HISPD_BROKEN
1132         host->quirks |= SDHCI_QUIRK_BROKEN_HISPD_MODE;
1133 #endif
1134
1135         if (priv->no_1p8)
1136                 host->quirks |= SDHCI_QUIRK_NO_1_8_V;
1137
1138         if (CONFIG_IS_ENABLED(ARCH_VERSAL_NET) &&
1139             device_is_compatible(dev, "xlnx,versal-net-5.1-emmc"))
1140                 host->quirks |= SDHCI_QUIRK_CAPS_BIT63_FOR_HS400;
1141
1142         plat->cfg.f_max = CONFIG_ZYNQ_SDHCI_MAX_FREQ;
1143
1144         ret = mmc_of_parse(dev, &plat->cfg);
1145         if (ret)
1146                 return ret;
1147
1148         host->max_clk = clock;
1149
1150         host->mmc = &plat->mmc;
1151         host->mmc->dev = dev;
1152         host->mmc->priv = host;
1153
1154         ret = sdhci_setup_cfg(&plat->cfg, host, plat->cfg.f_max,
1155                               CONFIG_ZYNQ_SDHCI_MIN_FREQ);
1156         if (ret)
1157                 return ret;
1158         upriv->mmc = host->mmc;
1159
1160         /*
1161          * WORKAROUND: Versal platforms have an issue with card detect state.
1162          * Due to this, host controller is switching off voltage to sd card
1163          * causing sd card timeout error. Workaround this by adding a wait for
1164          * 1000msec till the card detect state gets stable.
1165          */
1166         if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) || IS_ENABLED(CONFIG_ARCH_VERSAL)) {
1167                 u32 timeout = 1000000;
1168
1169                 while (((sdhci_readl(host, SDHCI_PRESENT_STATE) &
1170                          SDHCI_CARD_STATE_STABLE) == 0) && timeout) {
1171                         udelay(1);
1172                         timeout--;
1173                 }
1174                 if (!timeout) {
1175                         dev_err(dev, "Sdhci card detect state not stable\n");
1176                         return -ETIMEDOUT;
1177                 }
1178         }
1179
1180         return sdhci_probe(dev);
1181 }
1182
1183 static int arasan_sdhci_of_to_plat(struct udevice *dev)
1184 {
1185         struct arasan_sdhci_priv *priv = dev_get_priv(dev);
1186         u32 pm_info[2];
1187
1188         priv->host = calloc(1, sizeof(struct sdhci_host));
1189         if (!priv->host)
1190                 return -1;
1191
1192         priv->host->name = dev->name;
1193
1194 #if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL) || defined(CONFIG_ARCH_VERSAL_NET)
1195         priv->host->ops = &arasan_ops;
1196         arasan_dt_parse_clk_phases(dev);
1197 #endif
1198
1199         priv->host->ioaddr = (void *)dev_read_addr(dev);
1200         if (IS_ERR(priv->host->ioaddr))
1201                 return PTR_ERR(priv->host->ioaddr);
1202
1203         priv->bank = dev_read_u32_default(dev, "xlnx,mio-bank", 0);
1204         priv->no_1p8 = dev_read_bool(dev, "no-1-8-v");
1205
1206         priv->node_id = 0;
1207         if (!dev_read_u32_array(dev, "power-domains", pm_info, ARRAY_SIZE(pm_info)))
1208                 priv->node_id = pm_info[1];
1209
1210         return 0;
1211 }
1212
1213 static int arasan_sdhci_bind(struct udevice *dev)
1214 {
1215         struct arasan_sdhci_plat *plat = dev_get_plat(dev);
1216
1217         return sdhci_bind(dev, &plat->mmc, &plat->cfg);
1218 }
1219
1220 static const struct udevice_id arasan_sdhci_ids[] = {
1221         { .compatible = "arasan,sdhci-8.9a" },
1222         { .compatible = "xlnx,versal-net-5.1-emmc" },
1223         { }
1224 };
1225
1226 U_BOOT_DRIVER(arasan_sdhci_drv) = {
1227         .name           = "arasan_sdhci",
1228         .id             = UCLASS_MMC,
1229         .of_match       = arasan_sdhci_ids,
1230         .of_to_plat = arasan_sdhci_of_to_plat,
1231         .ops            = &sdhci_ops,
1232         .bind           = arasan_sdhci_bind,
1233         .probe          = arasan_sdhci_probe,
1234         .priv_auto      = sizeof(struct arasan_sdhci_priv),
1235         .plat_auto      = sizeof(struct arasan_sdhci_plat),
1236 };