drivers/mmc/zynq_sdhci.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2013 - 2015 Xilinx, Inc.
   4  *
   5  * Xilinx Zynq SD Host Controller Interface
   6  */
   7
   8 #include <clk.h>
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <fdtdec.h>
  12 #include <linux/delay.h>
  13 #include "mmc_private.h"
  14 #include <log.h>
  15 #include <reset.h>
  16 #include <dm/device_compat.h>
  17 #include <linux/err.h>
  18 #include <linux/libfdt.h>
  19 #include <asm/types.h>
  20 #include <linux/math64.h>
  21 #include <asm/cache.h>
  22 #include <malloc.h>
  23 #include <sdhci.h>
  24 #include <zynqmp_firmware.h>
  25
  26 #define SDHCI_ARASAN_ITAPDLY_REGISTER   0xF0F8
  27 #define SDHCI_ARASAN_ITAPDLY_SEL_MASK   GENMASK(7, 0)
  28 #define SDHCI_ARASAN_OTAPDLY_REGISTER   0xF0FC
  29 #define SDHCI_ARASAN_OTAPDLY_SEL_MASK   GENMASK(5, 0)
  30 #define SDHCI_ITAPDLY_CHGWIN            BIT(9)
  31 #define SDHCI_ITAPDLY_ENABLE            BIT(8)
  32 #define SDHCI_OTAPDLY_ENABLE            BIT(6)
  33
  34 #define SDHCI_TUNING_LOOP_COUNT         40
  35 #define MMC_BANK2                       0x2
  36
  37 #define SD_DLL_CTRL                     0xFF180358
  38 #define SD_ITAP_DLY                     0xFF180314
  39 #define SD_OTAP_DLY                     0xFF180318
  40 #define SD0_DLL_RST                     BIT(2)
  41 #define SD1_DLL_RST                     BIT(18)
  42 #define SD0_ITAPCHGWIN                  BIT(9)
  43 #define SD1_ITAPCHGWIN                  BIT(25)
  44 #define SD0_ITAPDLYENA                  BIT(8)
  45 #define SD1_ITAPDLYENA                  BIT(24)
  46 #define SD0_ITAPDLYSEL_MASK             GENMASK(7, 0)
  47 #define SD1_ITAPDLYSEL_MASK             GENMASK(23, 16)
  48 #define SD0_OTAPDLYSEL_MASK             GENMASK(5, 0)
  49 #define SD1_OTAPDLYSEL_MASK             GENMASK(21, 16)
  50
  51 struct arasan_sdhci_clk_data {
  52         int clk_phase_in[MMC_TIMING_MMC_HS400 + 1];
  53         int clk_phase_out[MMC_TIMING_MMC_HS400 + 1];
  54 };
  55
  56 struct arasan_sdhci_plat {
  57         struct mmc_config cfg;
  58         struct mmc mmc;
  59 };
  60
  61 struct arasan_sdhci_priv {
  62         struct sdhci_host *host;
  63         struct arasan_sdhci_clk_data clk_data;
  64         u32 node_id;
  65         u8 bank;
  66         u8 no_1p8;
  67         struct reset_ctl_bulk resets;
  68 };
  69
  70 /* For Versal platforms zynqmp_mmio_write() won't be available */
  71 __weak int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value)
  72 {
  73         return 0;
  74 }
  75
  76 __weak int xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
  77                              u32 arg3, u32 *ret_payload)
  78 {
  79         return 0;
  80 }
  81
  82 __weak int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id)
  83 {
  84         return 1;
  85 }
  86
  87 #if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL)
  88 /* Default settings for ZynqMP Clock Phases */
  89 static const u32 zynqmp_iclk_phases[] = {0, 63, 63, 0, 63,  0,
  90                                          0, 183, 54,  0, 0};
  91 static const u32 zynqmp_oclk_phases[] = {0, 72, 60, 0, 60, 72,
  92                                          135, 48, 72, 135, 0};
  93
  94 /* Default settings for Versal Clock Phases */
  95 static const u32 versal_iclk_phases[] = {0, 132, 132, 0, 132,
  96                                          0, 0, 162, 90, 0, 0};
  97 static const u32 versal_oclk_phases[] = {0,  60, 48, 0, 48, 72,
  98                                          90, 36, 60, 90, 0};
  99
 100 static const u8 mode2timing[] = {
 101         [MMC_LEGACY] = MMC_TIMING_LEGACY,
 102         [MMC_HS] = MMC_TIMING_MMC_HS,
 103         [SD_HS] = MMC_TIMING_SD_HS,
 104         [MMC_HS_52] = MMC_TIMING_MMC_HS,
 105         [MMC_DDR_52] = MMC_TIMING_MMC_DDR52,
 106         [UHS_SDR12] = MMC_TIMING_UHS_SDR12,
 107         [UHS_SDR25] = MMC_TIMING_UHS_SDR25,
 108         [UHS_SDR50] = MMC_TIMING_UHS_SDR50,
 109         [UHS_DDR50] = MMC_TIMING_UHS_DDR50,
 110         [UHS_SDR104] = MMC_TIMING_UHS_SDR104,
 111         [MMC_HS_200] = MMC_TIMING_MMC_HS200,
 112 };
 113
 114 static inline int arasan_zynqmp_set_in_tapdelay(u32 node_id, u32 itap_delay)
 115 {
 116         int ret;
 117
 118         if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
 119                 if (node_id == NODE_SD_0) {
 120                         ret = zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN,
 121                                                 SD0_ITAPCHGWIN);
 122                         if (ret)
 123                                 return ret;
 124
 125                         ret = zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYENA,
 126                                                 SD0_ITAPDLYENA);
 127                         if (ret)
 128                                 return ret;
 129
 130                         ret = zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPDLYSEL_MASK,
 131                                                 itap_delay);
 132                         if (ret)
 133                                 return ret;
 134
 135                         ret = zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN, 0);
 136                         if (ret)
 137                                 return ret;
 138                 }
 139                 ret = zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN,
 140                                         SD1_ITAPCHGWIN);
 141                 if (ret)
 142                         return ret;
 143
 144                 ret = zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYENA,
 145                                         SD1_ITAPDLYENA);
 146                 if (ret)
 147                         return ret;
 148
 149                 ret = zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPDLYSEL_MASK,
 150                                         (itap_delay << 16));
 151                 if (ret)
 152                         return ret;
 153
 154                 ret = zynqmp_mmio_write(SD_ITAP_DLY, SD1_ITAPCHGWIN, 0);
 155                 if (ret)
 156                         return ret;
 157         } else {
 158                 return xilinx_pm_request(PM_IOCTL, node_id,
 159                                          IOCTL_SET_SD_TAPDELAY,
 160                                          PM_TAPDELAY_INPUT, itap_delay, NULL);
 161         }
 162
 163         return 0;
 164 }
 165
 166 static inline int arasan_zynqmp_set_out_tapdelay(u32 node_id, u32 otap_delay)
 167 {
 168         if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
 169                 if (node_id == NODE_SD_0)
 170                         return zynqmp_mmio_write(SD_OTAP_DLY,
 171                                                  SD0_OTAPDLYSEL_MASK,
 172                                                  otap_delay);
 173
 174                 return zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
 175                                          (otap_delay << 16));
 176         } else {
 177                 return xilinx_pm_request(PM_IOCTL, node_id,
 178                                          IOCTL_SET_SD_TAPDELAY,
 179                                          PM_TAPDELAY_OUTPUT, otap_delay, NULL);
 180         }
 181 }
 182
 183 static inline int zynqmp_dll_reset(u32 node_id, u32 type)
 184 {
 185         if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
 186                 if (node_id == NODE_SD_0)
 187                         return zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST,
 188                                                  type == PM_DLL_RESET_ASSERT ?
 189                                                  SD0_DLL_RST : 0);
 190
 191                 return zynqmp_mmio_write(SD_DLL_CTRL, SD1_DLL_RST,
 192                                          type == PM_DLL_RESET_ASSERT ?
 193                                          SD1_DLL_RST : 0);
 194         } else {
 195                 return xilinx_pm_request(PM_IOCTL, node_id,
 196                                          IOCTL_SD_DLL_RESET, type, 0, NULL);
 197         }
 198 }
 199
 200 static int arasan_zynqmp_dll_reset(struct sdhci_host *host, u32 node_id)
 201 {
 202         struct mmc *mmc = (struct mmc *)host->mmc;
 203         struct udevice *dev = mmc->dev;
 204         unsigned long timeout;
 205         int ret;
 206         u16 clk;
 207
 208         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
 209         clk &= ~(SDHCI_CLOCK_CARD_EN);
 210         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 211
 212         /* Issue DLL Reset */
 213         ret = zynqmp_dll_reset(node_id, PM_DLL_RESET_ASSERT);
 214         if (ret) {
 215                 dev_err(dev, "dll_reset assert failed with err: %d\n", ret);
 216                 return ret;
 217         }
 218
 219         /* Allow atleast 1ms delay for proper DLL reset */
 220         mdelay(1);
 221         ret = zynqmp_dll_reset(node_id, PM_DLL_RESET_RELEASE);
 222         if (ret) {
 223                 dev_err(dev, "dll_reset release failed with err: %d\n", ret);
 224                 return ret;
 225         }
 226
 227         /* Wait max 20 ms */
 228         timeout = 100;
 229         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
 230                                 & SDHCI_CLOCK_INT_STABLE)) {
 231                 if (timeout == 0) {
 232                         dev_err(dev, ": Internal clock never stabilised.\n");
 233                         return -EBUSY;
 234                 }
 235                 timeout--;
 236                 udelay(1000);
 237         }
 238
 239         clk |= SDHCI_CLOCK_CARD_EN;
 240         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 241
 242         return 0;
 243 }
 244
 245 static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
 246 {
 247         struct mmc_cmd cmd;
 248         struct mmc_data data;
 249         u32 ctrl;
 250         struct sdhci_host *host;
 251         struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
 252         char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
 253
 254         dev_dbg(mmc->dev, "%s\n", __func__);
 255
 256         host = priv->host;
 257
 258         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 259         ctrl |= SDHCI_CTRL_EXEC_TUNING;
 260         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
 261
 262         mdelay(1);
 263
 264         arasan_zynqmp_dll_reset(host, priv->node_id);
 265
 266         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
 267         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
 268
 269         do {
 270                 cmd.cmdidx = opcode;
 271                 cmd.resp_type = MMC_RSP_R1;
 272                 cmd.cmdarg = 0;
 273
 274                 data.blocksize = 64;
 275                 data.blocks = 1;
 276                 data.flags = MMC_DATA_READ;
 277
 278                 if (tuning_loop_counter-- == 0)
 279                         break;
 280
 281                 if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200 &&
 282                     mmc->bus_width == 8)
 283                         data.blocksize = 128;
 284
 285                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 286                                                     data.blocksize),
 287                              SDHCI_BLOCK_SIZE);
 288                 sdhci_writew(host, data.blocks, SDHCI_BLOCK_COUNT);
 289                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
 290
 291                 mmc_send_cmd(mmc, &cmd, NULL);
 292                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 293
 294                 if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
 295                         udelay(1);
 296
 297         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
 298
 299         if (tuning_loop_counter < 0) {
 300                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
 301                 sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL2);
 302         }
 303
 304         if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
 305                 printf("%s:Tuning failed\n", __func__);
 306                 return -1;
 307         }
 308
 309         udelay(1);
 310         arasan_zynqmp_dll_reset(host, priv->node_id);
 311
 312         /* Enable only interrupts served by the SD controller */
 313         sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
 314                      SDHCI_INT_ENABLE);
 315         /* Mask all sdhci interrupt sources */
 316         sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
 317
 318         return 0;
 319 }
 320
 321 /**
 322  * sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
 323  *
 324  * @host:               Pointer to the sdhci_host structure.
 325  * @degrees:            The clock phase shift between 0 - 359.
 326  * Return: 0
 327  *
 328  * Set the SD Output Clock Tap Delays for Output path
 329  */
 330 static int sdhci_zynqmp_sdcardclk_set_phase(struct sdhci_host *host,
 331                                             int degrees)
 332 {
 333         struct mmc *mmc = (struct mmc *)host->mmc;
 334         struct udevice *dev = mmc->dev;
 335         struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
 336         u8 tap_delay, tap_max = 0;
 337         int timing = mode2timing[mmc->selected_mode];
 338         int ret;
 339
 340         /*
 341          * This is applicable for SDHCI_SPEC_300 and above
 342          * ZynqMP does not set phase for <=25MHz clock.
 343          * If degrees is zero, no need to do anything.
 344          */
 345         if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
 346                 return 0;
 347
 348         switch (timing) {
 349         case MMC_TIMING_MMC_HS:
 350         case MMC_TIMING_SD_HS:
 351         case MMC_TIMING_UHS_SDR25:
 352         case MMC_TIMING_UHS_DDR50:
 353         case MMC_TIMING_MMC_DDR52:
 354                 /* For 50MHz clock, 30 Taps are available */
 355                 tap_max = 30;
 356                 break;
 357         case MMC_TIMING_UHS_SDR50:
 358                 /* For 100MHz clock, 15 Taps are available */
 359                 tap_max = 15;
 360                 break;
 361         case MMC_TIMING_UHS_SDR104:
 362         case MMC_TIMING_MMC_HS200:
 363                 /* For 200MHz clock, 8 Taps are available */
 364                 tap_max = 8;
 365         default:
 366                 break;
 367         }
 368
 369         tap_delay = (degrees * tap_max) / 360;
 370
 371         /* Limit output tap_delay value to 6 bits */
 372         tap_delay &= SDHCI_ARASAN_OTAPDLY_SEL_MASK;
 373
 374         /* Set the Clock Phase */
 375         ret = arasan_zynqmp_set_out_tapdelay(priv->node_id, tap_delay);
 376         if (ret) {
 377                 dev_err(dev, "Error setting output Tap Delay\n");
 378                 return ret;
 379         }
 380
 381         /* Release DLL Reset */
 382         ret = zynqmp_dll_reset(priv->node_id, PM_DLL_RESET_RELEASE);
 383         if (ret) {
 384                 dev_err(dev, "dll_reset release failed with err: %d\n", ret);
 385                 return ret;
 386         }
 387
 388         return 0;
 389 }
 390
 391 /**
 392  * sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays
 393  *
 394  * @host:               Pointer to the sdhci_host structure.
 395  * @degrees:            The clock phase shift between 0 - 359.
 396  * Return: 0
 397  *
 398  * Set the SD Input Clock Tap Delays for Input path
 399  */
 400 static int sdhci_zynqmp_sampleclk_set_phase(struct sdhci_host *host,
 401                                             int degrees)
 402 {
 403         struct mmc *mmc = (struct mmc *)host->mmc;
 404         struct udevice *dev = mmc->dev;
 405         struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
 406         u8 tap_delay, tap_max = 0;
 407         int timing = mode2timing[mmc->selected_mode];
 408         int ret;
 409
 410         /*
 411          * This is applicable for SDHCI_SPEC_300 and above
 412          * ZynqMP does not set phase for <=25MHz clock.
 413          * If degrees is zero, no need to do anything.
 414          */
 415         if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
 416                 return 0;
 417
 418         /* Assert DLL Reset */
 419         ret = zynqmp_dll_reset(priv->node_id, PM_DLL_RESET_ASSERT);
 420         if (ret) {
 421                 dev_err(dev, "dll_reset assert failed with err: %d\n", ret);
 422                 return ret;
 423         }
 424
 425         switch (timing) {
 426         case MMC_TIMING_MMC_HS:
 427         case MMC_TIMING_SD_HS:
 428         case MMC_TIMING_UHS_SDR25:
 429         case MMC_TIMING_UHS_DDR50:
 430         case MMC_TIMING_MMC_DDR52:
 431                 /* For 50MHz clock, 120 Taps are available */
 432                 tap_max = 120;
 433                 break;
 434         case MMC_TIMING_UHS_SDR50:
 435                 /* For 100MHz clock, 60 Taps are available */
 436                 tap_max = 60;
 437                 break;
 438         case MMC_TIMING_UHS_SDR104:
 439         case MMC_TIMING_MMC_HS200:
 440                 /* For 200MHz clock, 30 Taps are available */
 441                 tap_max = 30;
 442         default:
 443                 break;
 444         }
 445
 446         tap_delay = (degrees * tap_max) / 360;
 447
 448         /* Limit input tap_delay value to 8 bits */
 449         tap_delay &= SDHCI_ARASAN_ITAPDLY_SEL_MASK;
 450
 451         ret = arasan_zynqmp_set_in_tapdelay(priv->node_id, tap_delay);
 452         if (ret) {
 453                 dev_err(dev, "Error setting Input Tap Delay\n");
 454                 return ret;
 455         }
 456
 457         return 0;
 458 }
 459
 460 /**
 461  * sdhci_versal_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
 462  *
 463  * @host:               Pointer to the sdhci_host structure.
 464  * @degrees:            The clock phase shift between 0 - 359.
 465  * Return: 0
 466  *
 467  * Set the SD Output Clock Tap Delays for Output path
 468  */
 469 static int sdhci_versal_sdcardclk_set_phase(struct sdhci_host *host,
 470                                             int degrees)
 471 {
 472         struct mmc *mmc = (struct mmc *)host->mmc;
 473         u8 tap_delay, tap_max = 0;
 474         int timing = mode2timing[mmc->selected_mode];
 475         u32 regval;
 476
 477         /*
 478          * This is applicable for SDHCI_SPEC_300 and above
 479          * Versal does not set phase for <=25MHz clock.
 480          * If degrees is zero, no need to do anything.
 481          */
 482         if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
 483                 return 0;
 484
 485         switch (timing) {
 486         case MMC_TIMING_MMC_HS:
 487         case MMC_TIMING_SD_HS:
 488         case MMC_TIMING_UHS_SDR25:
 489         case MMC_TIMING_UHS_DDR50:
 490         case MMC_TIMING_MMC_DDR52:
 491                 /* For 50MHz clock, 30 Taps are available */
 492                 tap_max = 30;
 493                 break;
 494         case MMC_TIMING_UHS_SDR50:
 495                 /* For 100MHz clock, 15 Taps are available */
 496                 tap_max = 15;
 497                 break;
 498         case MMC_TIMING_UHS_SDR104:
 499         case MMC_TIMING_MMC_HS200:
 500                 /* For 200MHz clock, 8 Taps are available */
 501                 tap_max = 8;
 502         default:
 503                 break;
 504         }
 505
 506         tap_delay = (degrees * tap_max) / 360;
 507
 508         /* Limit output tap_delay value to 6 bits */
 509         tap_delay &= SDHCI_ARASAN_OTAPDLY_SEL_MASK;
 510
 511         /* Set the Clock Phase */
 512         regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER);
 513         regval |= SDHCI_OTAPDLY_ENABLE;
 514         sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
 515         regval &= ~SDHCI_ARASAN_OTAPDLY_SEL_MASK;
 516         regval |= tap_delay;
 517         sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
 518
 519         return 0;
 520 }
 521
 522 /**
 523  * sdhci_versal_sampleclk_set_phase - Set the SD Input Clock Tap Delays
 524  *
 525  * @host:               Pointer to the sdhci_host structure.
 526  * @degrees:            The clock phase shift between 0 - 359.
 527  * Return: 0
 528  *
 529  * Set the SD Input Clock Tap Delays for Input path
 530  */
 531 static int sdhci_versal_sampleclk_set_phase(struct sdhci_host *host,
 532                                             int degrees)
 533 {
 534         struct mmc *mmc = (struct mmc *)host->mmc;
 535         u8 tap_delay, tap_max = 0;
 536         int timing = mode2timing[mmc->selected_mode];
 537         u32 regval;
 538
 539         /*
 540          * This is applicable for SDHCI_SPEC_300 and above
 541          * Versal does not set phase for <=25MHz clock.
 542          * If degrees is zero, no need to do anything.
 543          */
 544         if (SDHCI_GET_VERSION(host) < SDHCI_SPEC_300)
 545                 return 0;
 546
 547         switch (timing) {
 548         case MMC_TIMING_MMC_HS:
 549         case MMC_TIMING_SD_HS:
 550         case MMC_TIMING_UHS_SDR25:
 551         case MMC_TIMING_UHS_DDR50:
 552         case MMC_TIMING_MMC_DDR52:
 553                 /* For 50MHz clock, 120 Taps are available */
 554                 tap_max = 120;
 555                 break;
 556         case MMC_TIMING_UHS_SDR50:
 557                 /* For 100MHz clock, 60 Taps are available */
 558                 tap_max = 60;
 559                 break;
 560         case MMC_TIMING_UHS_SDR104:
 561         case MMC_TIMING_MMC_HS200:
 562                 /* For 200MHz clock, 30 Taps are available */
 563                 tap_max = 30;
 564         default:
 565                 break;
 566         }
 567
 568         tap_delay = (degrees * tap_max) / 360;
 569
 570         /* Limit input tap_delay value to 8 bits */
 571         tap_delay &= SDHCI_ARASAN_ITAPDLY_SEL_MASK;
 572
 573         /* Set the Clock Phase */
 574         regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER);
 575         regval |= SDHCI_ITAPDLY_CHGWIN;
 576         sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
 577         regval |= SDHCI_ITAPDLY_ENABLE;
 578         sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
 579         regval &= ~SDHCI_ARASAN_ITAPDLY_SEL_MASK;
 580         regval |= tap_delay;
 581         sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
 582         regval &= ~SDHCI_ITAPDLY_CHGWIN;
 583         sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
 584
 585         return 0;
 586 }
 587
 588 static int arasan_sdhci_set_tapdelay(struct sdhci_host *host)
 589 {
 590         struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
 591         struct arasan_sdhci_clk_data *clk_data = &priv->clk_data;
 592         struct mmc *mmc = (struct mmc *)host->mmc;
 593         struct udevice *dev = mmc->dev;
 594         u8 timing = mode2timing[mmc->selected_mode];
 595         u32 iclk_phase = clk_data->clk_phase_in[timing];
 596         u32 oclk_phase = clk_data->clk_phase_out[timing];
 597         int ret;
 598
 599         dev_dbg(dev, "%s, host:%s, mode:%d\n", __func__, host->name, timing);
 600
 601         if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) &&
 602             device_is_compatible(dev, "xlnx,zynqmp-8.9a")) {
 603                 ret = sdhci_zynqmp_sampleclk_set_phase(host, iclk_phase);
 604                 if (ret)
 605                         return ret;
 606
 607                 ret = sdhci_zynqmp_sdcardclk_set_phase(host, oclk_phase);
 608                 if (ret)
 609                         return ret;
 610         } else if (IS_ENABLED(CONFIG_ARCH_VERSAL) &&
 611                    device_is_compatible(dev, "xlnx,versal-8.9a")) {
 612                 ret = sdhci_versal_sampleclk_set_phase(host, iclk_phase);
 613                 if (ret)
 614                         return ret;
 615
 616                 ret = sdhci_versal_sdcardclk_set_phase(host, oclk_phase);
 617                 if (ret)
 618                         return ret;
 619         }
 620
 621         return 0;
 622 }
 623
 624 static void arasan_dt_read_clk_phase(struct udevice *dev, unsigned char timing,
 625                                      const char *prop)
 626 {
 627         struct arasan_sdhci_priv *priv = dev_get_priv(dev);
 628         struct arasan_sdhci_clk_data *clk_data = &priv->clk_data;
 629         u32 clk_phase[2] = {0};
 630
 631         /*
 632          * Read Tap Delay values from DT, if the DT does not contain the
 633          * Tap Values then use the pre-defined values
 634          */
 635         if (dev_read_u32_array(dev, prop, &clk_phase[0], 2)) {
 636                 dev_dbg(dev, "Using predefined clock phase for %s = %d %d\n",
 637                         prop, clk_data->clk_phase_in[timing],
 638                         clk_data->clk_phase_out[timing]);
 639                 return;
 640         }
 641
 642         /* The values read are Input and Output Clock Delays in order */
 643         clk_data->clk_phase_in[timing] = clk_phase[0];
 644         clk_data->clk_phase_out[timing] = clk_phase[1];
 645 }
 646
 647 /**
 648  * arasan_dt_parse_clk_phases - Read Tap Delay values from DT
 649  *
 650  * @dev:                Pointer to our struct udevice.
 651  *
 652  * Called at initialization to parse the values of Tap Delays.
 653  */
 654 static void arasan_dt_parse_clk_phases(struct udevice *dev)
 655 {
 656         struct arasan_sdhci_priv *priv = dev_get_priv(dev);
 657         struct arasan_sdhci_clk_data *clk_data = &priv->clk_data;
 658         int i;
 659
 660         if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) &&
 661             device_is_compatible(dev, "xlnx,zynqmp-8.9a")) {
 662                 for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
 663                         clk_data->clk_phase_in[i] = zynqmp_iclk_phases[i];
 664                         clk_data->clk_phase_out[i] = zynqmp_oclk_phases[i];
 665                 }
 666
 667                 if (priv->bank == MMC_BANK2) {
 668                         clk_data->clk_phase_out[MMC_TIMING_UHS_SDR104] = 90;
 669                         clk_data->clk_phase_out[MMC_TIMING_MMC_HS200] = 90;
 670                 }
 671         }
 672
 673         if (IS_ENABLED(CONFIG_ARCH_VERSAL) &&
 674             device_is_compatible(dev, "xlnx,versal-8.9a")) {
 675                 for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
 676                         clk_data->clk_phase_in[i] = versal_iclk_phases[i];
 677                         clk_data->clk_phase_out[i] = versal_oclk_phases[i];
 678                 }
 679         }
 680
 681         arasan_dt_read_clk_phase(dev, MMC_TIMING_LEGACY,
 682                                  "clk-phase-legacy");
 683         arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_HS,
 684                                  "clk-phase-mmc-hs");
 685         arasan_dt_read_clk_phase(dev, MMC_TIMING_SD_HS,
 686                                  "clk-phase-sd-hs");
 687         arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR12,
 688                                  "clk-phase-uhs-sdr12");
 689         arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR25,
 690                                  "clk-phase-uhs-sdr25");
 691         arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR50,
 692                                  "clk-phase-uhs-sdr50");
 693         arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_SDR104,
 694                                  "clk-phase-uhs-sdr104");
 695         arasan_dt_read_clk_phase(dev, MMC_TIMING_UHS_DDR50,
 696                                  "clk-phase-uhs-ddr50");
 697         arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_DDR52,
 698                                  "clk-phase-mmc-ddr52");
 699         arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_HS200,
 700                                  "clk-phase-mmc-hs200");
 701         arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_HS400,
 702                                  "clk-phase-mmc-hs400");
 703 }
 704
 705 static const struct sdhci_ops arasan_ops = {
 706         .platform_execute_tuning        = &arasan_sdhci_execute_tuning,
 707         .set_delay = &arasan_sdhci_set_tapdelay,
 708         .set_control_reg = &sdhci_set_control_reg,
 709 };
 710 #endif
 711
 712 #if defined(CONFIG_ARCH_ZYNQMP)
 713 static int sdhci_zynqmp_set_dynamic_config(struct arasan_sdhci_priv *priv,
 714                                            struct udevice *dev)
 715 {
 716         int ret;
 717         struct clk clk;
 718         unsigned long clock, mhz;
 719
 720         ret = xilinx_pm_request(PM_REQUEST_NODE, priv->node_id,
 721                                 ZYNQMP_PM_CAPABILITY_ACCESS, ZYNQMP_PM_MAX_QOS,
 722                                 ZYNQMP_PM_REQUEST_ACK_NO, NULL);
 723         if (ret) {
 724                 dev_err(dev, "Request node failed for %d\n", priv->node_id);
 725                 return ret;
 726         }
 727
 728         ret = reset_get_bulk(dev, &priv->resets);
 729         if (ret == -ENOTSUPP || ret == -ENOENT) {
 730                 dev_err(dev, "Reset not found\n");
 731                 return 0;
 732         } else if (ret) {
 733                 dev_err(dev, "Reset failed\n");
 734                 return ret;
 735         }
 736
 737         ret = reset_assert_bulk(&priv->resets);
 738         if (ret) {
 739                 dev_err(dev, "Reset assert failed\n");
 740                 return ret;
 741         }
 742
 743         ret = zynqmp_pm_set_sd_config(priv->node_id, SD_CONFIG_FIXED, 0);
 744         if (ret) {
 745                 dev_err(dev, "SD_CONFIG_FIXED failed\n");
 746                 return ret;
 747         }
 748
 749         ret = zynqmp_pm_set_sd_config(priv->node_id, SD_CONFIG_EMMC_SEL,
 750                                       dev_read_bool(dev, "non-removable"));
 751         if (ret) {
 752                 dev_err(dev, "SD_CONFIG_EMMC_SEL failed\n");
 753                 return ret;
 754         }
 755
 756         ret = clk_get_by_index(dev, 0, &clk);
 757         if (ret < 0) {
 758                 dev_err(dev, "failed to get clock\n");
 759                 return ret;
 760         }
 761
 762         clock = clk_get_rate(&clk);
 763         if (IS_ERR_VALUE(clock)) {
 764                 dev_err(dev, "failed to get rate\n");
 765                 return clock;
 766         }
 767
 768         mhz = DIV64_U64_ROUND_UP(clock, 1000000);
 769
 770         if (mhz > 100 && mhz <= 200)
 771                 mhz = 200;
 772         else if (mhz > 50 && mhz <= 100)
 773                 mhz = 100;
 774         else if (mhz > 25 && mhz <= 50)
 775                 mhz = 50;
 776         else
 777                 mhz = 25;
 778
 779         ret = zynqmp_pm_set_sd_config(priv->node_id, SD_CONFIG_BASECLK, mhz);
 780         if (ret) {
 781                 dev_err(dev, "SD_CONFIG_BASECLK failed\n");
 782                 return ret;
 783         }
 784
 785         ret = zynqmp_pm_set_sd_config(priv->node_id, SD_CONFIG_8BIT,
 786                                       (dev_read_u32_default(dev, "bus-width", 1) == 8));
 787         if (ret) {
 788                 dev_err(dev, "SD_CONFIG_8BIT failed\n");
 789                 return ret;
 790         }
 791
 792         ret = reset_deassert_bulk(&priv->resets);
 793         if (ret) {
 794                 dev_err(dev, "Reset release failed\n");
 795                 return ret;
 796         }
 797
 798         return 0;
 799 }
 800 #endif
 801
 802 static int arasan_sdhci_probe(struct udevice *dev)
 803 {
 804         struct arasan_sdhci_plat *plat = dev_get_plat(dev);
 805         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 806         struct arasan_sdhci_priv *priv = dev_get_priv(dev);
 807         struct sdhci_host *host;
 808         struct clk clk;
 809         unsigned long clock;
 810         int ret;
 811
 812         host = priv->host;
 813
 814 #if defined(CONFIG_ARCH_ZYNQMP)
 815         if (device_is_compatible(dev, "xlnx,zynqmp-8.9a")) {
 816                 ret = zynqmp_pm_is_function_supported(PM_IOCTL,
 817                                                       IOCTL_SET_SD_CONFIG);
 818                 if (!ret) {
 819                         ret = sdhci_zynqmp_set_dynamic_config(priv, dev);
 820                         if (ret)
 821                                 return ret;
 822                 }
 823         }
 824 #endif
 825
 826         ret = clk_get_by_index(dev, 0, &clk);
 827         if (ret < 0) {
 828                 dev_err(dev, "failed to get clock\n");
 829                 return ret;
 830         }
 831
 832         clock = clk_get_rate(&clk);
 833         if (IS_ERR_VALUE(clock)) {
 834                 dev_err(dev, "failed to get rate\n");
 835                 return clock;
 836         }
 837
 838         dev_dbg(dev, "%s: CLK %ld\n", __func__, clock);
 839
 840         ret = clk_enable(&clk);
 841         if (ret) {
 842                 dev_err(dev, "failed to enable clock\n");
 843                 return ret;
 844         }
 845
 846         host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
 847                        SDHCI_QUIRK_BROKEN_R1B;
 848
 849 #ifdef CONFIG_ZYNQ_HISPD_BROKEN
 850         host->quirks |= SDHCI_QUIRK_BROKEN_HISPD_MODE;
 851 #endif
 852
 853         if (priv->no_1p8)
 854                 host->quirks |= SDHCI_QUIRK_NO_1_8_V;
 855
 856         plat->cfg.f_max = CONFIG_ZYNQ_SDHCI_MAX_FREQ;
 857
 858         ret = mmc_of_parse(dev, &plat->cfg);
 859         if (ret)
 860                 return ret;
 861
 862         host->max_clk = clock;
 863
 864         host->mmc = &plat->mmc;
 865         host->mmc->dev = dev;
 866         host->mmc->priv = host;
 867
 868         ret = sdhci_setup_cfg(&plat->cfg, host, plat->cfg.f_max,
 869                               CONFIG_ZYNQ_SDHCI_MIN_FREQ);
 870         if (ret)
 871                 return ret;
 872         upriv->mmc = host->mmc;
 873
 874         /*
 875          * WORKAROUND: Versal platforms have an issue with card detect state.
 876          * Due to this, host controller is switching off voltage to sd card
 877          * causing sd card timeout error. Workaround this by adding a wait for
 878          * 1000msec till the card detect state gets stable.
 879          */
 880         if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) || IS_ENABLED(CONFIG_ARCH_VERSAL)) {
 881                 u32 timeout = 1000000;
 882
 883                 while (((sdhci_readl(host, SDHCI_PRESENT_STATE) &
 884                          SDHCI_CARD_STATE_STABLE) == 0) && timeout) {
 885                         udelay(1);
 886                         timeout--;
 887                 }
 888                 if (!timeout) {
 889                         dev_err(dev, "Sdhci card detect state not stable\n");
 890                         return -ETIMEDOUT;
 891                 }
 892         }
 893
 894         return sdhci_probe(dev);
 895 }
 896
 897 static int arasan_sdhci_of_to_plat(struct udevice *dev)
 898 {
 899         struct arasan_sdhci_priv *priv = dev_get_priv(dev);
 900         u32 pm_info[2];
 901
 902         priv->host = calloc(1, sizeof(struct sdhci_host));
 903         if (!priv->host)
 904                 return -1;
 905
 906         priv->host->name = dev->name;
 907
 908 #if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL)
 909         priv->host->ops = &arasan_ops;
 910         arasan_dt_parse_clk_phases(dev);
 911 #endif
 912
 913         priv->host->ioaddr = (void *)dev_read_addr(dev);
 914         if (IS_ERR(priv->host->ioaddr))
 915                 return PTR_ERR(priv->host->ioaddr);
 916
 917         priv->bank = dev_read_u32_default(dev, "xlnx,mio-bank", 0);
 918         priv->no_1p8 = dev_read_bool(dev, "no-1-8-v");
 919
 920         priv->node_id = 0;
 921         if (!dev_read_u32_array(dev, "power-domains", pm_info, ARRAY_SIZE(pm_info)))
 922                 priv->node_id = pm_info[1];
 923
 924         return 0;
 925 }
 926
 927 static int arasan_sdhci_bind(struct udevice *dev)
 928 {
 929         struct arasan_sdhci_plat *plat = dev_get_plat(dev);
 930
 931         return sdhci_bind(dev, &plat->mmc, &plat->cfg);
 932 }
 933
 934 static const struct udevice_id arasan_sdhci_ids[] = {
 935         { .compatible = "arasan,sdhci-8.9a" },
 936         { }
 937 };
 938
 939 U_BOOT_DRIVER(arasan_sdhci_drv) = {
 940         .name           = "arasan_sdhci",
 941         .id             = UCLASS_MMC,
 942         .of_match       = arasan_sdhci_ids,
 943         .of_to_plat = arasan_sdhci_of_to_plat,
 944         .ops            = &sdhci_ops,
 945         .bind           = arasan_sdhci_bind,
 946         .probe          = arasan_sdhci_probe,
 947         .priv_auto      = sizeof(struct arasan_sdhci_priv),
 948         .plat_auto      = sizeof(struct arasan_sdhci_plat),
 949 };