drivers/mmc/xenon_sdhci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver for Marvell SOC Platform Group Xenon SDHC as a platform device
   4  *
   5  * Copyright (C) 2016 Marvell, All Rights Reserved.
   6  *
   7  * Author:      Victor Gu <xigu@marvell.com>
   8  * Date:        2016-8-24
   9  *
  10  * Included parts of the Linux driver version which was written by:
  11  * Hu Ziji <huziji@marvell.com>
  12  *
  13  * Ported to from Marvell 2015.01 to mainline U-Boot 2017.01:
  14  * Stefan Roese <sr@denx.de>
  15  */
  16
  17 #include <common.h>
  18 #include <dm.h>
  19 #include <fdtdec.h>
  20 #include <linux/bitops.h>
  21 #include <linux/delay.h>
  22 #include <linux/libfdt.h>
  23 #include <malloc.h>
  24 #include <sdhci.h>
  25 #include <power/regulator.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 /* Register Offset of SD Host Controller SOCP self-defined register */
  30 #define SDHC_SYS_CFG_INFO                       0x0104
  31 #define SLOT_TYPE_SDIO_SHIFT                    24
  32 #define SLOT_TYPE_EMMC_MASK                     0xFF
  33 #define SLOT_TYPE_EMMC_SHIFT                    16
  34 #define SLOT_TYPE_SD_SDIO_MMC_MASK              0xFF
  35 #define SLOT_TYPE_SD_SDIO_MMC_SHIFT             8
  36 #define NR_SUPPORTED_SLOT_MASK                  0x7
  37
  38 #define SDHC_SYS_OP_CTRL                        0x0108
  39 #define AUTO_CLKGATE_DISABLE_MASK               BIT(20)
  40 #define SDCLK_IDLEOFF_ENABLE_SHIFT              8
  41 #define SLOT_ENABLE_SHIFT                       0
  42
  43 #define SDHC_SYS_EXT_OP_CTRL                    0x010C
  44 #define MASK_CMD_CONFLICT_ERROR                 BIT(8)
  45
  46 #define SDHC_SLOT_EMMC_CTRL                     0x0130
  47 #define ENABLE_DATA_STROBE_SHIFT                24
  48 #define SET_EMMC_RSTN_SHIFT                     16
  49 #define EMMC_VCCQ_MASK                          0x3
  50 #define EMMC_VCCQ_1_8V                          0x1
  51 #define EMMC_VCCQ_1_2V                          0x2
  52 #define EMMC_VCCQ_3_3V                          0x3
  53
  54 #define SDHC_SLOT_RETUNING_REQ_CTRL             0x0144
  55 /* retuning compatible */
  56 #define RETUNING_COMPATIBLE                     0x1
  57
  58 /* Xenon specific Mode Select value */
  59 #define XENON_SDHCI_CTRL_HS200                  0x5
  60 #define XENON_SDHCI_CTRL_HS400                  0x6
  61
  62 #define EMMC_PHY_REG_BASE                       0x170
  63 #define EMMC_PHY_TIMING_ADJUST                  EMMC_PHY_REG_BASE
  64 #define OUTPUT_QSN_PHASE_SELECT                 BIT(17)
  65 #define SAMPL_INV_QSP_PHASE_SELECT              BIT(18)
  66 #define SAMPL_INV_QSP_PHASE_SELECT_SHIFT        18
  67 #define EMMC_PHY_SLOW_MODE                      BIT(29)
  68 #define PHY_INITIALIZAION                       BIT(31)
  69 #define WAIT_CYCLE_BEFORE_USING_MASK            0xf
  70 #define WAIT_CYCLE_BEFORE_USING_SHIFT           12
  71 #define FC_SYNC_EN_DURATION_MASK                0xf
  72 #define FC_SYNC_EN_DURATION_SHIFT               8
  73 #define FC_SYNC_RST_EN_DURATION_MASK            0xf
  74 #define FC_SYNC_RST_EN_DURATION_SHIFT           4
  75 #define FC_SYNC_RST_DURATION_MASK               0xf
  76 #define FC_SYNC_RST_DURATION_SHIFT              0
  77
  78 #define EMMC_PHY_FUNC_CONTROL                   (EMMC_PHY_REG_BASE + 0x4)
  79 #define DQ_ASYNC_MODE                           BIT(4)
  80 #define DQ_DDR_MODE_SHIFT                       8
  81 #define DQ_DDR_MODE_MASK                        0xff
  82 #define CMD_DDR_MODE                            BIT(16)
  83
  84 #define EMMC_PHY_PAD_CONTROL                    (EMMC_PHY_REG_BASE + 0x8)
  85 #define REC_EN_SHIFT                            24
  86 #define REC_EN_MASK                             0xf
  87 #define FC_DQ_RECEN                             BIT(24)
  88 #define FC_CMD_RECEN                            BIT(25)
  89 #define FC_QSP_RECEN                            BIT(26)
  90 #define FC_QSN_RECEN                            BIT(27)
  91 #define OEN_QSN                                 BIT(28)
  92 #define AUTO_RECEN_CTRL                         BIT(30)
  93
  94 #define EMMC_PHY_PAD_CONTROL1                   (EMMC_PHY_REG_BASE + 0xc)
  95 #define EMMC5_1_FC_QSP_PD                       BIT(9)
  96 #define EMMC5_1_FC_QSP_PU                       BIT(25)
  97 #define EMMC5_1_FC_CMD_PD                       BIT(8)
  98 #define EMMC5_1_FC_CMD_PU                       BIT(24)
  99 #define EMMC5_1_FC_DQ_PD                        0xff
 100 #define EMMC5_1_FC_DQ_PU                        (0xff << 16)
 101
 102 #define SDHCI_RETUNE_EVT_INTSIG                 0x00001000
 103
 104 /* Hyperion only have one slot 0 */
 105 #define XENON_MMC_SLOT_ID_HYPERION              0
 106
 107 #define MMC_TIMING_LEGACY       0
 108 #define MMC_TIMING_MMC_HS       1
 109 #define MMC_TIMING_SD_HS        2
 110 #define MMC_TIMING_UHS_SDR12    3
 111 #define MMC_TIMING_UHS_SDR25    4
 112 #define MMC_TIMING_UHS_SDR50    5
 113 #define MMC_TIMING_UHS_SDR104   6
 114 #define MMC_TIMING_UHS_DDR50    7
 115 #define MMC_TIMING_MMC_DDR52    8
 116 #define MMC_TIMING_MMC_HS200    9
 117 #define MMC_TIMING_MMC_HS400    10
 118
 119 #define XENON_MMC_MAX_CLK       400000000
 120 #define XENON_MMC_3V3_UV        3300000
 121 #define XENON_MMC_1V8_UV        1800000
 122
 123 enum soc_pad_ctrl_type {
 124         SOC_PAD_SD,
 125         SOC_PAD_FIXED_1_8V,
 126 };
 127
 128 struct xenon_sdhci_plat {
 129         struct mmc_config cfg;
 130         struct mmc mmc;
 131 };
 132
 133 struct xenon_sdhci_priv {
 134         struct sdhci_host host;
 135
 136         u8 timing;
 137
 138         unsigned int clock;
 139
 140         void *pad_ctrl_reg;
 141         int pad_type;
 142
 143         struct udevice *vqmmc;
 144 };
 145
 146 static int xenon_mmc_phy_init(struct sdhci_host *host)
 147 {
 148         struct xenon_sdhci_priv *priv = host->mmc->priv;
 149         u32 clock = priv->clock;
 150         u32 time;
 151         u32 var;
 152
 153         /* Enable QSP PHASE SELECT */
 154         var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST);
 155         var |= SAMPL_INV_QSP_PHASE_SELECT;
 156         if ((priv->timing == MMC_TIMING_UHS_SDR50) ||
 157             (priv->timing == MMC_TIMING_UHS_SDR25) ||
 158             (priv->timing == MMC_TIMING_UHS_SDR12) ||
 159             (priv->timing == MMC_TIMING_SD_HS) ||
 160             (priv->timing == MMC_TIMING_LEGACY))
 161                 var |= EMMC_PHY_SLOW_MODE;
 162         sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST);
 163
 164         /* Poll for host MMC PHY clock init to be stable */
 165         /* Wait up to 10ms */
 166         time = 100;
 167         while (time--) {
 168                 var = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
 169                 if (var & SDHCI_CLOCK_INT_STABLE)
 170                         break;
 171
 172                 udelay(100);
 173         }
 174
 175         if (time <= 0) {
 176                 pr_err("Failed to enable MMC internal clock in time\n");
 177                 return -ETIMEDOUT;
 178         }
 179
 180         /* Init PHY */
 181         var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST);
 182         var |= PHY_INITIALIZAION;
 183         sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST);
 184
 185         if (clock == 0) {
 186                 /* Use the possibly slowest bus frequency value */
 187                 clock = 100000;
 188         }
 189
 190         /* Poll for host eMMC PHY init to complete */
 191         /* Wait up to 10ms */
 192         time = 100;
 193         while (time--) {
 194                 var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST);
 195                 var &= PHY_INITIALIZAION;
 196                 if (!var)
 197                         break;
 198
 199                 /* wait for host eMMC PHY init to complete */
 200                 udelay(100);
 201         }
 202
 203         if (time <= 0) {
 204                 pr_err("Failed to init MMC PHY in time\n");
 205                 return -ETIMEDOUT;
 206         }
 207
 208         return 0;
 209 }
 210
 211 #define ARMADA_3700_SOC_PAD_1_8V        0x1
 212 #define ARMADA_3700_SOC_PAD_3_3V        0x0
 213
 214 static void armada_3700_soc_pad_voltage_set(struct sdhci_host *host)
 215 {
 216         struct xenon_sdhci_priv *priv = host->mmc->priv;
 217
 218         if (priv->pad_type == SOC_PAD_FIXED_1_8V)
 219                 writel(ARMADA_3700_SOC_PAD_1_8V, priv->pad_ctrl_reg);
 220         else if (priv->pad_type == SOC_PAD_SD)
 221                 writel(ARMADA_3700_SOC_PAD_3_3V, priv->pad_ctrl_reg);
 222 }
 223
 224 static int xenon_mmc_start_signal_voltage_switch(struct sdhci_host *host)
 225 {
 226         struct xenon_sdhci_priv *priv = host->mmc->priv;
 227         u8 voltage;
 228         u32 ctrl;
 229         int ret = 0;
 230
 231         /* If there is no vqmmc regulator, return */
 232         if (!priv->vqmmc)
 233                 return 0;
 234
 235         if (priv->pad_type == SOC_PAD_FIXED_1_8V) {
 236                 /* Switch to 1.8v */
 237                 ret = regulator_set_value(priv->vqmmc,
 238                                           XENON_MMC_1V8_UV);
 239         } else if (priv->pad_type == SOC_PAD_SD) {
 240                 /* Get voltage info */
 241                 voltage = sdhci_readb(host, SDHCI_POWER_CONTROL);
 242                 voltage &= ~SDHCI_POWER_ON;
 243
 244                 if (voltage == SDHCI_POWER_330) {
 245                         /* Switch to 3.3v */
 246                         ret = regulator_set_value(priv->vqmmc,
 247                                                   XENON_MMC_3V3_UV);
 248                 } else {
 249                         /* Switch to 1.8v */
 250                         ret = regulator_set_value(priv->vqmmc,
 251                                                   XENON_MMC_1V8_UV);
 252                 }
 253         }
 254
 255         /* Set VCCQ, eMMC mode: 1.8V; SD/SDIO mode: 3.3V */
 256         ctrl = sdhci_readl(host, SDHC_SLOT_EMMC_CTRL);
 257         if (IS_SD(host->mmc))
 258                 ctrl |= EMMC_VCCQ_3_3V;
 259         else
 260                 ctrl |= EMMC_VCCQ_1_8V;
 261         sdhci_writel(host, ctrl, SDHC_SLOT_EMMC_CTRL);
 262
 263         if (ret)
 264                 printf("Signal voltage switch fail\n");
 265
 266         return ret;
 267 }
 268
 269 static void xenon_mmc_phy_set(struct sdhci_host *host)
 270 {
 271         struct xenon_sdhci_priv *priv = host->mmc->priv;
 272         u32 var;
 273
 274         /* Setup pad, set bit[30], bit[28] and bits[26:24] */
 275         var = sdhci_readl(host, EMMC_PHY_PAD_CONTROL);
 276         var |= AUTO_RECEN_CTRL | OEN_QSN | FC_QSP_RECEN |
 277                 FC_CMD_RECEN | FC_DQ_RECEN;
 278         sdhci_writel(host, var, EMMC_PHY_PAD_CONTROL);
 279
 280         /* Set CMD and DQ Pull Up */
 281         var = sdhci_readl(host, EMMC_PHY_PAD_CONTROL1);
 282         var |= (EMMC5_1_FC_CMD_PU | EMMC5_1_FC_DQ_PU);
 283         var &= ~(EMMC5_1_FC_CMD_PD | EMMC5_1_FC_DQ_PD);
 284         sdhci_writel(host, var, EMMC_PHY_PAD_CONTROL1);
 285
 286         /*
 287          * If timing belongs to high speed, set bit[17] of
 288          * EMMC_PHY_TIMING_ADJUST register
 289          */
 290         if ((priv->timing == MMC_TIMING_MMC_HS400) ||
 291             (priv->timing == MMC_TIMING_MMC_HS200) ||
 292             (priv->timing == MMC_TIMING_UHS_SDR50) ||
 293             (priv->timing == MMC_TIMING_UHS_SDR104) ||
 294             (priv->timing == MMC_TIMING_UHS_DDR50) ||
 295             (priv->timing == MMC_TIMING_UHS_SDR25) ||
 296             (priv->timing == MMC_TIMING_MMC_DDR52)) {
 297                 var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST);
 298                 var |= OUTPUT_QSN_PHASE_SELECT;
 299                 sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST);
 300         }
 301
 302         /*
 303          * When setting EMMC_PHY_FUNC_CONTROL register,
 304          * SD clock should be disabled
 305          */
 306         var = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
 307         var &= ~SDHCI_CLOCK_CARD_EN;
 308         sdhci_writew(host, var, SDHCI_CLOCK_CONTROL);
 309
 310         var = sdhci_readl(host, EMMC_PHY_FUNC_CONTROL);
 311         if (host->mmc->ddr_mode) {
 312                 var |= (DQ_DDR_MODE_MASK << DQ_DDR_MODE_SHIFT) | CMD_DDR_MODE;
 313         } else {
 314                 var &= ~((DQ_DDR_MODE_MASK << DQ_DDR_MODE_SHIFT) |
 315                          CMD_DDR_MODE);
 316         }
 317         sdhci_writel(host, var, EMMC_PHY_FUNC_CONTROL);
 318
 319         /* Enable bus clock */
 320         var = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
 321         var |= SDHCI_CLOCK_CARD_EN;
 322         sdhci_writew(host, var, SDHCI_CLOCK_CONTROL);
 323
 324         xenon_mmc_phy_init(host);
 325 }
 326
 327 /* Enable/Disable the Auto Clock Gating function of this slot */
 328 static void xenon_mmc_set_acg(struct sdhci_host *host, bool enable)
 329 {
 330         u32 var;
 331
 332         var = sdhci_readl(host, SDHC_SYS_OP_CTRL);
 333         if (enable)
 334                 var &= ~AUTO_CLKGATE_DISABLE_MASK;
 335         else
 336                 var |= AUTO_CLKGATE_DISABLE_MASK;
 337
 338         sdhci_writel(host, var, SDHC_SYS_OP_CTRL);
 339 }
 340
 341 #define SLOT_MASK(slot)         BIT(slot)
 342
 343 /* Enable specific slot */
 344 static void xenon_mmc_enable_slot(struct sdhci_host *host, u8 slot)
 345 {
 346         u32 var;
 347
 348         var = sdhci_readl(host, SDHC_SYS_OP_CTRL);
 349         var |= SLOT_MASK(slot) << SLOT_ENABLE_SHIFT;
 350         sdhci_writel(host, var, SDHC_SYS_OP_CTRL);
 351 }
 352
 353 /* Enable Parallel Transfer Mode */
 354 static void xenon_mmc_enable_parallel_tran(struct sdhci_host *host, u8 slot)
 355 {
 356         u32 var;
 357
 358         var = sdhci_readl(host, SDHC_SYS_EXT_OP_CTRL);
 359         var |= SLOT_MASK(slot);
 360         sdhci_writel(host, var, SDHC_SYS_EXT_OP_CTRL);
 361 }
 362
 363 static void xenon_mmc_disable_tuning(struct sdhci_host *host, u8 slot)
 364 {
 365         u32 var;
 366
 367         /* Clear the Re-Tuning Request functionality */
 368         var = sdhci_readl(host, SDHC_SLOT_RETUNING_REQ_CTRL);
 369         var &= ~RETUNING_COMPATIBLE;
 370         sdhci_writel(host, var, SDHC_SLOT_RETUNING_REQ_CTRL);
 371
 372         /* Clear the Re-tuning Event Signal Enable */
 373         var = sdhci_readl(host, SDHCI_SIGNAL_ENABLE);
 374         var &= ~SDHCI_RETUNE_EVT_INTSIG;
 375         sdhci_writel(host, var, SDHCI_SIGNAL_ENABLE);
 376 }
 377
 378 /* Mask command conflict error */
 379 static void xenon_mask_cmd_conflict_err(struct sdhci_host *host)
 380 {
 381         u32  reg;
 382
 383         reg = sdhci_readl(host, SDHC_SYS_EXT_OP_CTRL);
 384         reg |= MASK_CMD_CONFLICT_ERROR;
 385         sdhci_writel(host, reg, SDHC_SYS_EXT_OP_CTRL);
 386 }
 387
 388 /* Platform specific function for post set_ios configuration */
 389 static int xenon_sdhci_set_ios_post(struct sdhci_host *host)
 390 {
 391         struct xenon_sdhci_priv *priv = host->mmc->priv;
 392         uint speed = host->mmc->tran_speed;
 393         int pwr_18v = 0;
 394
 395         /*
 396          * Signal Voltage Switching is only applicable for Host Controllers
 397          * v3.00 and above.
 398          */
 399         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 400                 xenon_mmc_start_signal_voltage_switch(host);
 401
 402         if ((sdhci_readb(host, SDHCI_POWER_CONTROL) & ~SDHCI_POWER_ON) ==
 403             SDHCI_POWER_180)
 404                 pwr_18v = 1;
 405
 406         /* Set timing variable according to the configured speed */
 407         if (IS_SD(host->mmc)) {
 408                 /* SD/SDIO */
 409                 if (pwr_18v) {
 410                         if (host->mmc->ddr_mode)
 411                                 priv->timing = MMC_TIMING_UHS_DDR50;
 412                         else if (speed <= 25000000)
 413                                 priv->timing = MMC_TIMING_UHS_SDR25;
 414                         else
 415                                 priv->timing = MMC_TIMING_UHS_SDR50;
 416                 } else {
 417                         if (speed <= 25000000)
 418                                 priv->timing = MMC_TIMING_LEGACY;
 419                         else
 420                                 priv->timing = MMC_TIMING_SD_HS;
 421                 }
 422         } else {
 423                 /* eMMC */
 424                 if (host->mmc->ddr_mode)
 425                         priv->timing = MMC_TIMING_MMC_DDR52;
 426                 else if (speed <= 26000000)
 427                         priv->timing = MMC_TIMING_LEGACY;
 428                 else
 429                         priv->timing = MMC_TIMING_MMC_HS;
 430         }
 431
 432         /* Re-init the PHY */
 433         xenon_mmc_phy_set(host);
 434
 435         return 0;
 436 }
 437
 438 /* Install a driver specific handler for post set_ios configuration */
 439 static const struct sdhci_ops xenon_sdhci_ops = {
 440         .set_ios_post = xenon_sdhci_set_ios_post
 441 };
 442
 443 static int xenon_sdhci_probe(struct udevice *dev)
 444 {
 445         struct xenon_sdhci_plat *plat = dev_get_platdata(dev);
 446         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 447         struct xenon_sdhci_priv *priv = dev_get_priv(dev);
 448         struct sdhci_host *host = dev_get_priv(dev);
 449         int ret;
 450
 451         host->mmc = &plat->mmc;
 452         host->mmc->priv = host;
 453         host->mmc->dev = dev;
 454         upriv->mmc = host->mmc;
 455
 456         /* Set quirks */
 457         host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_32BIT_DMA_ADDR;
 458
 459         /* Set default timing */
 460         priv->timing = MMC_TIMING_LEGACY;
 461
 462         /* Get the vqmmc regulator if there is */
 463         device_get_supply_regulator(dev, "vqmmc-supply", &priv->vqmmc);
 464         /* Set the initial voltage value to 3.3V if there is regulator */
 465         if (priv->vqmmc) {
 466                 ret = regulator_set_value(priv->vqmmc,
 467                                           XENON_MMC_3V3_UV);
 468                 if (ret) {
 469                         printf("Failed to set VQMMC regulator to 3.3V\n");
 470                         return ret;
 471                 }
 472         }
 473
 474         /* Disable auto clock gating during init */
 475         xenon_mmc_set_acg(host, false);
 476
 477         /* Enable slot */
 478         xenon_mmc_enable_slot(host, XENON_MMC_SLOT_ID_HYPERION);
 479
 480         /*
 481          * Set default power on SoC PHY PAD register (currently only
 482          * available on the Armada 3700)
 483          */
 484         if (priv->pad_ctrl_reg)
 485                 armada_3700_soc_pad_voltage_set(host);
 486
 487         host->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_DDR_52MHz;
 488
 489         ret = mmc_of_parse(dev, &plat->cfg);
 490         if (ret)
 491                 return ret;
 492
 493         host->ops = &xenon_sdhci_ops;
 494
 495         host->max_clk = XENON_MMC_MAX_CLK;
 496         ret = sdhci_setup_cfg(&plat->cfg, host, XENON_MMC_MAX_CLK, 0);
 497         if (ret)
 498                 return ret;
 499
 500         ret = sdhci_probe(dev);
 501         if (ret)
 502                 return ret;
 503
 504         /* Enable parallel transfer */
 505         xenon_mmc_enable_parallel_tran(host, XENON_MMC_SLOT_ID_HYPERION);
 506
 507         /* Disable tuning functionality of this slot */
 508         xenon_mmc_disable_tuning(host, XENON_MMC_SLOT_ID_HYPERION);
 509
 510         /* Enable auto clock gating after init */
 511         xenon_mmc_set_acg(host, true);
 512
 513         xenon_mask_cmd_conflict_err(host);
 514
 515         return ret;
 516 }
 517
 518 static int xenon_sdhci_ofdata_to_platdata(struct udevice *dev)
 519 {
 520         struct sdhci_host *host = dev_get_priv(dev);
 521         struct xenon_sdhci_priv *priv = dev_get_priv(dev);
 522         const char *name;
 523
 524         host->name = dev->name;
 525         host->ioaddr = dev_read_addr_ptr(dev);
 526
 527         if (device_is_compatible(dev, "marvell,armada-3700-sdhci"))
 528                 priv->pad_ctrl_reg = (void *)devfdt_get_addr_index(dev, 1);
 529
 530         name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "marvell,pad-type",
 531                            NULL);
 532         if (name) {
 533                 if (0 == strncmp(name, "sd", 2)) {
 534                         priv->pad_type = SOC_PAD_SD;
 535                 } else if (0 == strncmp(name, "fixed-1-8v", 10)) {
 536                         priv->pad_type = SOC_PAD_FIXED_1_8V;
 537                 } else {
 538                         printf("Unsupported SOC PHY PAD ctrl type %s\n", name);
 539                         return -EINVAL;
 540                 }
 541         }
 542
 543         return 0;
 544 }
 545
 546 static int xenon_sdhci_bind(struct udevice *dev)
 547 {
 548         struct xenon_sdhci_plat *plat = dev_get_platdata(dev);
 549
 550         return sdhci_bind(dev, &plat->mmc, &plat->cfg);
 551 }
 552
 553 static const struct udevice_id xenon_sdhci_ids[] = {
 554         { .compatible = "marvell,armada-8k-sdhci",},
 555         { .compatible = "marvell,armada-3700-sdhci",},
 556         { }
 557 };
 558
 559 U_BOOT_DRIVER(xenon_sdhci_drv) = {
 560         .name           = "xenon_sdhci",
 561         .id             = UCLASS_MMC,
 562         .of_match       = xenon_sdhci_ids,
 563         .ofdata_to_platdata = xenon_sdhci_ofdata_to_platdata,
 564         .ops            = &sdhci_ops,
 565         .bind           = xenon_sdhci_bind,
 566         .probe          = xenon_sdhci_probe,
 567         .priv_auto_alloc_size = sizeof(struct xenon_sdhci_priv),
 568         .platdata_auto_alloc_size = sizeof(struct xenon_sdhci_plat),
 569 };