1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for Marvell SOC Platform Group Xenon SDHC as a platform device
5 * Copyright (C) 2016 Marvell, All Rights Reserved.
7 * Author: Victor Gu <xigu@marvell.com>
10 * Included parts of the Linux driver version which was written by:
11 * Hu Ziji <huziji@marvell.com>
13 * Ported to from Marvell 2015.01 to mainline U-Boot 2017.01:
14 * Stefan Roese <sr@denx.de>
20 #include <linux/bitops.h>
21 #include <linux/delay.h>
22 #include <linux/libfdt.h>
25 #include <power/regulator.h>
27 DECLARE_GLOBAL_DATA_PTR;
29 /* Register Offset of SD Host Controller SOCP self-defined register */
30 #define SDHC_SYS_CFG_INFO 0x0104
31 #define SLOT_TYPE_SDIO_SHIFT 24
32 #define SLOT_TYPE_EMMC_MASK 0xFF
33 #define SLOT_TYPE_EMMC_SHIFT 16
34 #define SLOT_TYPE_SD_SDIO_MMC_MASK 0xFF
35 #define SLOT_TYPE_SD_SDIO_MMC_SHIFT 8
36 #define NR_SUPPORTED_SLOT_MASK 0x7
38 #define SDHC_SYS_OP_CTRL 0x0108
39 #define AUTO_CLKGATE_DISABLE_MASK BIT(20)
40 #define SDCLK_IDLEOFF_ENABLE_SHIFT 8
41 #define SLOT_ENABLE_SHIFT 0
43 #define SDHC_SYS_EXT_OP_CTRL 0x010C
44 #define MASK_CMD_CONFLICT_ERROR BIT(8)
46 #define SDHC_SLOT_EMMC_CTRL 0x0130
47 #define ENABLE_DATA_STROBE_SHIFT 24
48 #define SET_EMMC_RSTN_SHIFT 16
49 #define EMMC_VCCQ_MASK 0x3
50 #define EMMC_VCCQ_1_8V 0x1
51 #define EMMC_VCCQ_1_2V 0x2
52 #define EMMC_VCCQ_3_3V 0x3
54 #define SDHC_SLOT_RETUNING_REQ_CTRL 0x0144
55 /* retuning compatible */
56 #define RETUNING_COMPATIBLE 0x1
58 /* Xenon specific Mode Select value */
59 #define XENON_SDHCI_CTRL_HS200 0x5
60 #define XENON_SDHCI_CTRL_HS400 0x6
62 #define EMMC_PHY_REG_BASE 0x170
63 #define EMMC_PHY_TIMING_ADJUST EMMC_PHY_REG_BASE
64 #define OUTPUT_QSN_PHASE_SELECT BIT(17)
65 #define SAMPL_INV_QSP_PHASE_SELECT BIT(18)
66 #define SAMPL_INV_QSP_PHASE_SELECT_SHIFT 18
67 #define EMMC_PHY_SLOW_MODE BIT(29)
68 #define PHY_INITIALIZAION BIT(31)
69 #define WAIT_CYCLE_BEFORE_USING_MASK 0xf
70 #define WAIT_CYCLE_BEFORE_USING_SHIFT 12
71 #define FC_SYNC_EN_DURATION_MASK 0xf
72 #define FC_SYNC_EN_DURATION_SHIFT 8
73 #define FC_SYNC_RST_EN_DURATION_MASK 0xf
74 #define FC_SYNC_RST_EN_DURATION_SHIFT 4
75 #define FC_SYNC_RST_DURATION_MASK 0xf
76 #define FC_SYNC_RST_DURATION_SHIFT 0
78 #define EMMC_PHY_FUNC_CONTROL (EMMC_PHY_REG_BASE + 0x4)
79 #define DQ_ASYNC_MODE BIT(4)
80 #define DQ_DDR_MODE_SHIFT 8
81 #define DQ_DDR_MODE_MASK 0xff
82 #define CMD_DDR_MODE BIT(16)
84 #define EMMC_PHY_PAD_CONTROL (EMMC_PHY_REG_BASE + 0x8)
85 #define REC_EN_SHIFT 24
86 #define REC_EN_MASK 0xf
87 #define FC_DQ_RECEN BIT(24)
88 #define FC_CMD_RECEN BIT(25)
89 #define FC_QSP_RECEN BIT(26)
90 #define FC_QSN_RECEN BIT(27)
91 #define OEN_QSN BIT(28)
92 #define AUTO_RECEN_CTRL BIT(30)
94 #define EMMC_PHY_PAD_CONTROL1 (EMMC_PHY_REG_BASE + 0xc)
95 #define EMMC5_1_FC_QSP_PD BIT(9)
96 #define EMMC5_1_FC_QSP_PU BIT(25)
97 #define EMMC5_1_FC_CMD_PD BIT(8)
98 #define EMMC5_1_FC_CMD_PU BIT(24)
99 #define EMMC5_1_FC_DQ_PD 0xff
100 #define EMMC5_1_FC_DQ_PU (0xff << 16)
102 #define SDHCI_RETUNE_EVT_INTSIG 0x00001000
104 /* Hyperion only have one slot 0 */
105 #define XENON_MMC_SLOT_ID_HYPERION 0
107 #define XENON_MMC_MAX_CLK 400000000
108 #define XENON_MMC_3V3_UV 3300000
109 #define XENON_MMC_1V8_UV 1800000
111 enum soc_pad_ctrl_type {
116 struct xenon_sdhci_plat {
117 struct mmc_config cfg;
121 struct xenon_sdhci_priv {
122 struct sdhci_host host;
131 struct udevice *vqmmc;
134 static int xenon_mmc_phy_init(struct sdhci_host *host)
136 struct xenon_sdhci_priv *priv = host->mmc->priv;
137 u32 clock = priv->clock;
141 /* Enable QSP PHASE SELECT */
142 var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST);
143 var |= SAMPL_INV_QSP_PHASE_SELECT;
144 if ((priv->timing == MMC_TIMING_UHS_SDR50) ||
145 (priv->timing == MMC_TIMING_UHS_SDR25) ||
146 (priv->timing == MMC_TIMING_UHS_SDR12) ||
147 (priv->timing == MMC_TIMING_SD_HS) ||
148 (priv->timing == MMC_TIMING_LEGACY))
149 var |= EMMC_PHY_SLOW_MODE;
150 sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST);
152 /* Poll for host MMC PHY clock init to be stable */
153 /* Wait up to 10ms */
156 var = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
157 if (var & SDHCI_CLOCK_INT_STABLE)
164 pr_err("Failed to enable MMC internal clock in time\n");
169 var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST);
170 var |= PHY_INITIALIZAION;
171 sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST);
174 /* Use the possibly slowest bus frequency value */
178 /* Poll for host eMMC PHY init to complete */
179 /* Wait up to 10ms */
182 var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST);
183 var &= PHY_INITIALIZAION;
187 /* wait for host eMMC PHY init to complete */
192 pr_err("Failed to init MMC PHY in time\n");
199 #define ARMADA_3700_SOC_PAD_1_8V 0x1
200 #define ARMADA_3700_SOC_PAD_3_3V 0x0
202 static void armada_3700_soc_pad_voltage_set(struct sdhci_host *host)
204 struct xenon_sdhci_priv *priv = host->mmc->priv;
206 if (priv->pad_type == SOC_PAD_FIXED_1_8V)
207 writel(ARMADA_3700_SOC_PAD_1_8V, priv->pad_ctrl_reg);
208 else if (priv->pad_type == SOC_PAD_SD)
209 writel(ARMADA_3700_SOC_PAD_3_3V, priv->pad_ctrl_reg);
212 static int xenon_mmc_start_signal_voltage_switch(struct sdhci_host *host)
214 struct xenon_sdhci_priv *priv = host->mmc->priv;
219 /* If there is no vqmmc regulator, return */
223 if (priv->pad_type == SOC_PAD_FIXED_1_8V) {
225 ret = regulator_set_value(priv->vqmmc,
227 } else if (priv->pad_type == SOC_PAD_SD) {
228 /* Get voltage info */
229 voltage = sdhci_readb(host, SDHCI_POWER_CONTROL);
230 voltage &= ~SDHCI_POWER_ON;
232 if (voltage == SDHCI_POWER_330) {
234 ret = regulator_set_value(priv->vqmmc,
238 ret = regulator_set_value(priv->vqmmc,
243 /* Set VCCQ, eMMC mode: 1.8V; SD/SDIO mode: 3.3V */
244 ctrl = sdhci_readl(host, SDHC_SLOT_EMMC_CTRL);
245 if (IS_SD(host->mmc))
246 ctrl |= EMMC_VCCQ_3_3V;
248 ctrl |= EMMC_VCCQ_1_8V;
249 sdhci_writel(host, ctrl, SDHC_SLOT_EMMC_CTRL);
252 printf("Signal voltage switch fail\n");
257 static void xenon_mmc_phy_set(struct sdhci_host *host)
259 struct xenon_sdhci_priv *priv = host->mmc->priv;
262 /* Setup pad, set bit[30], bit[28] and bits[26:24] */
263 var = sdhci_readl(host, EMMC_PHY_PAD_CONTROL);
264 var |= AUTO_RECEN_CTRL | OEN_QSN | FC_QSP_RECEN |
265 FC_CMD_RECEN | FC_DQ_RECEN;
266 sdhci_writel(host, var, EMMC_PHY_PAD_CONTROL);
268 /* Set CMD and DQ Pull Up */
269 var = sdhci_readl(host, EMMC_PHY_PAD_CONTROL1);
270 var |= (EMMC5_1_FC_CMD_PU | EMMC5_1_FC_DQ_PU);
271 var &= ~(EMMC5_1_FC_CMD_PD | EMMC5_1_FC_DQ_PD);
272 sdhci_writel(host, var, EMMC_PHY_PAD_CONTROL1);
275 * If timing belongs to high speed, set bit[17] of
276 * EMMC_PHY_TIMING_ADJUST register
278 if ((priv->timing == MMC_TIMING_MMC_HS400) ||
279 (priv->timing == MMC_TIMING_MMC_HS200) ||
280 (priv->timing == MMC_TIMING_UHS_SDR50) ||
281 (priv->timing == MMC_TIMING_UHS_SDR104) ||
282 (priv->timing == MMC_TIMING_UHS_DDR50) ||
283 (priv->timing == MMC_TIMING_UHS_SDR25) ||
284 (priv->timing == MMC_TIMING_MMC_DDR52)) {
285 var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST);
286 var |= OUTPUT_QSN_PHASE_SELECT;
287 sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST);
291 * When setting EMMC_PHY_FUNC_CONTROL register,
292 * SD clock should be disabled
294 var = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
295 var &= ~SDHCI_CLOCK_CARD_EN;
296 sdhci_writew(host, var, SDHCI_CLOCK_CONTROL);
298 var = sdhci_readl(host, EMMC_PHY_FUNC_CONTROL);
299 if (host->mmc->ddr_mode) {
300 var |= (DQ_DDR_MODE_MASK << DQ_DDR_MODE_SHIFT) | CMD_DDR_MODE;
302 var &= ~((DQ_DDR_MODE_MASK << DQ_DDR_MODE_SHIFT) |
305 sdhci_writel(host, var, EMMC_PHY_FUNC_CONTROL);
307 /* Enable bus clock */
308 var = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
309 var |= SDHCI_CLOCK_CARD_EN;
310 sdhci_writew(host, var, SDHCI_CLOCK_CONTROL);
312 xenon_mmc_phy_init(host);
315 /* Enable/Disable the Auto Clock Gating function of this slot */
316 static void xenon_mmc_set_acg(struct sdhci_host *host, bool enable)
320 var = sdhci_readl(host, SDHC_SYS_OP_CTRL);
322 var &= ~AUTO_CLKGATE_DISABLE_MASK;
324 var |= AUTO_CLKGATE_DISABLE_MASK;
326 sdhci_writel(host, var, SDHC_SYS_OP_CTRL);
329 #define SLOT_MASK(slot) BIT(slot)
331 /* Enable specific slot */
332 static void xenon_mmc_enable_slot(struct sdhci_host *host, u8 slot)
336 var = sdhci_readl(host, SDHC_SYS_OP_CTRL);
337 var |= SLOT_MASK(slot) << SLOT_ENABLE_SHIFT;
338 sdhci_writel(host, var, SDHC_SYS_OP_CTRL);
341 /* Enable Parallel Transfer Mode */
342 static void xenon_mmc_enable_parallel_tran(struct sdhci_host *host, u8 slot)
346 var = sdhci_readl(host, SDHC_SYS_EXT_OP_CTRL);
347 var |= SLOT_MASK(slot);
348 sdhci_writel(host, var, SDHC_SYS_EXT_OP_CTRL);
351 static void xenon_mmc_disable_tuning(struct sdhci_host *host, u8 slot)
355 /* Clear the Re-Tuning Request functionality */
356 var = sdhci_readl(host, SDHC_SLOT_RETUNING_REQ_CTRL);
357 var &= ~RETUNING_COMPATIBLE;
358 sdhci_writel(host, var, SDHC_SLOT_RETUNING_REQ_CTRL);
360 /* Clear the Re-tuning Event Signal Enable */
361 var = sdhci_readl(host, SDHCI_SIGNAL_ENABLE);
362 var &= ~SDHCI_RETUNE_EVT_INTSIG;
363 sdhci_writel(host, var, SDHCI_SIGNAL_ENABLE);
366 /* Mask command conflict error */
367 static void xenon_mask_cmd_conflict_err(struct sdhci_host *host)
371 reg = sdhci_readl(host, SDHC_SYS_EXT_OP_CTRL);
372 reg |= MASK_CMD_CONFLICT_ERROR;
373 sdhci_writel(host, reg, SDHC_SYS_EXT_OP_CTRL);
376 /* Platform specific function for post set_ios configuration */
377 static int xenon_sdhci_set_ios_post(struct sdhci_host *host)
379 struct xenon_sdhci_priv *priv = host->mmc->priv;
380 uint speed = host->mmc->tran_speed;
384 * Signal Voltage Switching is only applicable for Host Controllers
387 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
388 xenon_mmc_start_signal_voltage_switch(host);
390 if ((sdhci_readb(host, SDHCI_POWER_CONTROL) & ~SDHCI_POWER_ON) ==
394 /* Set timing variable according to the configured speed */
395 if (IS_SD(host->mmc)) {
398 if (host->mmc->ddr_mode)
399 priv->timing = MMC_TIMING_UHS_DDR50;
400 else if (speed <= 25000000)
401 priv->timing = MMC_TIMING_UHS_SDR25;
403 priv->timing = MMC_TIMING_UHS_SDR50;
405 if (speed <= 25000000)
406 priv->timing = MMC_TIMING_LEGACY;
408 priv->timing = MMC_TIMING_SD_HS;
412 if (host->mmc->ddr_mode)
413 priv->timing = MMC_TIMING_MMC_DDR52;
414 else if (speed <= 26000000)
415 priv->timing = MMC_TIMING_LEGACY;
417 priv->timing = MMC_TIMING_MMC_HS;
420 /* Re-init the PHY */
421 xenon_mmc_phy_set(host);
426 /* Install a driver specific handler for post set_ios configuration */
427 static const struct sdhci_ops xenon_sdhci_ops = {
428 .set_ios_post = xenon_sdhci_set_ios_post
431 static int xenon_sdhci_probe(struct udevice *dev)
433 struct xenon_sdhci_plat *plat = dev_get_plat(dev);
434 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
435 struct xenon_sdhci_priv *priv = dev_get_priv(dev);
436 struct sdhci_host *host = dev_get_priv(dev);
439 host->mmc = &plat->mmc;
440 host->mmc->priv = host;
441 host->mmc->dev = dev;
442 upriv->mmc = host->mmc;
445 host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_32BIT_DMA_ADDR;
447 /* Set default timing */
448 priv->timing = MMC_TIMING_LEGACY;
450 /* Get the vqmmc regulator if there is */
451 device_get_supply_regulator(dev, "vqmmc-supply", &priv->vqmmc);
452 /* Set the initial voltage value to 3.3V if there is regulator */
454 ret = regulator_set_value(priv->vqmmc,
457 printf("Failed to set VQMMC regulator to 3.3V\n");
462 /* Disable auto clock gating during init */
463 xenon_mmc_set_acg(host, false);
466 xenon_mmc_enable_slot(host, XENON_MMC_SLOT_ID_HYPERION);
469 * Set default power on SoC PHY PAD register (currently only
470 * available on the Armada 3700)
472 if (priv->pad_ctrl_reg)
473 armada_3700_soc_pad_voltage_set(host);
475 host->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_DDR_52MHz;
477 ret = mmc_of_parse(dev, &plat->cfg);
481 host->ops = &xenon_sdhci_ops;
483 host->max_clk = XENON_MMC_MAX_CLK;
484 ret = sdhci_setup_cfg(&plat->cfg, host, XENON_MMC_MAX_CLK, 0);
488 ret = sdhci_probe(dev);
492 /* Enable parallel transfer */
493 xenon_mmc_enable_parallel_tran(host, XENON_MMC_SLOT_ID_HYPERION);
495 /* Disable tuning functionality of this slot */
496 xenon_mmc_disable_tuning(host, XENON_MMC_SLOT_ID_HYPERION);
498 /* Enable auto clock gating after init */
499 xenon_mmc_set_acg(host, true);
501 xenon_mask_cmd_conflict_err(host);
506 static int xenon_sdhci_of_to_plat(struct udevice *dev)
508 struct sdhci_host *host = dev_get_priv(dev);
509 struct xenon_sdhci_priv *priv = dev_get_priv(dev);
512 host->name = dev->name;
513 host->ioaddr = dev_read_addr_ptr(dev);
515 if (device_is_compatible(dev, "marvell,armada-3700-sdhci"))
516 priv->pad_ctrl_reg = (void *)devfdt_get_addr_index(dev, 1);
518 name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "marvell,pad-type",
521 if (0 == strncmp(name, "sd", 2)) {
522 priv->pad_type = SOC_PAD_SD;
523 } else if (0 == strncmp(name, "fixed-1-8v", 10)) {
524 priv->pad_type = SOC_PAD_FIXED_1_8V;
526 printf("Unsupported SOC PHY PAD ctrl type %s\n", name);
534 static int xenon_sdhci_bind(struct udevice *dev)
536 struct xenon_sdhci_plat *plat = dev_get_plat(dev);
538 return sdhci_bind(dev, &plat->mmc, &plat->cfg);
541 static const struct udevice_id xenon_sdhci_ids[] = {
542 { .compatible = "marvell,armada-8k-sdhci",},
543 { .compatible = "marvell,armada-3700-sdhci",},
547 U_BOOT_DRIVER(xenon_sdhci_drv) = {
548 .name = "xenon_sdhci",
550 .of_match = xenon_sdhci_ids,
551 .of_to_plat = xenon_sdhci_of_to_plat,
553 .bind = xenon_sdhci_bind,
554 .probe = xenon_sdhci_probe,
555 .priv_auto = sizeof(struct xenon_sdhci_priv),
556 .plat_auto = sizeof(struct xenon_sdhci_plat),