drivers/mmc/xenon_sdhci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver for Marvell SOC Platform Group Xenon SDHC as a platform device
   4  *
   5  * Copyright (C) 2016 Marvell, All Rights Reserved.
   6  *
   7  * Author:      Victor Gu <xigu@marvell.com>
   8  * Date:        2016-8-24
   9  *
  10  * Included parts of the Linux driver version which was written by:
  11  * Hu Ziji <huziji@marvell.com>
  12  *
  13  * Ported to from Marvell 2015.01 to mainline U-Boot 2017.01:
  14  * Stefan Roese <sr@denx.de>
  15  */
  16
  17 #include <common.h>
  18 #include <dm.h>
  19 #include <fdtdec.h>
  20 #include <linux/bitops.h>
  21 #include <linux/delay.h>
  22 #include <linux/libfdt.h>
  23 #include <malloc.h>
  24 #include <sdhci.h>
  25 #include <power/regulator.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 /* Register Offset of SD Host Controller SOCP self-defined register */
  30 #define SDHC_SYS_CFG_INFO                       0x0104
  31 #define SLOT_TYPE_SDIO_SHIFT                    24
  32 #define SLOT_TYPE_EMMC_MASK                     0xFF
  33 #define SLOT_TYPE_EMMC_SHIFT                    16
  34 #define SLOT_TYPE_SD_SDIO_MMC_MASK              0xFF
  35 #define SLOT_TYPE_SD_SDIO_MMC_SHIFT             8
  36 #define NR_SUPPORTED_SLOT_MASK                  0x7
  37
  38 #define SDHC_SYS_OP_CTRL                        0x0108
  39 #define AUTO_CLKGATE_DISABLE_MASK               BIT(20)
  40 #define SDCLK_IDLEOFF_ENABLE_SHIFT              8
  41 #define SLOT_ENABLE_SHIFT                       0
  42
  43 #define SDHC_SYS_EXT_OP_CTRL                    0x010C
  44 #define MASK_CMD_CONFLICT_ERROR                 BIT(8)
  45
  46 #define SDHC_SLOT_EMMC_CTRL                     0x0130
  47 #define ENABLE_DATA_STROBE_SHIFT                24
  48 #define SET_EMMC_RSTN_SHIFT                     16
  49 #define EMMC_VCCQ_MASK                          0x3
  50 #define EMMC_VCCQ_1_8V                          0x1
  51 #define EMMC_VCCQ_1_2V                          0x2
  52 #define EMMC_VCCQ_3_3V                          0x3
  53
  54 #define SDHC_SLOT_RETUNING_REQ_CTRL             0x0144
  55 /* retuning compatible */
  56 #define RETUNING_COMPATIBLE                     0x1
  57
  58 /* Xenon specific Mode Select value */
  59 #define XENON_SDHCI_CTRL_HS200                  0x5
  60 #define XENON_SDHCI_CTRL_HS400                  0x6
  61
  62 #define EMMC_PHY_REG_BASE                       0x170
  63 #define EMMC_PHY_TIMING_ADJUST                  EMMC_PHY_REG_BASE
  64 #define OUTPUT_QSN_PHASE_SELECT                 BIT(17)
  65 #define SAMPL_INV_QSP_PHASE_SELECT              BIT(18)
  66 #define SAMPL_INV_QSP_PHASE_SELECT_SHIFT        18
  67 #define EMMC_PHY_SLOW_MODE                      BIT(29)
  68 #define PHY_INITIALIZAION                       BIT(31)
  69 #define WAIT_CYCLE_BEFORE_USING_MASK            0xf
  70 #define WAIT_CYCLE_BEFORE_USING_SHIFT           12
  71 #define FC_SYNC_EN_DURATION_MASK                0xf
  72 #define FC_SYNC_EN_DURATION_SHIFT               8
  73 #define FC_SYNC_RST_EN_DURATION_MASK            0xf
  74 #define FC_SYNC_RST_EN_DURATION_SHIFT           4
  75 #define FC_SYNC_RST_DURATION_MASK               0xf
  76 #define FC_SYNC_RST_DURATION_SHIFT              0
  77
  78 #define EMMC_PHY_FUNC_CONTROL                   (EMMC_PHY_REG_BASE + 0x4)
  79 #define DQ_ASYNC_MODE                           BIT(4)
  80 #define DQ_DDR_MODE_SHIFT                       8
  81 #define DQ_DDR_MODE_MASK                        0xff
  82 #define CMD_DDR_MODE                            BIT(16)
  83
  84 #define EMMC_PHY_PAD_CONTROL                    (EMMC_PHY_REG_BASE + 0x8)
  85 #define REC_EN_SHIFT                            24
  86 #define REC_EN_MASK                             0xf
  87 #define FC_DQ_RECEN                             BIT(24)
  88 #define FC_CMD_RECEN                            BIT(25)
  89 #define FC_QSP_RECEN                            BIT(26)
  90 #define FC_QSN_RECEN                            BIT(27)
  91 #define OEN_QSN                                 BIT(28)
  92 #define AUTO_RECEN_CTRL                         BIT(30)
  93
  94 #define EMMC_PHY_PAD_CONTROL1                   (EMMC_PHY_REG_BASE + 0xc)
  95 #define EMMC5_1_FC_QSP_PD                       BIT(9)
  96 #define EMMC5_1_FC_QSP_PU                       BIT(25)
  97 #define EMMC5_1_FC_CMD_PD                       BIT(8)
  98 #define EMMC5_1_FC_CMD_PU                       BIT(24)
  99 #define EMMC5_1_FC_DQ_PD                        0xff
 100 #define EMMC5_1_FC_DQ_PU                        (0xff << 16)
 101
 102 #define SDHCI_RETUNE_EVT_INTSIG                 0x00001000
 103
 104 /* Hyperion only have one slot 0 */
 105 #define XENON_MMC_SLOT_ID_HYPERION              0
 106
 107 #define XENON_MMC_MAX_CLK       400000000
 108 #define XENON_MMC_3V3_UV        3300000
 109 #define XENON_MMC_1V8_UV        1800000
 110
 111 enum soc_pad_ctrl_type {
 112         SOC_PAD_SD,
 113         SOC_PAD_FIXED_1_8V,
 114 };
 115
 116 struct xenon_sdhci_plat {
 117         struct mmc_config cfg;
 118         struct mmc mmc;
 119 };
 120
 121 struct xenon_sdhci_priv {
 122         struct sdhci_host host;
 123
 124         u8 timing;
 125
 126         unsigned int clock;
 127
 128         void *pad_ctrl_reg;
 129         int pad_type;
 130
 131         struct udevice *vqmmc;
 132 };
 133
 134 static int xenon_mmc_phy_init(struct sdhci_host *host)
 135 {
 136         struct xenon_sdhci_priv *priv = host->mmc->priv;
 137         u32 clock = priv->clock;
 138         u32 time;
 139         u32 var;
 140
 141         /* Enable QSP PHASE SELECT */
 142         var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST);
 143         var |= SAMPL_INV_QSP_PHASE_SELECT;
 144         if ((priv->timing == MMC_TIMING_UHS_SDR50) ||
 145             (priv->timing == MMC_TIMING_UHS_SDR25) ||
 146             (priv->timing == MMC_TIMING_UHS_SDR12) ||
 147             (priv->timing == MMC_TIMING_SD_HS) ||
 148             (priv->timing == MMC_TIMING_LEGACY))
 149                 var |= EMMC_PHY_SLOW_MODE;
 150         sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST);
 151
 152         /* Poll for host MMC PHY clock init to be stable */
 153         /* Wait up to 10ms */
 154         time = 100;
 155         while (time--) {
 156                 var = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
 157                 if (var & SDHCI_CLOCK_INT_STABLE)
 158                         break;
 159
 160                 udelay(100);
 161         }
 162
 163         if (time <= 0) {
 164                 pr_err("Failed to enable MMC internal clock in time\n");
 165                 return -ETIMEDOUT;
 166         }
 167
 168         /* Init PHY */
 169         var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST);
 170         var |= PHY_INITIALIZAION;
 171         sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST);
 172
 173         if (clock == 0) {
 174                 /* Use the possibly slowest bus frequency value */
 175                 clock = 100000;
 176         }
 177
 178         /* Poll for host eMMC PHY init to complete */
 179         /* Wait up to 10ms */
 180         time = 100;
 181         while (time--) {
 182                 var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST);
 183                 var &= PHY_INITIALIZAION;
 184                 if (!var)
 185                         break;
 186
 187                 /* wait for host eMMC PHY init to complete */
 188                 udelay(100);
 189         }
 190
 191         if (time <= 0) {
 192                 pr_err("Failed to init MMC PHY in time\n");
 193                 return -ETIMEDOUT;
 194         }
 195
 196         return 0;
 197 }
 198
 199 #define ARMADA_3700_SOC_PAD_1_8V        0x1
 200 #define ARMADA_3700_SOC_PAD_3_3V        0x0
 201
 202 static void armada_3700_soc_pad_voltage_set(struct sdhci_host *host)
 203 {
 204         struct xenon_sdhci_priv *priv = host->mmc->priv;
 205
 206         if (priv->pad_type == SOC_PAD_FIXED_1_8V)
 207                 writel(ARMADA_3700_SOC_PAD_1_8V, priv->pad_ctrl_reg);
 208         else if (priv->pad_type == SOC_PAD_SD)
 209                 writel(ARMADA_3700_SOC_PAD_3_3V, priv->pad_ctrl_reg);
 210 }
 211
 212 static int xenon_mmc_start_signal_voltage_switch(struct sdhci_host *host)
 213 {
 214         struct xenon_sdhci_priv *priv = host->mmc->priv;
 215         u8 voltage;
 216         u32 ctrl;
 217         int ret = 0;
 218
 219         /* If there is no vqmmc regulator, return */
 220         if (!priv->vqmmc)
 221                 return 0;
 222
 223         if (priv->pad_type == SOC_PAD_FIXED_1_8V) {
 224                 /* Switch to 1.8v */
 225                 ret = regulator_set_value(priv->vqmmc,
 226                                           XENON_MMC_1V8_UV);
 227         } else if (priv->pad_type == SOC_PAD_SD) {
 228                 /* Get voltage info */
 229                 voltage = sdhci_readb(host, SDHCI_POWER_CONTROL);
 230                 voltage &= ~SDHCI_POWER_ON;
 231
 232                 if (voltage == SDHCI_POWER_330) {
 233                         /* Switch to 3.3v */
 234                         ret = regulator_set_value(priv->vqmmc,
 235                                                   XENON_MMC_3V3_UV);
 236                 } else {
 237                         /* Switch to 1.8v */
 238                         ret = regulator_set_value(priv->vqmmc,
 239                                                   XENON_MMC_1V8_UV);
 240                 }
 241         }
 242
 243         /* Set VCCQ, eMMC mode: 1.8V; SD/SDIO mode: 3.3V */
 244         ctrl = sdhci_readl(host, SDHC_SLOT_EMMC_CTRL);
 245         if (IS_SD(host->mmc))
 246                 ctrl |= EMMC_VCCQ_3_3V;
 247         else
 248                 ctrl |= EMMC_VCCQ_1_8V;
 249         sdhci_writel(host, ctrl, SDHC_SLOT_EMMC_CTRL);
 250
 251         if (ret)
 252                 printf("Signal voltage switch fail\n");
 253
 254         return ret;
 255 }
 256
 257 static void xenon_mmc_phy_set(struct sdhci_host *host)
 258 {
 259         struct xenon_sdhci_priv *priv = host->mmc->priv;
 260         u32 var;
 261
 262         /* Setup pad, set bit[30], bit[28] and bits[26:24] */
 263         var = sdhci_readl(host, EMMC_PHY_PAD_CONTROL);
 264         var |= AUTO_RECEN_CTRL | OEN_QSN | FC_QSP_RECEN |
 265                 FC_CMD_RECEN | FC_DQ_RECEN;
 266         sdhci_writel(host, var, EMMC_PHY_PAD_CONTROL);
 267
 268         /* Set CMD and DQ Pull Up */
 269         var = sdhci_readl(host, EMMC_PHY_PAD_CONTROL1);
 270         var |= (EMMC5_1_FC_CMD_PU | EMMC5_1_FC_DQ_PU);
 271         var &= ~(EMMC5_1_FC_CMD_PD | EMMC5_1_FC_DQ_PD);
 272         sdhci_writel(host, var, EMMC_PHY_PAD_CONTROL1);
 273
 274         /*
 275          * If timing belongs to high speed, set bit[17] of
 276          * EMMC_PHY_TIMING_ADJUST register
 277          */
 278         if ((priv->timing == MMC_TIMING_MMC_HS400) ||
 279             (priv->timing == MMC_TIMING_MMC_HS200) ||
 280             (priv->timing == MMC_TIMING_UHS_SDR50) ||
 281             (priv->timing == MMC_TIMING_UHS_SDR104) ||
 282             (priv->timing == MMC_TIMING_UHS_DDR50) ||
 283             (priv->timing == MMC_TIMING_UHS_SDR25) ||
 284             (priv->timing == MMC_TIMING_MMC_DDR52)) {
 285                 var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST);
 286                 var |= OUTPUT_QSN_PHASE_SELECT;
 287                 sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST);
 288         }
 289
 290         /*
 291          * When setting EMMC_PHY_FUNC_CONTROL register,
 292          * SD clock should be disabled
 293          */
 294         var = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
 295         var &= ~SDHCI_CLOCK_CARD_EN;
 296         sdhci_writew(host, var, SDHCI_CLOCK_CONTROL);
 297
 298         var = sdhci_readl(host, EMMC_PHY_FUNC_CONTROL);
 299         if (host->mmc->ddr_mode) {
 300                 var |= (DQ_DDR_MODE_MASK << DQ_DDR_MODE_SHIFT) | CMD_DDR_MODE;
 301         } else {
 302                 var &= ~((DQ_DDR_MODE_MASK << DQ_DDR_MODE_SHIFT) |
 303                          CMD_DDR_MODE);
 304         }
 305         sdhci_writel(host, var, EMMC_PHY_FUNC_CONTROL);
 306
 307         /* Enable bus clock */
 308         var = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
 309         var |= SDHCI_CLOCK_CARD_EN;
 310         sdhci_writew(host, var, SDHCI_CLOCK_CONTROL);
 311
 312         xenon_mmc_phy_init(host);
 313 }
 314
 315 /* Enable/Disable the Auto Clock Gating function of this slot */
 316 static void xenon_mmc_set_acg(struct sdhci_host *host, bool enable)
 317 {
 318         u32 var;
 319
 320         var = sdhci_readl(host, SDHC_SYS_OP_CTRL);
 321         if (enable)
 322                 var &= ~AUTO_CLKGATE_DISABLE_MASK;
 323         else
 324                 var |= AUTO_CLKGATE_DISABLE_MASK;
 325
 326         sdhci_writel(host, var, SDHC_SYS_OP_CTRL);
 327 }
 328
 329 #define SLOT_MASK(slot)         BIT(slot)
 330
 331 /* Enable specific slot */
 332 static void xenon_mmc_enable_slot(struct sdhci_host *host, u8 slot)
 333 {
 334         u32 var;
 335
 336         var = sdhci_readl(host, SDHC_SYS_OP_CTRL);
 337         var |= SLOT_MASK(slot) << SLOT_ENABLE_SHIFT;
 338         sdhci_writel(host, var, SDHC_SYS_OP_CTRL);
 339 }
 340
 341 /* Disable specific slot */
 342 static void xenon_mmc_disable_slot(struct sdhci_host *host, u8 slot)
 343 {
 344         u32 var;
 345
 346         var = sdhci_readl(host, SDHC_SYS_OP_CTRL);
 347         var &= ~(SLOT_MASK(slot) << SLOT_ENABLE_SHIFT);
 348         sdhci_writel(host, var, SDHC_SYS_OP_CTRL);
 349 }
 350
 351 /* Enable Parallel Transfer Mode */
 352 static void xenon_mmc_enable_parallel_tran(struct sdhci_host *host, u8 slot)
 353 {
 354         u32 var;
 355
 356         var = sdhci_readl(host, SDHC_SYS_EXT_OP_CTRL);
 357         var |= SLOT_MASK(slot);
 358         sdhci_writel(host, var, SDHC_SYS_EXT_OP_CTRL);
 359 }
 360
 361 static void xenon_mmc_disable_tuning(struct sdhci_host *host, u8 slot)
 362 {
 363         u32 var;
 364
 365         /* Clear the Re-Tuning Request functionality */
 366         var = sdhci_readl(host, SDHC_SLOT_RETUNING_REQ_CTRL);
 367         var &= ~RETUNING_COMPATIBLE;
 368         sdhci_writel(host, var, SDHC_SLOT_RETUNING_REQ_CTRL);
 369
 370         /* Clear the Re-tuning Event Signal Enable */
 371         var = sdhci_readl(host, SDHCI_SIGNAL_ENABLE);
 372         var &= ~SDHCI_RETUNE_EVT_INTSIG;
 373         sdhci_writel(host, var, SDHCI_SIGNAL_ENABLE);
 374 }
 375
 376 /* Mask command conflict error */
 377 static void xenon_mask_cmd_conflict_err(struct sdhci_host *host)
 378 {
 379         u32  reg;
 380
 381         reg = sdhci_readl(host, SDHC_SYS_EXT_OP_CTRL);
 382         reg |= MASK_CMD_CONFLICT_ERROR;
 383         sdhci_writel(host, reg, SDHC_SYS_EXT_OP_CTRL);
 384 }
 385
 386 /* Platform specific function for post set_ios configuration */
 387 static int xenon_sdhci_set_ios_post(struct sdhci_host *host)
 388 {
 389         struct xenon_sdhci_priv *priv = host->mmc->priv;
 390         uint speed = host->mmc->tran_speed;
 391         int pwr_18v = 0;
 392
 393         /*
 394          * Signal Voltage Switching is only applicable for Host Controllers
 395          * v3.00 and above.
 396          */
 397         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 398                 xenon_mmc_start_signal_voltage_switch(host);
 399
 400         if ((sdhci_readb(host, SDHCI_POWER_CONTROL) & ~SDHCI_POWER_ON) ==
 401             SDHCI_POWER_180)
 402                 pwr_18v = 1;
 403
 404         /* Set timing variable according to the configured speed */
 405         if (IS_SD(host->mmc)) {
 406                 /* SD/SDIO */
 407                 if (pwr_18v) {
 408                         if (host->mmc->ddr_mode)
 409                                 priv->timing = MMC_TIMING_UHS_DDR50;
 410                         else if (speed <= 25000000)
 411                                 priv->timing = MMC_TIMING_UHS_SDR25;
 412                         else
 413                                 priv->timing = MMC_TIMING_UHS_SDR50;
 414                 } else {
 415                         if (speed <= 25000000)
 416                                 priv->timing = MMC_TIMING_LEGACY;
 417                         else
 418                                 priv->timing = MMC_TIMING_SD_HS;
 419                 }
 420         } else {
 421                 /* eMMC */
 422                 if (host->mmc->ddr_mode)
 423                         priv->timing = MMC_TIMING_MMC_DDR52;
 424                 else if (speed <= 26000000)
 425                         priv->timing = MMC_TIMING_LEGACY;
 426                 else
 427                         priv->timing = MMC_TIMING_MMC_HS;
 428         }
 429
 430         /* Re-init the PHY */
 431         xenon_mmc_phy_set(host);
 432
 433         return 0;
 434 }
 435
 436 /* Install a driver specific handler for post set_ios configuration */
 437 static const struct sdhci_ops xenon_sdhci_ops = {
 438         .set_ios_post = xenon_sdhci_set_ios_post
 439 };
 440
 441 static int xenon_sdhci_probe(struct udevice *dev)
 442 {
 443         struct xenon_sdhci_plat *plat = dev_get_plat(dev);
 444         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 445         struct xenon_sdhci_priv *priv = dev_get_priv(dev);
 446         struct sdhci_host *host = dev_get_priv(dev);
 447         int ret;
 448
 449         host->mmc = &plat->mmc;
 450         host->mmc->priv = host;
 451         host->mmc->dev = dev;
 452         upriv->mmc = host->mmc;
 453
 454         /* Set quirks */
 455         host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_32BIT_DMA_ADDR;
 456
 457         /* Set default timing */
 458         priv->timing = MMC_TIMING_LEGACY;
 459
 460         /* Get the vqmmc regulator if there is */
 461         device_get_supply_regulator(dev, "vqmmc-supply", &priv->vqmmc);
 462         /* Set the initial voltage value to 3.3V if there is regulator */
 463         if (priv->vqmmc) {
 464                 ret = regulator_set_value(priv->vqmmc,
 465                                           XENON_MMC_3V3_UV);
 466                 if (ret) {
 467                         printf("Failed to set VQMMC regulator to 3.3V\n");
 468                         return ret;
 469                 }
 470         }
 471
 472         /* Disable auto clock gating during init */
 473         xenon_mmc_set_acg(host, false);
 474
 475         /* Enable slot */
 476         xenon_mmc_enable_slot(host, XENON_MMC_SLOT_ID_HYPERION);
 477
 478         /*
 479          * Set default power on SoC PHY PAD register (currently only
 480          * available on the Armada 3700)
 481          */
 482         if (priv->pad_ctrl_reg)
 483                 armada_3700_soc_pad_voltage_set(host);
 484
 485         host->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_DDR_52MHz;
 486
 487         ret = mmc_of_parse(dev, &plat->cfg);
 488         if (ret)
 489                 return ret;
 490
 491         host->ops = &xenon_sdhci_ops;
 492
 493         host->max_clk = XENON_MMC_MAX_CLK;
 494         ret = sdhci_setup_cfg(&plat->cfg, host, XENON_MMC_MAX_CLK, 0);
 495         if (ret)
 496                 return ret;
 497
 498         ret = sdhci_probe(dev);
 499         if (ret)
 500                 return ret;
 501
 502         /* Enable parallel transfer */
 503         xenon_mmc_enable_parallel_tran(host, XENON_MMC_SLOT_ID_HYPERION);
 504
 505         /* Disable tuning functionality of this slot */
 506         xenon_mmc_disable_tuning(host, XENON_MMC_SLOT_ID_HYPERION);
 507
 508         /* Enable auto clock gating after init */
 509         xenon_mmc_set_acg(host, true);
 510
 511         xenon_mask_cmd_conflict_err(host);
 512
 513         return ret;
 514 }
 515
 516 static int xenon_sdhci_remove(struct udevice *dev)
 517 {
 518         struct sdhci_host *host = dev_get_priv(dev);
 519
 520         xenon_mmc_disable_slot(host, XENON_MMC_SLOT_ID_HYPERION);
 521         return 0;
 522 }
 523
 524 static int xenon_sdhci_of_to_plat(struct udevice *dev)
 525 {
 526         struct sdhci_host *host = dev_get_priv(dev);
 527         struct xenon_sdhci_priv *priv = dev_get_priv(dev);
 528         const char *name;
 529
 530         host->name = dev->name;
 531         host->ioaddr = dev_read_addr_ptr(dev);
 532
 533         if (device_is_compatible(dev, "marvell,armada-3700-sdhci"))
 534                 priv->pad_ctrl_reg = (void *)devfdt_get_addr_index(dev, 1);
 535
 536         name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "marvell,pad-type",
 537                            NULL);
 538         if (name) {
 539                 if (0 == strncmp(name, "sd", 2)) {
 540                         priv->pad_type = SOC_PAD_SD;
 541                 } else if (0 == strncmp(name, "fixed-1-8v", 10)) {
 542                         priv->pad_type = SOC_PAD_FIXED_1_8V;
 543                 } else {
 544                         printf("Unsupported SOC PHY PAD ctrl type %s\n", name);
 545                         return -EINVAL;
 546                 }
 547         }
 548
 549         return 0;
 550 }
 551
 552 static int xenon_sdhci_bind(struct udevice *dev)
 553 {
 554         struct xenon_sdhci_plat *plat = dev_get_plat(dev);
 555
 556         return sdhci_bind(dev, &plat->mmc, &plat->cfg);
 557 }
 558
 559 static const struct udevice_id xenon_sdhci_ids[] = {
 560         { .compatible = "marvell,armada-8k-sdhci",},
 561         { .compatible = "marvell,armada-3700-sdhci",},
 562         { }
 563 };
 564
 565 U_BOOT_DRIVER(xenon_sdhci_drv) = {
 566         .name           = "xenon_sdhci",
 567         .id             = UCLASS_MMC,
 568         .of_match       = xenon_sdhci_ids,
 569         .of_to_plat = xenon_sdhci_of_to_plat,
 570         .ops            = &sdhci_ops,
 571         .bind           = xenon_sdhci_bind,
 572         .probe          = xenon_sdhci_probe,
 573         .remove         = xenon_sdhci_remove,
 574         .priv_auto      = sizeof(struct xenon_sdhci_priv),
 575         .plat_auto      = sizeof(struct xenon_sdhci_plat),
 576 };