1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
12 #include <linux/compat.h>
13 #include <linux/dma-direction.h>
15 #include <linux/sizes.h>
16 #include <power/regulator.h>
17 #include <asm/unaligned.h>
19 #include "tmio-common.h"
21 static const struct dm_mmc_ops uniphier_sd_ops = {
22 .send_cmd = tmio_sd_send_cmd,
23 .set_ios = tmio_sd_set_ios,
24 .get_cd = tmio_sd_get_cd,
27 static const struct udevice_id uniphier_sd_match[] = {
28 { .compatible = "socionext,uniphier-sd-v2.91" },
29 { .compatible = "socionext,uniphier-sd-v3.1" },
30 { .compatible = "socionext,uniphier-sd-v3.1.1" },
34 static ulong uniphier_sd_clk_get_rate(struct tmio_sd_priv *priv)
36 #if CONFIG_IS_ENABLED(CLK)
37 return clk_get_rate(&priv->clk);
38 #elif CONFIG_SPL_BUILD
45 static int uniphier_sd_probe(struct udevice *dev)
47 struct tmio_sd_priv *priv = dev_get_priv(dev);
49 priv->clk_get_rate = uniphier_sd_clk_get_rate;
50 priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2;
52 #ifndef CONFIG_SPL_BUILD
55 ret = clk_get_by_index(dev, 0, &priv->clk);
57 dev_err(dev, "failed to get host clock\n");
62 ret = clk_set_rate(&priv->clk, ULONG_MAX);
64 dev_err(dev, "failed to set rate for host clock\n");
69 ret = clk_enable(&priv->clk);
71 dev_err(dev, "failed to enable host clock\n");
76 return tmio_sd_probe(dev, 0);
79 U_BOOT_DRIVER(uniphier_mmc) = {
80 .name = "uniphier-mmc",
82 .of_match = uniphier_sd_match,
84 .probe = uniphier_sd_probe,
85 .priv_auto_alloc_size = sizeof(struct tmio_sd_priv),
86 .platdata_auto_alloc_size = sizeof(struct tmio_sd_plat),
87 .ops = &uniphier_sd_ops,