1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
13 #include <dm/device_compat.h>
14 #include <linux/compat.h>
15 #include <linux/dma-direction.h>
17 #include <linux/sizes.h>
18 #include <power/regulator.h>
19 #include <asm/unaligned.h>
21 #include "tmio-common.h"
23 static const struct dm_mmc_ops uniphier_sd_ops = {
24 .send_cmd = tmio_sd_send_cmd,
25 .set_ios = tmio_sd_set_ios,
26 .get_cd = tmio_sd_get_cd,
29 static const struct udevice_id uniphier_sd_match[] = {
30 { .compatible = "socionext,uniphier-sd-v2.91" },
31 { .compatible = "socionext,uniphier-sd-v3.1" },
32 { .compatible = "socionext,uniphier-sd-v3.1.1" },
36 static ulong uniphier_sd_clk_get_rate(struct tmio_sd_priv *priv)
38 #if CONFIG_IS_ENABLED(CLK)
39 return clk_get_rate(&priv->clk);
40 #elif CONFIG_SPL_BUILD
47 static int uniphier_sd_probe(struct udevice *dev)
49 struct tmio_sd_priv *priv = dev_get_priv(dev);
51 priv->clk_get_rate = uniphier_sd_clk_get_rate;
52 priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2;
54 #ifndef CONFIG_SPL_BUILD
57 ret = clk_get_by_index(dev, 0, &priv->clk);
59 dev_err(dev, "failed to get host clock\n");
64 ret = clk_set_rate(&priv->clk, ULONG_MAX);
66 dev_err(dev, "failed to set rate for host clock\n");
71 ret = clk_enable(&priv->clk);
73 dev_err(dev, "failed to enable host clock\n");
78 return tmio_sd_probe(dev, 0);
81 U_BOOT_DRIVER(uniphier_mmc) = {
82 .name = "uniphier-mmc",
84 .of_match = uniphier_sd_match,
86 .probe = uniphier_sd_probe,
87 .priv_auto = sizeof(struct tmio_sd_priv),
88 .plat_auto = sizeof(struct tmio_sd_plat),
89 .ops = &uniphier_sd_ops,