1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
12 #include <dm/pinctrl.h>
13 #include <linux/compat.h>
14 #include <linux/dma-direction.h>
16 #include <linux/sizes.h>
17 #include <power/regulator.h>
18 #include <asm/unaligned.h>
20 #include "tmio-common.h"
22 DECLARE_GLOBAL_DATA_PTR;
24 static u64 tmio_sd_readq(struct tmio_sd_priv *priv, unsigned int reg)
26 return readq(priv->regbase + (reg << 1));
29 static void tmio_sd_writeq(struct tmio_sd_priv *priv,
30 u64 val, unsigned int reg)
32 writeq(val, priv->regbase + (reg << 1));
35 static u16 tmio_sd_readw(struct tmio_sd_priv *priv, unsigned int reg)
37 return readw(priv->regbase + (reg >> 1));
40 static void tmio_sd_writew(struct tmio_sd_priv *priv,
41 u16 val, unsigned int reg)
43 writew(val, priv->regbase + (reg >> 1));
46 u32 tmio_sd_readl(struct tmio_sd_priv *priv, unsigned int reg)
50 if (priv->caps & TMIO_SD_CAP_64BIT)
51 return readl(priv->regbase + (reg << 1));
52 else if (priv->caps & TMIO_SD_CAP_16BIT) {
53 val = readw(priv->regbase + (reg >> 1)) & 0xffff;
54 if ((reg == TMIO_SD_RSP10) || (reg == TMIO_SD_RSP32) ||
55 (reg == TMIO_SD_RSP54) || (reg == TMIO_SD_RSP76)) {
56 val |= readw(priv->regbase + (reg >> 1) + 2) << 16;
60 return readl(priv->regbase + reg);
63 void tmio_sd_writel(struct tmio_sd_priv *priv,
64 u32 val, unsigned int reg)
66 if (priv->caps & TMIO_SD_CAP_64BIT)
67 writel(val, priv->regbase + (reg << 1));
68 else if (priv->caps & TMIO_SD_CAP_16BIT) {
69 writew(val & 0xffff, priv->regbase + (reg >> 1));
70 if (reg == TMIO_SD_INFO1 || reg == TMIO_SD_INFO1_MASK ||
71 reg == TMIO_SD_INFO2 || reg == TMIO_SD_INFO2_MASK ||
73 writew(val >> 16, priv->regbase + (reg >> 1) + 2);
75 writel(val, priv->regbase + reg);
78 static dma_addr_t __dma_map_single(void *ptr, size_t size,
79 enum dma_data_direction dir)
81 unsigned long addr = (unsigned long)ptr;
83 if (dir == DMA_FROM_DEVICE)
84 invalidate_dcache_range(addr, addr + size);
86 flush_dcache_range(addr, addr + size);
91 static void __dma_unmap_single(dma_addr_t addr, size_t size,
92 enum dma_data_direction dir)
94 if (dir != DMA_TO_DEVICE)
95 invalidate_dcache_range(addr, addr + size);
98 static int tmio_sd_check_error(struct udevice *dev)
100 struct tmio_sd_priv *priv = dev_get_priv(dev);
101 u32 info2 = tmio_sd_readl(priv, TMIO_SD_INFO2);
103 if (info2 & TMIO_SD_INFO2_ERR_RTO) {
105 * TIMEOUT must be returned for unsupported command. Do not
106 * display error log since this might be a part of sequence to
107 * distinguish between SD and MMC.
112 if (info2 & TMIO_SD_INFO2_ERR_TO) {
113 dev_err(dev, "timeout error\n");
117 if (info2 & (TMIO_SD_INFO2_ERR_END | TMIO_SD_INFO2_ERR_CRC |
118 TMIO_SD_INFO2_ERR_IDX)) {
119 dev_err(dev, "communication out of sync\n");
123 if (info2 & (TMIO_SD_INFO2_ERR_ILA | TMIO_SD_INFO2_ERR_ILR |
124 TMIO_SD_INFO2_ERR_ILW)) {
125 dev_err(dev, "illegal access\n");
132 static int tmio_sd_wait_for_irq(struct udevice *dev, unsigned int reg,
135 struct tmio_sd_priv *priv = dev_get_priv(dev);
139 while (!(tmio_sd_readl(priv, reg) & flag)) {
141 dev_err(dev, "timeout\n");
145 ret = tmio_sd_check_error(dev);
155 #define tmio_pio_read_fifo(__width, __suffix) \
156 static void tmio_pio_read_fifo_##__width(struct tmio_sd_priv *priv, \
157 char *pbuf, uint blksz) \
159 u##__width *buf = (u##__width *)pbuf; \
162 if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \
163 for (i = 0; i < blksz / ((__width) / 8); i++) { \
164 *buf++ = tmio_sd_read##__suffix(priv, \
168 for (i = 0; i < blksz / ((__width) / 8); i++) { \
170 data = tmio_sd_read##__suffix(priv, \
172 put_unaligned(data, buf++); \
177 tmio_pio_read_fifo(64, q)
178 tmio_pio_read_fifo(32, l)
179 tmio_pio_read_fifo(16, w)
181 static int tmio_sd_pio_read_one_block(struct udevice *dev, char *pbuf,
184 struct tmio_sd_priv *priv = dev_get_priv(dev);
187 /* wait until the buffer is filled with data */
188 ret = tmio_sd_wait_for_irq(dev, TMIO_SD_INFO2,
194 * Clear the status flag _before_ read the buffer out because
195 * TMIO_SD_INFO2_BRE is edge-triggered, not level-triggered.
197 tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
199 if (priv->caps & TMIO_SD_CAP_64BIT)
200 tmio_pio_read_fifo_64(priv, pbuf, blocksize);
201 else if (priv->caps & TMIO_SD_CAP_16BIT)
202 tmio_pio_read_fifo_16(priv, pbuf, blocksize);
204 tmio_pio_read_fifo_32(priv, pbuf, blocksize);
209 #define tmio_pio_write_fifo(__width, __suffix) \
210 static void tmio_pio_write_fifo_##__width(struct tmio_sd_priv *priv, \
211 const char *pbuf, uint blksz)\
213 const u##__width *buf = (const u##__width *)pbuf; \
216 if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \
217 for (i = 0; i < blksz / ((__width) / 8); i++) { \
218 tmio_sd_write##__suffix(priv, *buf++, \
222 for (i = 0; i < blksz / ((__width) / 8); i++) { \
223 u##__width data = get_unaligned(buf++); \
224 tmio_sd_write##__suffix(priv, data, \
230 tmio_pio_write_fifo(64, q)
231 tmio_pio_write_fifo(32, l)
232 tmio_pio_write_fifo(16, w)
234 static int tmio_sd_pio_write_one_block(struct udevice *dev,
235 const char *pbuf, uint blocksize)
237 struct tmio_sd_priv *priv = dev_get_priv(dev);
240 /* wait until the buffer becomes empty */
241 ret = tmio_sd_wait_for_irq(dev, TMIO_SD_INFO2,
246 tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
248 if (priv->caps & TMIO_SD_CAP_64BIT)
249 tmio_pio_write_fifo_64(priv, pbuf, blocksize);
250 else if (priv->caps & TMIO_SD_CAP_16BIT)
251 tmio_pio_write_fifo_16(priv, pbuf, blocksize);
253 tmio_pio_write_fifo_32(priv, pbuf, blocksize);
258 static int tmio_sd_pio_xfer(struct udevice *dev, struct mmc_data *data)
260 const char *src = data->src;
261 char *dest = data->dest;
264 for (i = 0; i < data->blocks; i++) {
265 if (data->flags & MMC_DATA_READ)
266 ret = tmio_sd_pio_read_one_block(dev, dest,
269 ret = tmio_sd_pio_write_one_block(dev, src,
274 if (data->flags & MMC_DATA_READ)
275 dest += data->blocksize;
277 src += data->blocksize;
283 static void tmio_sd_dma_start(struct tmio_sd_priv *priv,
288 tmio_sd_writel(priv, 0, TMIO_SD_DMA_INFO1);
289 tmio_sd_writel(priv, 0, TMIO_SD_DMA_INFO2);
292 tmp = tmio_sd_readl(priv, TMIO_SD_EXTMODE);
293 tmp |= TMIO_SD_EXTMODE_DMA_EN;
294 tmio_sd_writel(priv, tmp, TMIO_SD_EXTMODE);
296 tmio_sd_writel(priv, dma_addr & U32_MAX, TMIO_SD_DMA_ADDR_L);
298 /* suppress the warning "right shift count >= width of type" */
299 dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr));
301 tmio_sd_writel(priv, dma_addr & U32_MAX, TMIO_SD_DMA_ADDR_H);
303 tmio_sd_writel(priv, TMIO_SD_DMA_CTL_START, TMIO_SD_DMA_CTL);
306 static int tmio_sd_dma_wait_for_irq(struct udevice *dev, u32 flag,
309 struct tmio_sd_priv *priv = dev_get_priv(dev);
310 long wait = 1000000 + 10 * blocks;
312 while (!(tmio_sd_readl(priv, TMIO_SD_DMA_INFO1) & flag)) {
314 dev_err(dev, "timeout during DMA\n");
321 if (tmio_sd_readl(priv, TMIO_SD_DMA_INFO2)) {
322 dev_err(dev, "error during DMA\n");
329 static int tmio_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
331 struct tmio_sd_priv *priv = dev_get_priv(dev);
332 size_t len = data->blocks * data->blocksize;
334 enum dma_data_direction dir;
339 tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE);
341 if (data->flags & MMC_DATA_READ) {
343 dir = DMA_FROM_DEVICE;
345 * The DMA READ completion flag position differs on Socionext
346 * and Renesas SoCs. It is bit 20 on Socionext SoCs and using
347 * bit 17 is a hardware bug and forbidden. It is bit 17 on
348 * Renesas SoCs and bit 20 does not work on them.
350 poll_flag = (priv->caps & TMIO_SD_CAP_RCAR) ?
351 TMIO_SD_DMA_INFO1_END_RD :
352 TMIO_SD_DMA_INFO1_END_RD2;
353 tmp |= TMIO_SD_DMA_MODE_DIR_RD;
355 buf = (void *)data->src;
357 poll_flag = TMIO_SD_DMA_INFO1_END_WR;
358 tmp &= ~TMIO_SD_DMA_MODE_DIR_RD;
361 tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE);
363 dma_addr = __dma_map_single(buf, len, dir);
365 tmio_sd_dma_start(priv, dma_addr);
367 ret = tmio_sd_dma_wait_for_irq(dev, poll_flag, data->blocks);
369 __dma_unmap_single(dma_addr, len, dir);
374 /* check if the address is DMA'able */
375 static bool tmio_sd_addr_is_dmaable(const char *src)
377 uintptr_t addr = (uintptr_t)src;
379 if (!IS_ALIGNED(addr, TMIO_SD_DMA_MINALIGN))
382 #if defined(CONFIG_RCAR_GEN3)
383 /* Gen3 DMA has 32bit limit */
388 #if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \
389 defined(CONFIG_SPL_BUILD)
391 * For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways
392 * of L2, which is unreachable from the DMA engine.
394 if (addr < CONFIG_SPL_STACK)
401 int tmio_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
402 struct mmc_data *data)
404 struct tmio_sd_priv *priv = dev_get_priv(dev);
408 if (tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_CBSY) {
409 dev_err(dev, "command busy\n");
413 /* clear all status flags */
414 tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
415 tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
417 /* disable DMA once */
418 tmp = tmio_sd_readl(priv, TMIO_SD_EXTMODE);
419 tmp &= ~TMIO_SD_EXTMODE_DMA_EN;
420 tmio_sd_writel(priv, tmp, TMIO_SD_EXTMODE);
422 tmio_sd_writel(priv, cmd->cmdarg, TMIO_SD_ARG);
427 tmio_sd_writel(priv, data->blocksize, TMIO_SD_SIZE);
428 tmio_sd_writel(priv, data->blocks, TMIO_SD_SECCNT);
430 /* Do not send CMD12 automatically */
431 tmp |= TMIO_SD_CMD_NOSTOP | TMIO_SD_CMD_DATA;
433 if (data->blocks > 1)
434 tmp |= TMIO_SD_CMD_MULTI;
436 if (data->flags & MMC_DATA_READ)
437 tmp |= TMIO_SD_CMD_RD;
441 * Do not use the response type auto-detection on this hardware.
442 * CMD8, for example, has different response types on SD and eMMC,
443 * while this controller always assumes the response type for SD.
444 * Set the response type manually.
446 switch (cmd->resp_type) {
448 tmp |= TMIO_SD_CMD_RSP_NONE;
451 tmp |= TMIO_SD_CMD_RSP_R1;
454 tmp |= TMIO_SD_CMD_RSP_R1B;
457 tmp |= TMIO_SD_CMD_RSP_R2;
460 tmp |= TMIO_SD_CMD_RSP_R3;
463 dev_err(dev, "unknown response type\n");
467 dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n",
468 cmd->cmdidx, tmp, cmd->cmdarg);
469 tmio_sd_writel(priv, tmp, TMIO_SD_CMD);
471 ret = tmio_sd_wait_for_irq(dev, TMIO_SD_INFO1,
476 if (cmd->resp_type & MMC_RSP_136) {
477 u32 rsp_127_104 = tmio_sd_readl(priv, TMIO_SD_RSP76);
478 u32 rsp_103_72 = tmio_sd_readl(priv, TMIO_SD_RSP54);
479 u32 rsp_71_40 = tmio_sd_readl(priv, TMIO_SD_RSP32);
480 u32 rsp_39_8 = tmio_sd_readl(priv, TMIO_SD_RSP10);
482 cmd->response[0] = ((rsp_127_104 & 0x00ffffff) << 8) |
483 ((rsp_103_72 & 0xff000000) >> 24);
484 cmd->response[1] = ((rsp_103_72 & 0x00ffffff) << 8) |
485 ((rsp_71_40 & 0xff000000) >> 24);
486 cmd->response[2] = ((rsp_71_40 & 0x00ffffff) << 8) |
487 ((rsp_39_8 & 0xff000000) >> 24);
488 cmd->response[3] = (rsp_39_8 & 0xffffff) << 8;
491 cmd->response[0] = tmio_sd_readl(priv, TMIO_SD_RSP10);
495 /* use DMA if the HW supports it and the buffer is aligned */
496 if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL &&
497 tmio_sd_addr_is_dmaable(data->src))
498 ret = tmio_sd_dma_xfer(dev, data);
500 ret = tmio_sd_pio_xfer(dev, data);
502 ret = tmio_sd_wait_for_irq(dev, TMIO_SD_INFO1,
508 tmio_sd_wait_for_irq(dev, TMIO_SD_INFO2, TMIO_SD_INFO2_SCLKDIVEN);
513 static int tmio_sd_set_bus_width(struct tmio_sd_priv *priv,
518 switch (mmc->bus_width) {
521 val = TMIO_SD_OPTION_WIDTH_1;
524 val = TMIO_SD_OPTION_WIDTH_4;
527 val = TMIO_SD_OPTION_WIDTH_8;
533 tmp = tmio_sd_readl(priv, TMIO_SD_OPTION);
534 tmp &= ~TMIO_SD_OPTION_WIDTH_MASK;
536 tmio_sd_writel(priv, tmp, TMIO_SD_OPTION);
541 static void tmio_sd_set_ddr_mode(struct tmio_sd_priv *priv,
546 tmp = tmio_sd_readl(priv, TMIO_SD_IF_MODE);
548 tmp |= TMIO_SD_IF_MODE_DDR;
550 tmp &= ~TMIO_SD_IF_MODE_DDR;
551 tmio_sd_writel(priv, tmp, TMIO_SD_IF_MODE);
554 static void tmio_sd_set_clk_rate(struct tmio_sd_priv *priv,
557 unsigned int divisor;
563 divisor = DIV_ROUND_UP(priv->mclk, mmc->clock);
566 val = (priv->caps & TMIO_SD_CAP_RCAR) ?
567 TMIO_SD_CLKCTL_RCAR_DIV1 : TMIO_SD_CLKCTL_DIV1;
568 else if (divisor <= 2)
569 val = TMIO_SD_CLKCTL_DIV2;
570 else if (divisor <= 4)
571 val = TMIO_SD_CLKCTL_DIV4;
572 else if (divisor <= 8)
573 val = TMIO_SD_CLKCTL_DIV8;
574 else if (divisor <= 16)
575 val = TMIO_SD_CLKCTL_DIV16;
576 else if (divisor <= 32)
577 val = TMIO_SD_CLKCTL_DIV32;
578 else if (divisor <= 64)
579 val = TMIO_SD_CLKCTL_DIV64;
580 else if (divisor <= 128)
581 val = TMIO_SD_CLKCTL_DIV128;
582 else if (divisor <= 256)
583 val = TMIO_SD_CLKCTL_DIV256;
584 else if (divisor <= 512 || !(priv->caps & TMIO_SD_CAP_DIV1024))
585 val = TMIO_SD_CLKCTL_DIV512;
587 val = TMIO_SD_CLKCTL_DIV1024;
589 tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
590 if (tmp & TMIO_SD_CLKCTL_SCLKEN &&
591 (tmp & TMIO_SD_CLKCTL_DIV_MASK) == val)
594 /* stop the clock before changing its rate to avoid a glitch signal */
595 tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
596 tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
598 tmp &= ~TMIO_SD_CLKCTL_DIV_MASK;
599 tmp |= val | TMIO_SD_CLKCTL_OFFEN;
600 tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
602 tmp |= TMIO_SD_CLKCTL_SCLKEN;
603 tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
608 static void tmio_sd_set_pins(struct udevice *dev)
610 __maybe_unused struct mmc *mmc = mmc_get_mmc_dev(dev);
612 #ifdef CONFIG_DM_REGULATOR
613 struct tmio_sd_priv *priv = dev_get_priv(dev);
615 if (priv->vqmmc_dev) {
616 if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
617 regulator_set_value(priv->vqmmc_dev, 1800000);
619 regulator_set_value(priv->vqmmc_dev, 3300000);
620 regulator_set_enable(priv->vqmmc_dev, true);
624 #ifdef CONFIG_PINCTRL
625 switch (mmc->selected_mode) {
632 pinctrl_select_state(dev, "default");
640 pinctrl_select_state(dev, "state_uhs");
648 int tmio_sd_set_ios(struct udevice *dev)
650 struct tmio_sd_priv *priv = dev_get_priv(dev);
651 struct mmc *mmc = mmc_get_mmc_dev(dev);
654 dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n",
655 mmc->clock, mmc->ddr_mode, mmc->bus_width);
657 ret = tmio_sd_set_bus_width(priv, mmc);
660 tmio_sd_set_ddr_mode(priv, mmc);
661 tmio_sd_set_clk_rate(priv, mmc);
662 tmio_sd_set_pins(dev);
667 int tmio_sd_get_cd(struct udevice *dev)
669 struct tmio_sd_priv *priv = dev_get_priv(dev);
671 if (priv->caps & TMIO_SD_CAP_NONREMOVABLE)
674 return !!(tmio_sd_readl(priv, TMIO_SD_INFO1) &
678 static void tmio_sd_host_init(struct tmio_sd_priv *priv)
682 /* soft reset of the host */
683 tmp = tmio_sd_readl(priv, TMIO_SD_SOFT_RST);
684 tmp &= ~TMIO_SD_SOFT_RST_RSTX;
685 tmio_sd_writel(priv, tmp, TMIO_SD_SOFT_RST);
686 tmp |= TMIO_SD_SOFT_RST_RSTX;
687 tmio_sd_writel(priv, tmp, TMIO_SD_SOFT_RST);
689 /* FIXME: implement eMMC hw_reset */
691 tmio_sd_writel(priv, TMIO_SD_STOP_SEC, TMIO_SD_STOP);
694 * Connected to 32bit AXI.
695 * This register dropped backward compatibility at version 0x10.
696 * Write an appropriate value depending on the IP version.
698 if (priv->version >= 0x10)
699 tmio_sd_writel(priv, 0x101, TMIO_SD_HOST_MODE);
701 tmio_sd_writel(priv, 0x0, TMIO_SD_HOST_MODE);
703 if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL) {
704 tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE);
705 tmp |= TMIO_SD_DMA_MODE_ADDR_INC;
706 tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE);
710 int tmio_sd_bind(struct udevice *dev)
712 struct tmio_sd_plat *plat = dev_get_platdata(dev);
714 return mmc_bind(dev, &plat->mmc, &plat->cfg);
717 int tmio_sd_probe(struct udevice *dev, u32 quirks)
719 struct tmio_sd_plat *plat = dev_get_platdata(dev);
720 struct tmio_sd_priv *priv = dev_get_priv(dev);
721 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
725 base = devfdt_get_addr(dev);
726 if (base == FDT_ADDR_T_NONE)
729 priv->regbase = devm_ioremap(dev, base, SZ_2K);
733 #ifdef CONFIG_DM_REGULATOR
734 device_get_supply_regulator(dev, "vqmmc-supply", &priv->vqmmc_dev);
737 ret = mmc_of_parse(dev, &plat->cfg);
739 dev_err(dev, "failed to parse host caps\n");
743 plat->cfg.name = dev->name;
744 plat->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
749 priv->version = tmio_sd_readl(priv, TMIO_SD_VERSION) &
751 dev_dbg(dev, "version %x\n", priv->version);
752 if (priv->version >= 0x10) {
753 priv->caps |= TMIO_SD_CAP_DMA_INTERNAL;
754 priv->caps |= TMIO_SD_CAP_DIV1024;
757 if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable",
759 priv->caps |= TMIO_SD_CAP_NONREMOVABLE;
761 tmio_sd_host_init(priv);
763 plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
764 plat->cfg.f_min = priv->mclk /
765 (priv->caps & TMIO_SD_CAP_DIV1024 ? 1024 : 512);
766 plat->cfg.f_max = priv->mclk;
767 plat->cfg.b_max = U32_MAX; /* max value of TMIO_SD_SECCNT */
769 upriv->mmc = &plat->mmc;