2 * Copyright (C) 2016 Socionext Inc.
3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5 * SPDX-License-Identifier: GPL-2.0+
13 #include <dm/pinctrl.h>
14 #include <linux/compat.h>
15 #include <linux/dma-direction.h>
17 #include <linux/sizes.h>
18 #include <power/regulator.h>
19 #include <asm/unaligned.h>
21 #include "tmio-common.h"
23 DECLARE_GLOBAL_DATA_PTR;
25 static u64 tmio_sd_readq(struct tmio_sd_priv *priv, unsigned int reg)
27 return readq(priv->regbase + (reg << 1));
30 static void tmio_sd_writeq(struct tmio_sd_priv *priv,
31 u64 val, unsigned int reg)
33 writeq(val, priv->regbase + (reg << 1));
36 static u16 tmio_sd_readw(struct tmio_sd_priv *priv, unsigned int reg)
38 return readw(priv->regbase + (reg >> 1));
41 static void tmio_sd_writew(struct tmio_sd_priv *priv,
42 u16 val, unsigned int reg)
44 writew(val, priv->regbase + (reg >> 1));
47 u32 tmio_sd_readl(struct tmio_sd_priv *priv, unsigned int reg)
51 if (priv->caps & TMIO_SD_CAP_64BIT)
52 return readl(priv->regbase + (reg << 1));
53 else if (priv->caps & TMIO_SD_CAP_16BIT) {
54 val = readw(priv->regbase + (reg >> 1)) & 0xffff;
55 if ((reg == TMIO_SD_RSP10) || (reg == TMIO_SD_RSP32) ||
56 (reg == TMIO_SD_RSP54) || (reg == TMIO_SD_RSP76)) {
57 val |= readw(priv->regbase + (reg >> 1) + 2) << 16;
61 return readl(priv->regbase + reg);
64 void tmio_sd_writel(struct tmio_sd_priv *priv,
65 u32 val, unsigned int reg)
67 if (priv->caps & TMIO_SD_CAP_64BIT)
68 writel(val, priv->regbase + (reg << 1));
69 else if (priv->caps & TMIO_SD_CAP_16BIT) {
70 writew(val & 0xffff, priv->regbase + (reg >> 1));
71 if (reg == TMIO_SD_INFO1 || reg == TMIO_SD_INFO1_MASK ||
72 reg == TMIO_SD_INFO2 || reg == TMIO_SD_INFO2_MASK ||
74 writew(val >> 16, priv->regbase + (reg >> 1) + 2);
76 writel(val, priv->regbase + reg);
79 static dma_addr_t __dma_map_single(void *ptr, size_t size,
80 enum dma_data_direction dir)
82 unsigned long addr = (unsigned long)ptr;
84 if (dir == DMA_FROM_DEVICE)
85 invalidate_dcache_range(addr, addr + size);
87 flush_dcache_range(addr, addr + size);
92 static void __dma_unmap_single(dma_addr_t addr, size_t size,
93 enum dma_data_direction dir)
95 if (dir != DMA_TO_DEVICE)
96 invalidate_dcache_range(addr, addr + size);
99 static int tmio_sd_check_error(struct udevice *dev)
101 struct tmio_sd_priv *priv = dev_get_priv(dev);
102 u32 info2 = tmio_sd_readl(priv, TMIO_SD_INFO2);
104 if (info2 & TMIO_SD_INFO2_ERR_RTO) {
106 * TIMEOUT must be returned for unsupported command. Do not
107 * display error log since this might be a part of sequence to
108 * distinguish between SD and MMC.
113 if (info2 & TMIO_SD_INFO2_ERR_TO) {
114 dev_err(dev, "timeout error\n");
118 if (info2 & (TMIO_SD_INFO2_ERR_END | TMIO_SD_INFO2_ERR_CRC |
119 TMIO_SD_INFO2_ERR_IDX)) {
120 dev_err(dev, "communication out of sync\n");
124 if (info2 & (TMIO_SD_INFO2_ERR_ILA | TMIO_SD_INFO2_ERR_ILR |
125 TMIO_SD_INFO2_ERR_ILW)) {
126 dev_err(dev, "illegal access\n");
133 static int tmio_sd_wait_for_irq(struct udevice *dev, unsigned int reg,
136 struct tmio_sd_priv *priv = dev_get_priv(dev);
140 while (!(tmio_sd_readl(priv, reg) & flag)) {
142 dev_err(dev, "timeout\n");
146 ret = tmio_sd_check_error(dev);
156 #define tmio_pio_read_fifo(__width, __suffix) \
157 static void tmio_pio_read_fifo_##__width(struct tmio_sd_priv *priv, \
158 char *pbuf, uint blksz) \
160 u##__width *buf = (u##__width *)pbuf; \
163 if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \
164 for (i = 0; i < blksz / ((__width) / 8); i++) { \
165 *buf++ = tmio_sd_read##__suffix(priv, \
169 for (i = 0; i < blksz / ((__width) / 8); i++) { \
171 data = tmio_sd_read##__suffix(priv, \
173 put_unaligned(data, buf++); \
178 tmio_pio_read_fifo(64, q)
179 tmio_pio_read_fifo(32, l)
180 tmio_pio_read_fifo(16, w)
182 static int tmio_sd_pio_read_one_block(struct udevice *dev, char *pbuf,
185 struct tmio_sd_priv *priv = dev_get_priv(dev);
188 /* wait until the buffer is filled with data */
189 ret = tmio_sd_wait_for_irq(dev, TMIO_SD_INFO2,
195 * Clear the status flag _before_ read the buffer out because
196 * TMIO_SD_INFO2_BRE is edge-triggered, not level-triggered.
198 tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
200 if (priv->caps & TMIO_SD_CAP_64BIT)
201 tmio_pio_read_fifo_64(priv, pbuf, blocksize);
202 else if (priv->caps & TMIO_SD_CAP_16BIT)
203 tmio_pio_read_fifo_16(priv, pbuf, blocksize);
205 tmio_pio_read_fifo_32(priv, pbuf, blocksize);
210 #define tmio_pio_write_fifo(__width, __suffix) \
211 static void tmio_pio_write_fifo_##__width(struct tmio_sd_priv *priv, \
212 const char *pbuf, uint blksz)\
214 const u##__width *buf = (const u##__width *)pbuf; \
217 if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \
218 for (i = 0; i < blksz / ((__width) / 8); i++) { \
219 tmio_sd_write##__suffix(priv, *buf++, \
223 for (i = 0; i < blksz / ((__width) / 8); i++) { \
224 u##__width data = get_unaligned(buf++); \
225 tmio_sd_write##__suffix(priv, data, \
231 tmio_pio_write_fifo(64, q)
232 tmio_pio_write_fifo(32, l)
233 tmio_pio_write_fifo(16, w)
235 static int tmio_sd_pio_write_one_block(struct udevice *dev,
236 const char *pbuf, uint blocksize)
238 struct tmio_sd_priv *priv = dev_get_priv(dev);
241 /* wait until the buffer becomes empty */
242 ret = tmio_sd_wait_for_irq(dev, TMIO_SD_INFO2,
247 tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
249 if (priv->caps & TMIO_SD_CAP_64BIT)
250 tmio_pio_write_fifo_64(priv, pbuf, blocksize);
251 else if (priv->caps & TMIO_SD_CAP_16BIT)
252 tmio_pio_write_fifo_16(priv, pbuf, blocksize);
254 tmio_pio_write_fifo_32(priv, pbuf, blocksize);
259 static int tmio_sd_pio_xfer(struct udevice *dev, struct mmc_data *data)
261 const char *src = data->src;
262 char *dest = data->dest;
265 for (i = 0; i < data->blocks; i++) {
266 if (data->flags & MMC_DATA_READ)
267 ret = tmio_sd_pio_read_one_block(dev, dest,
270 ret = tmio_sd_pio_write_one_block(dev, src,
275 if (data->flags & MMC_DATA_READ)
276 dest += data->blocksize;
278 src += data->blocksize;
284 static void tmio_sd_dma_start(struct tmio_sd_priv *priv,
289 tmio_sd_writel(priv, 0, TMIO_SD_DMA_INFO1);
290 tmio_sd_writel(priv, 0, TMIO_SD_DMA_INFO2);
293 tmp = tmio_sd_readl(priv, TMIO_SD_EXTMODE);
294 tmp |= TMIO_SD_EXTMODE_DMA_EN;
295 tmio_sd_writel(priv, tmp, TMIO_SD_EXTMODE);
297 tmio_sd_writel(priv, dma_addr & U32_MAX, TMIO_SD_DMA_ADDR_L);
299 /* suppress the warning "right shift count >= width of type" */
300 dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr));
302 tmio_sd_writel(priv, dma_addr & U32_MAX, TMIO_SD_DMA_ADDR_H);
304 tmio_sd_writel(priv, TMIO_SD_DMA_CTL_START, TMIO_SD_DMA_CTL);
307 static int tmio_sd_dma_wait_for_irq(struct udevice *dev, u32 flag,
310 struct tmio_sd_priv *priv = dev_get_priv(dev);
311 long wait = 1000000 + 10 * blocks;
313 while (!(tmio_sd_readl(priv, TMIO_SD_DMA_INFO1) & flag)) {
315 dev_err(dev, "timeout during DMA\n");
322 if (tmio_sd_readl(priv, TMIO_SD_DMA_INFO2)) {
323 dev_err(dev, "error during DMA\n");
330 static int tmio_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
332 struct tmio_sd_priv *priv = dev_get_priv(dev);
333 size_t len = data->blocks * data->blocksize;
335 enum dma_data_direction dir;
340 tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE);
342 if (data->flags & MMC_DATA_READ) {
344 dir = DMA_FROM_DEVICE;
346 * The DMA READ completion flag position differs on Socionext
347 * and Renesas SoCs. It is bit 20 on Socionext SoCs and using
348 * bit 17 is a hardware bug and forbidden. It is bit 17 on
349 * Renesas SoCs and bit 20 does not work on them.
351 poll_flag = (priv->caps & TMIO_SD_CAP_RCAR) ?
352 TMIO_SD_DMA_INFO1_END_RD :
353 TMIO_SD_DMA_INFO1_END_RD2;
354 tmp |= TMIO_SD_DMA_MODE_DIR_RD;
356 buf = (void *)data->src;
358 poll_flag = TMIO_SD_DMA_INFO1_END_WR;
359 tmp &= ~TMIO_SD_DMA_MODE_DIR_RD;
362 tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE);
364 dma_addr = __dma_map_single(buf, len, dir);
366 tmio_sd_dma_start(priv, dma_addr);
368 ret = tmio_sd_dma_wait_for_irq(dev, poll_flag, data->blocks);
370 __dma_unmap_single(dma_addr, len, dir);
375 /* check if the address is DMA'able */
376 static bool tmio_sd_addr_is_dmaable(unsigned long addr)
378 if (!IS_ALIGNED(addr, TMIO_SD_DMA_MINALIGN))
381 #if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \
382 defined(CONFIG_SPL_BUILD)
384 * For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways
385 * of L2, which is unreachable from the DMA engine.
387 if (addr < CONFIG_SPL_STACK)
394 int tmio_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
395 struct mmc_data *data)
397 struct tmio_sd_priv *priv = dev_get_priv(dev);
401 if (tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_CBSY) {
402 dev_err(dev, "command busy\n");
406 /* clear all status flags */
407 tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
408 tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
410 /* disable DMA once */
411 tmp = tmio_sd_readl(priv, TMIO_SD_EXTMODE);
412 tmp &= ~TMIO_SD_EXTMODE_DMA_EN;
413 tmio_sd_writel(priv, tmp, TMIO_SD_EXTMODE);
415 tmio_sd_writel(priv, cmd->cmdarg, TMIO_SD_ARG);
420 tmio_sd_writel(priv, data->blocksize, TMIO_SD_SIZE);
421 tmio_sd_writel(priv, data->blocks, TMIO_SD_SECCNT);
423 /* Do not send CMD12 automatically */
424 tmp |= TMIO_SD_CMD_NOSTOP | TMIO_SD_CMD_DATA;
426 if (data->blocks > 1)
427 tmp |= TMIO_SD_CMD_MULTI;
429 if (data->flags & MMC_DATA_READ)
430 tmp |= TMIO_SD_CMD_RD;
434 * Do not use the response type auto-detection on this hardware.
435 * CMD8, for example, has different response types on SD and eMMC,
436 * while this controller always assumes the response type for SD.
437 * Set the response type manually.
439 switch (cmd->resp_type) {
441 tmp |= TMIO_SD_CMD_RSP_NONE;
444 tmp |= TMIO_SD_CMD_RSP_R1;
447 tmp |= TMIO_SD_CMD_RSP_R1B;
450 tmp |= TMIO_SD_CMD_RSP_R2;
453 tmp |= TMIO_SD_CMD_RSP_R3;
456 dev_err(dev, "unknown response type\n");
460 dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n",
461 cmd->cmdidx, tmp, cmd->cmdarg);
462 tmio_sd_writel(priv, tmp, TMIO_SD_CMD);
464 ret = tmio_sd_wait_for_irq(dev, TMIO_SD_INFO1,
469 if (cmd->resp_type & MMC_RSP_136) {
470 u32 rsp_127_104 = tmio_sd_readl(priv, TMIO_SD_RSP76);
471 u32 rsp_103_72 = tmio_sd_readl(priv, TMIO_SD_RSP54);
472 u32 rsp_71_40 = tmio_sd_readl(priv, TMIO_SD_RSP32);
473 u32 rsp_39_8 = tmio_sd_readl(priv, TMIO_SD_RSP10);
475 cmd->response[0] = ((rsp_127_104 & 0x00ffffff) << 8) |
476 ((rsp_103_72 & 0xff000000) >> 24);
477 cmd->response[1] = ((rsp_103_72 & 0x00ffffff) << 8) |
478 ((rsp_71_40 & 0xff000000) >> 24);
479 cmd->response[2] = ((rsp_71_40 & 0x00ffffff) << 8) |
480 ((rsp_39_8 & 0xff000000) >> 24);
481 cmd->response[3] = (rsp_39_8 & 0xffffff) << 8;
484 cmd->response[0] = tmio_sd_readl(priv, TMIO_SD_RSP10);
488 /* use DMA if the HW supports it and the buffer is aligned */
489 if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL &&
490 tmio_sd_addr_is_dmaable((long)data->src))
491 ret = tmio_sd_dma_xfer(dev, data);
493 ret = tmio_sd_pio_xfer(dev, data);
495 ret = tmio_sd_wait_for_irq(dev, TMIO_SD_INFO1,
501 tmio_sd_wait_for_irq(dev, TMIO_SD_INFO2, TMIO_SD_INFO2_SCLKDIVEN);
506 static int tmio_sd_set_bus_width(struct tmio_sd_priv *priv,
511 switch (mmc->bus_width) {
514 val = TMIO_SD_OPTION_WIDTH_1;
517 val = TMIO_SD_OPTION_WIDTH_4;
520 val = TMIO_SD_OPTION_WIDTH_8;
526 tmp = tmio_sd_readl(priv, TMIO_SD_OPTION);
527 tmp &= ~TMIO_SD_OPTION_WIDTH_MASK;
529 tmio_sd_writel(priv, tmp, TMIO_SD_OPTION);
534 static void tmio_sd_set_ddr_mode(struct tmio_sd_priv *priv,
539 tmp = tmio_sd_readl(priv, TMIO_SD_IF_MODE);
541 tmp |= TMIO_SD_IF_MODE_DDR;
543 tmp &= ~TMIO_SD_IF_MODE_DDR;
544 tmio_sd_writel(priv, tmp, TMIO_SD_IF_MODE);
547 static void tmio_sd_set_clk_rate(struct tmio_sd_priv *priv,
550 unsigned int divisor;
556 divisor = DIV_ROUND_UP(priv->mclk, mmc->clock);
559 val = (priv->caps & TMIO_SD_CAP_RCAR) ?
560 TMIO_SD_CLKCTL_RCAR_DIV1 : TMIO_SD_CLKCTL_DIV1;
561 else if (divisor <= 2)
562 val = TMIO_SD_CLKCTL_DIV2;
563 else if (divisor <= 4)
564 val = TMIO_SD_CLKCTL_DIV4;
565 else if (divisor <= 8)
566 val = TMIO_SD_CLKCTL_DIV8;
567 else if (divisor <= 16)
568 val = TMIO_SD_CLKCTL_DIV16;
569 else if (divisor <= 32)
570 val = TMIO_SD_CLKCTL_DIV32;
571 else if (divisor <= 64)
572 val = TMIO_SD_CLKCTL_DIV64;
573 else if (divisor <= 128)
574 val = TMIO_SD_CLKCTL_DIV128;
575 else if (divisor <= 256)
576 val = TMIO_SD_CLKCTL_DIV256;
577 else if (divisor <= 512 || !(priv->caps & TMIO_SD_CAP_DIV1024))
578 val = TMIO_SD_CLKCTL_DIV512;
580 val = TMIO_SD_CLKCTL_DIV1024;
582 tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
583 if (tmp & TMIO_SD_CLKCTL_SCLKEN &&
584 (tmp & TMIO_SD_CLKCTL_DIV_MASK) == val)
587 /* stop the clock before changing its rate to avoid a glitch signal */
588 tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
589 tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
591 tmp &= ~TMIO_SD_CLKCTL_DIV_MASK;
592 tmp |= val | TMIO_SD_CLKCTL_OFFEN;
593 tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
595 tmp |= TMIO_SD_CLKCTL_SCLKEN;
596 tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
601 static void tmio_sd_set_pins(struct udevice *dev)
603 __maybe_unused struct mmc *mmc = mmc_get_mmc_dev(dev);
605 #ifdef CONFIG_DM_REGULATOR
606 struct tmio_sd_priv *priv = dev_get_priv(dev);
608 if (priv->vqmmc_dev) {
609 if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
610 regulator_set_value(priv->vqmmc_dev, 1800000);
612 regulator_set_value(priv->vqmmc_dev, 3300000);
613 regulator_set_enable(priv->vqmmc_dev, true);
617 #ifdef CONFIG_PINCTRL
618 switch (mmc->selected_mode) {
625 pinctrl_select_state(dev, "default");
633 pinctrl_select_state(dev, "state_uhs");
641 int tmio_sd_set_ios(struct udevice *dev)
643 struct tmio_sd_priv *priv = dev_get_priv(dev);
644 struct mmc *mmc = mmc_get_mmc_dev(dev);
647 dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n",
648 mmc->clock, mmc->ddr_mode, mmc->bus_width);
650 ret = tmio_sd_set_bus_width(priv, mmc);
653 tmio_sd_set_ddr_mode(priv, mmc);
654 tmio_sd_set_clk_rate(priv, mmc);
655 tmio_sd_set_pins(dev);
660 int tmio_sd_get_cd(struct udevice *dev)
662 struct tmio_sd_priv *priv = dev_get_priv(dev);
664 if (priv->caps & TMIO_SD_CAP_NONREMOVABLE)
667 return !!(tmio_sd_readl(priv, TMIO_SD_INFO1) &
671 static void tmio_sd_host_init(struct tmio_sd_priv *priv)
675 /* soft reset of the host */
676 tmp = tmio_sd_readl(priv, TMIO_SD_SOFT_RST);
677 tmp &= ~TMIO_SD_SOFT_RST_RSTX;
678 tmio_sd_writel(priv, tmp, TMIO_SD_SOFT_RST);
679 tmp |= TMIO_SD_SOFT_RST_RSTX;
680 tmio_sd_writel(priv, tmp, TMIO_SD_SOFT_RST);
682 /* FIXME: implement eMMC hw_reset */
684 tmio_sd_writel(priv, TMIO_SD_STOP_SEC, TMIO_SD_STOP);
687 * Connected to 32bit AXI.
688 * This register dropped backward compatibility at version 0x10.
689 * Write an appropriate value depending on the IP version.
691 if (priv->version >= 0x10)
692 tmio_sd_writel(priv, 0x101, TMIO_SD_HOST_MODE);
694 tmio_sd_writel(priv, 0x0, TMIO_SD_HOST_MODE);
696 if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL) {
697 tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE);
698 tmp |= TMIO_SD_DMA_MODE_ADDR_INC;
699 tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE);
703 int tmio_sd_bind(struct udevice *dev)
705 struct tmio_sd_plat *plat = dev_get_platdata(dev);
707 return mmc_bind(dev, &plat->mmc, &plat->cfg);
710 int tmio_sd_probe(struct udevice *dev, u32 quirks)
712 struct tmio_sd_plat *plat = dev_get_platdata(dev);
713 struct tmio_sd_priv *priv = dev_get_priv(dev);
714 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
718 base = devfdt_get_addr(dev);
719 if (base == FDT_ADDR_T_NONE)
722 priv->regbase = devm_ioremap(dev, base, SZ_2K);
726 #ifdef CONFIG_DM_REGULATOR
727 device_get_supply_regulator(dev, "vqmmc-supply", &priv->vqmmc_dev);
730 ret = mmc_of_parse(dev, &plat->cfg);
732 dev_err(dev, "failed to parse host caps\n");
736 plat->cfg.name = dev->name;
737 plat->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
742 priv->version = tmio_sd_readl(priv, TMIO_SD_VERSION) &
744 dev_dbg(dev, "version %x\n", priv->version);
745 if (priv->version >= 0x10) {
746 priv->caps |= TMIO_SD_CAP_DMA_INTERNAL;
747 priv->caps |= TMIO_SD_CAP_DIV1024;
750 if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable",
752 priv->caps |= TMIO_SD_CAP_NONREMOVABLE;
754 tmio_sd_host_init(priv);
756 plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
757 plat->cfg.f_min = priv->mclk /
758 (priv->caps & TMIO_SD_CAP_DIV1024 ? 1024 : 512);
759 plat->cfg.f_max = priv->mclk;
760 plat->cfg.b_max = U32_MAX; /* max value of TMIO_SD_SECCNT */
762 upriv->mmc = &plat->mmc;