Tegra2: mmc: Support DMA restarts at buffer boundaries
[platform/kernel/u-boot.git] / drivers / mmc / tegra2_mmc.c
1 /*
2  * (C) Copyright 2009 SAMSUNG Electronics
3  * Minkyu Kang <mk7.kang@samsung.com>
4  * Jaehoon Chung <jh80.chung@samsung.com>
5  * Portions Copyright 2011 NVIDIA Corporation
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
20  */
21
22 #include <common.h>
23 #include <mmc.h>
24 #include <asm/io.h>
25 #include <asm/arch/clk_rst.h>
26 #include <asm/arch/clock.h>
27 #include "tegra2_mmc.h"
28
29 /* support 4 mmc hosts */
30 struct mmc mmc_dev[4];
31 struct mmc_host mmc_host[4];
32
33
34 /**
35  * Get the host address and peripheral ID for a device. Devices are numbered
36  * from 0 to 3.
37  *
38  * @param host          Structure to fill in (base, reg, mmc_id)
39  * @param dev_index     Device index (0-3)
40  */
41 static void tegra2_get_setup(struct mmc_host *host, int dev_index)
42 {
43         debug("tegra2_get_base_mmc: dev_index = %d\n", dev_index);
44
45         switch (dev_index) {
46         case 1:
47                 host->base = TEGRA2_SDMMC3_BASE;
48                 host->mmc_id = PERIPH_ID_SDMMC3;
49                 break;
50         case 2:
51                 host->base = TEGRA2_SDMMC2_BASE;
52                 host->mmc_id = PERIPH_ID_SDMMC2;
53                 break;
54         case 3:
55                 host->base = TEGRA2_SDMMC1_BASE;
56                 host->mmc_id = PERIPH_ID_SDMMC1;
57                 break;
58         case 0:
59         default:
60                 host->base = TEGRA2_SDMMC4_BASE;
61                 host->mmc_id = PERIPH_ID_SDMMC4;
62                 break;
63         }
64
65         host->reg = (struct tegra2_mmc *)host->base;
66 }
67
68 static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data)
69 {
70         unsigned char ctrl;
71
72         debug("data->dest: %08X, data->blocks: %u, data->blocksize: %u\n",
73         (u32)data->dest, data->blocks, data->blocksize);
74
75         writel((u32)data->dest, &host->reg->sysad);
76         /*
77          * DMASEL[4:3]
78          * 00 = Selects SDMA
79          * 01 = Reserved
80          * 10 = Selects 32-bit Address ADMA2
81          * 11 = Selects 64-bit Address ADMA2
82          */
83         ctrl = readb(&host->reg->hostctl);
84         ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK;
85         ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA;
86         writeb(ctrl, &host->reg->hostctl);
87
88         /* We do not handle DMA boundaries, so set it to max (512 KiB) */
89         writew((7 << 12) | (data->blocksize & 0xFFF), &host->reg->blksize);
90         writew(data->blocks, &host->reg->blkcnt);
91 }
92
93 static void mmc_set_transfer_mode(struct mmc_host *host, struct mmc_data *data)
94 {
95         unsigned short mode;
96         debug(" mmc_set_transfer_mode called\n");
97         /*
98          * TRNMOD
99          * MUL1SIN0[5]  : Multi/Single Block Select
100          * RD1WT0[4]    : Data Transfer Direction Select
101          *      1 = read
102          *      0 = write
103          * ENACMD12[2]  : Auto CMD12 Enable
104          * ENBLKCNT[1]  : Block Count Enable
105          * ENDMA[0]     : DMA Enable
106          */
107         mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE |
108                 TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE);
109
110         if (data->blocks > 1)
111                 mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT;
112
113         if (data->flags & MMC_DATA_READ)
114                 mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ;
115
116         writew(mode, &host->reg->trnmod);
117 }
118
119 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
120                         struct mmc_data *data)
121 {
122         struct mmc_host *host = (struct mmc_host *)mmc->priv;
123         int flags, i;
124         unsigned int timeout;
125         unsigned int mask;
126         unsigned int retry = 0x100000;
127         debug(" mmc_send_cmd called\n");
128
129         /* Wait max 10 ms */
130         timeout = 10;
131
132         /*
133          * PRNSTS
134          * CMDINHDAT[1] : Command Inhibit (DAT)
135          * CMDINHCMD[0] : Command Inhibit (CMD)
136          */
137         mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD;
138         if ((data != NULL) || (cmd->resp_type & MMC_RSP_BUSY))
139                 mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT;
140
141         /*
142          * We shouldn't wait for data inhibit for stop commands, even
143          * though they might use busy signaling
144          */
145         if (data)
146                 mask &= ~TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT;
147
148         while (readl(&host->reg->prnsts) & mask) {
149                 if (timeout == 0) {
150                         printf("%s: timeout error\n", __func__);
151                         return -1;
152                 }
153                 timeout--;
154                 udelay(1000);
155         }
156
157         if (data)
158                 mmc_prepare_data(host, data);
159
160         debug("cmd->arg: %08x\n", cmd->cmdarg);
161         writel(cmd->cmdarg, &host->reg->argument);
162
163         if (data)
164                 mmc_set_transfer_mode(host, data);
165
166         if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
167                 return -1;
168
169         /*
170          * CMDREG
171          * CMDIDX[13:8] : Command index
172          * DATAPRNT[5]  : Data Present Select
173          * ENCMDIDX[4]  : Command Index Check Enable
174          * ENCMDCRC[3]  : Command CRC Check Enable
175          * RSPTYP[1:0]
176          *      00 = No Response
177          *      01 = Length 136
178          *      10 = Length 48
179          *      11 = Length 48 Check busy after response
180          */
181         if (!(cmd->resp_type & MMC_RSP_PRESENT))
182                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE;
183         else if (cmd->resp_type & MMC_RSP_136)
184                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136;
185         else if (cmd->resp_type & MMC_RSP_BUSY)
186                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY;
187         else
188                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48;
189
190         if (cmd->resp_type & MMC_RSP_CRC)
191                 flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK;
192         if (cmd->resp_type & MMC_RSP_OPCODE)
193                 flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK;
194         if (data)
195                 flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER;
196
197         debug("cmd: %d\n", cmd->cmdidx);
198
199         writew((cmd->cmdidx << 8) | flags, &host->reg->cmdreg);
200
201         for (i = 0; i < retry; i++) {
202                 mask = readl(&host->reg->norintsts);
203                 /* Command Complete */
204                 if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) {
205                         if (!data)
206                                 writel(mask, &host->reg->norintsts);
207                         break;
208                 }
209         }
210
211         if (i == retry) {
212                 printf("%s: waiting for status update\n", __func__);
213                 return TIMEOUT;
214         }
215
216         if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) {
217                 /* Timeout Error */
218                 debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
219                 return TIMEOUT;
220         } else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
221                 /* Error Interrupt */
222                 debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
223                 return -1;
224         }
225
226         if (cmd->resp_type & MMC_RSP_PRESENT) {
227                 if (cmd->resp_type & MMC_RSP_136) {
228                         /* CRC is stripped so we need to do some shifting. */
229                         for (i = 0; i < 4; i++) {
230                                 unsigned int offset =
231                                         (unsigned int)(&host->reg->rspreg3 - i);
232                                 cmd->response[i] = readl(offset) << 8;
233
234                                 if (i != 3) {
235                                         cmd->response[i] |=
236                                                 readb(offset - 1);
237                                 }
238                                 debug("cmd->resp[%d]: %08x\n",
239                                                 i, cmd->response[i]);
240                         }
241                 } else if (cmd->resp_type & MMC_RSP_BUSY) {
242                         for (i = 0; i < retry; i++) {
243                                 /* PRNTDATA[23:20] : DAT[3:0] Line Signal */
244                                 if (readl(&host->reg->prnsts)
245                                         & (1 << 20))    /* DAT[0] */
246                                         break;
247                         }
248
249                         if (i == retry) {
250                                 printf("%s: card is still busy\n", __func__);
251                                 return TIMEOUT;
252                         }
253
254                         cmd->response[0] = readl(&host->reg->rspreg0);
255                         debug("cmd->resp[0]: %08x\n", cmd->response[0]);
256                 } else {
257                         cmd->response[0] = readl(&host->reg->rspreg0);
258                         debug("cmd->resp[0]: %08x\n", cmd->response[0]);
259                 }
260         }
261
262         if (data) {
263                 while (1) {
264                         mask = readl(&host->reg->norintsts);
265
266                         if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
267                                 /* Error Interrupt */
268                                 writel(mask, &host->reg->norintsts);
269                                 printf("%s: error during transfer: 0x%08x\n",
270                                                 __func__, mask);
271                                 return -1;
272                         } else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) {
273                                 /*
274                                  * DMA Interrupt, restart the transfer where
275                                  * it was interrupted.
276                                  */
277                                 unsigned int address = readl(&host->reg->sysad);
278
279                                 debug("DMA end\n");
280                                 writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT,
281                                        &host->reg->norintsts);
282                                 writel(address, &host->reg->sysad);
283                         } else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) {
284                                 /* Transfer Complete */
285                                 debug("r/w is done\n");
286                                 break;
287                         }
288                 }
289                 writel(mask, &host->reg->norintsts);
290         }
291
292         udelay(1000);
293         return 0;
294 }
295
296 static void mmc_change_clock(struct mmc_host *host, uint clock)
297 {
298         int div;
299         unsigned short clk;
300         unsigned long timeout;
301
302         debug(" mmc_change_clock called\n");
303
304         /*
305          * Change Tegra2 SDMMCx clock divisor here. Source is 216MHz,
306          * PLLP_OUT0
307          */
308         if (clock == 0)
309                 goto out;
310         clock_adjust_periph_pll_div(host->mmc_id, CLOCK_ID_PERIPH, clock,
311                                     &div);
312         debug("div = %d\n", div);
313
314         writew(0, &host->reg->clkcon);
315
316         /*
317          * CLKCON
318          * SELFREQ[15:8]        : base clock divided by value
319          * ENSDCLK[2]           : SD Clock Enable
320          * STBLINTCLK[1]        : Internal Clock Stable
321          * ENINTCLK[0]          : Internal Clock Enable
322          */
323         div >>= 1;
324         clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) |
325                TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE);
326         writew(clk, &host->reg->clkcon);
327
328         /* Wait max 10 ms */
329         timeout = 10;
330         while (!(readw(&host->reg->clkcon) &
331                  TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) {
332                 if (timeout == 0) {
333                         printf("%s: timeout error\n", __func__);
334                         return;
335                 }
336                 timeout--;
337                 udelay(1000);
338         }
339
340         clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
341         writew(clk, &host->reg->clkcon);
342
343         debug("mmc_change_clock: clkcon = %08X\n", clk);
344
345 out:
346         host->clock = clock;
347 }
348
349 static void mmc_set_ios(struct mmc *mmc)
350 {
351         struct mmc_host *host = mmc->priv;
352         unsigned char ctrl;
353         debug(" mmc_set_ios called\n");
354
355         debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
356
357         /* Change clock first */
358         mmc_change_clock(host, mmc->clock);
359
360         ctrl = readb(&host->reg->hostctl);
361
362         /*
363          * WIDE8[5]
364          * 0 = Depend on WIDE4
365          * 1 = 8-bit mode
366          * WIDE4[1]
367          * 1 = 4-bit mode
368          * 0 = 1-bit mode
369          */
370         if (mmc->bus_width == 8)
371                 ctrl |= (1 << 5);
372         else if (mmc->bus_width == 4)
373                 ctrl |= (1 << 1);
374         else
375                 ctrl &= ~(1 << 1);
376
377         writeb(ctrl, &host->reg->hostctl);
378         debug("mmc_set_ios: hostctl = %08X\n", ctrl);
379 }
380
381 static void mmc_reset(struct mmc_host *host)
382 {
383         unsigned int timeout;
384         debug(" mmc_reset called\n");
385
386         /*
387          * RSTALL[0] : Software reset for all
388          * 1 = reset
389          * 0 = work
390          */
391         writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &host->reg->swrst);
392
393         host->clock = 0;
394
395         /* Wait max 100 ms */
396         timeout = 100;
397
398         /* hw clears the bit when it's done */
399         while (readb(&host->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) {
400                 if (timeout == 0) {
401                         printf("%s: timeout error\n", __func__);
402                         return;
403                 }
404                 timeout--;
405                 udelay(1000);
406         }
407 }
408
409 static int mmc_core_init(struct mmc *mmc)
410 {
411         struct mmc_host *host = (struct mmc_host *)mmc->priv;
412         unsigned int mask;
413         debug(" mmc_core_init called\n");
414
415         mmc_reset(host);
416
417         host->version = readw(&host->reg->hcver);
418         debug("host version = %x\n", host->version);
419
420         /* mask all */
421         writel(0xffffffff, &host->reg->norintstsen);
422         writel(0xffffffff, &host->reg->norintsigen);
423
424         writeb(0xe, &host->reg->timeoutcon);    /* TMCLK * 2^27 */
425         /*
426          * NORMAL Interrupt Status Enable Register init
427          * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
428          * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
429          * [3] ENSTADMAINT   : DMA boundary interrupt
430          * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
431          * [0] ENSTACMDCMPLT : Command Complete Status Enable
432         */
433         mask = readl(&host->reg->norintstsen);
434         mask &= ~(0xffff);
435         mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE |
436                  TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE |
437                  TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT |
438                  TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY |
439                  TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY);
440         writel(mask, &host->reg->norintstsen);
441
442         /*
443          * NORMAL Interrupt Signal Enable Register init
444          * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
445          */
446         mask = readl(&host->reg->norintsigen);
447         mask &= ~(0xffff);
448         mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE;
449         writel(mask, &host->reg->norintsigen);
450
451         return 0;
452 }
453
454 static int tegra2_mmc_initialize(int dev_index, int bus_width)
455 {
456         struct mmc_host *host;
457         struct mmc *mmc;
458
459         debug(" mmc_initialize called\n");
460
461         host = &mmc_host[dev_index];
462
463         host->clock = 0;
464         tegra2_get_setup(host, dev_index);
465
466         clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000);
467
468         mmc = &mmc_dev[dev_index];
469
470         sprintf(mmc->name, "Tegra2 SD/MMC");
471         mmc->priv = host;
472         mmc->send_cmd = mmc_send_cmd;
473         mmc->set_ios = mmc_set_ios;
474         mmc->init = mmc_core_init;
475
476         mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
477         if (bus_width == 8)
478                 mmc->host_caps = MMC_MODE_8BIT;
479         else
480                 mmc->host_caps = MMC_MODE_4BIT;
481         mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC;
482
483         /*
484          * min freq is for card identification, and is the highest
485          *  low-speed SDIO card frequency (actually 400KHz)
486          * max freq is highest HS eMMC clock as per the SD/MMC spec
487          *  (actually 52MHz)
488          * Both of these are the closest equivalents w/216MHz source
489          *  clock and Tegra2 SDMMC divisors.
490          */
491         mmc->f_min = 375000;
492         mmc->f_max = 48000000;
493
494         mmc_register(mmc);
495
496         return 0;
497 }
498
499 int tegra2_mmc_init(int dev_index, int bus_width)
500 {
501         debug(" tegra2_mmc_init: index %d, bus width %d\n",
502                 dev_index, bus_width);
503         return tegra2_mmc_initialize(dev_index, bus_width);
504 }